JP2003298078A - Photoelectromotive element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a photoelectromotive element such as a solar cell or the like that is superior in electric characteristics such as power generation efficiency or the like, by adopting a low-temperature process to keep a semiconductor substrate with a long carrier life time and high quality. <P>SOLUTION: A rear-side joint type solar cell is provided with a PN joint and an electrode on the opposite surface to the light incident surface of a semiconductor substrate 11, and it is also provided with an intrinsic semiconductor film 12 of ≥0.1 nm and ≤50 nm in thickness, P- an N-type conductive semiconductor layers 13 and 14 thereon, and electrodes 15 and 16 thereon, on the entire surface with the PN joint. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photovoltaic element such as a back junction solar cell having a PN junction and positive and negative electrodes arranged on the surface opposite to the light incident surface.

[0002]

2. Description of the Related Art Many of the solar cells that are industrially produced in large quantities use amorphous silicon materials. However, such a solar cell has a problem that the production cost is low but the power generation efficiency is low. Therefore, for this improvement, a silicon single crystal or polycrystalline substrate is coated with an amorphous silicon film having a conductivity type opposite to that of the substrate, and PN is formed.
Efforts have been made to form junctions and thereby improve photovoltaic conversion efficiency.

When a junction is formed by combining such a crystalline silicon substrate and an amorphous silicon film, recombination of photogenerated carriers occurs at the interface between different types of semiconductor layers due to the existence of the interface order. There was a problem that it was difficult to achieve the expected performance. In order to solve such a problem, an attempt has been made to reduce the order of interfaces by forming an intrinsic amorphous semiconductor film at the interface between the crystalline silicon substrate and the amorphous silicon film.

Further, generally, a solar cell is provided with a transparent electrode on the light incident surface side and takes out a photoelectromotive force between the light incident surface and an electrode provided on the opposite surface. For this reason, there is a problem that light is blocked by the transparent electrode provided on the light incident surface side, which limits the power generation efficiency. In order to avoid such problems, do not arrange a transparent electrode on the light incident surface side,
A PN junction is formed in the vicinity of the side opposite to the light incident surface of the substrate,
There is known a back surface junction solar cell in which electrodes respectively connected to the P layer and the N layer are arranged, and the P layers and the N layers are alternately arranged in a comb tooth shape.

However, in the back junction solar cell, since carriers generated near the front surface of the semiconductor substrate reach the PN junction disposed near the back surface of the substrate, a high quality crystalline semiconductor having a large carrier lifetime. A substrate is needed. However, since a high temperature process such as thermal oxidation and thermal diffusion is required in the manufacturing process of the back junction solar cell, there is a problem that the carrier lifetime is deteriorated and it is difficult to obtain expected performance such as power generation efficiency.

[0006]

The present invention has been made in view of the above-mentioned circumstances, and by using a low-temperature treatment process, the state of a high-quality semiconductor substrate having a large carrier lifetime is maintained. An object is to provide a photovoltaic element such as a solar cell having high power generation efficiency.

[0007]

The photovoltaic element of the present invention is a back junction solar cell in which a PN junction and an electrode are formed on the surface of the semiconductor substrate opposite to the light incident surface, and the surface on which the PN junction is formed. An intrinsic semiconductor film having a thickness of 0.1 nm or more and 50 nm or less, a P-type and N-type conductive semiconductor layer on the film, and an electrode provided on the semiconductor layer To do. Here, it is preferable that the electrodes provided on the P-type and N-type conductive semiconductor layers are alternately arranged in a comb-like shape.

The intrinsic semiconductor film is preferably formed by plasma CVD or catalytic CVD, and particularly preferably catalytic CVD. Further, a layer having a conductivity type opposite to that of the substrate may be provided on the light incident surface side of the semiconductor substrate.

An intrinsic semiconductor film is formed by using plasma CVD or catalytic CVD, and junctions and electrodes alternately arranged in the shape of P-type and N-type comb teeth are formed on the intrinsic semiconductor film by a low temperature treatment process. By doing so, the carrier lifetime of the semiconductor substrate can be maintained in a high state. Thereby, good photoelectric conversion efficiency such as high power generation efficiency as the back surface junction type photovoltaic element can be obtained. In particular,
By using the catalytic CVD, it is possible to maintain the substrate in a high quality state, and it is possible to relatively increase the productivity of film formation.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a photovoltaic device according to an embodiment of the present invention. This photovoltaic element is a solar cell, for example, a back surface junction solar cell in which a PN junction and an electrode are arranged on the rear surface side of the N-type crystalline semiconductor substrate 11. The crystalline semiconductor substrate 11 is, for example, a N-type impurity-doped silicon single crystal substrate made of a dendritic web having a thickness of about 100 μm, and the intrinsic semiconductor film 12 is provided on the back surface side. Further, ribbon polycrystal may be used as the crystalline semiconductor substrate 11.

The single crystal or polycrystalline silicon substrate is
A thin band-shaped (sheet-shaped) crystal can be grown and produced by pulling a seed crystal from a crucible obtained by melting a silicon raw material adjusted to a predetermined temperature along a crystal axis of a predetermined orientation. That is, a long crystal can be continuously pulled up by sandwiching this crystal between endless belts and pulling it up. Then, a thin band-shaped crystal is cut into an appropriate size to obtain a rectangular sheet-shaped single crystal or polycrystalline silicon substrate having a thickness of 150 μm or less. For details, see Japanese Patent Application No. 2000-27531 of the applicant.
See issue 5.

The intrinsic semiconductor film 12 is an extremely thin amorphous layer having a thickness of 0.1 nm or more and 50 nm or less. The intrinsic semiconductor film is an amorphous silicon film, a heterostructure film of amorphous silicon and a microcrystalline silicon film, an amorphous silicon carbide film, or a heterostructure of an amorphous silicon carbide film and a microcrystalline silicon film. A film or the like. This intrinsic semiconductor film is an electrically neutral film, and by sandwiching this film between PN junctions, there is a hydrogen passivation effect, and it is possible to improve electrical characteristics such as an increase in open circuit voltage.

The intrinsic semiconductor film 12 is preferably formed by catalytic CVD or plasma CVD. Catalyst CV
As shown in FIG. 2A, the method D includes a gas supply system device 21, a high temperature catalyst 22, a film formation target substrate 23, a substrate holder 24, and the like in a vacuum container capable of depressurizing. Here, the high temperature catalyst 22 is made of a wire material such as tungsten or molybdenum.
It is heated to 00 to 2400 ° C. to activate the target gas to form a vapor phase growth film on the surface of the substrate 23. On the other hand, the plasma CVD apparatus shown in FIG.
By supplying a high-frequency voltage from the high-frequency power source 27 between the electrodes 25 and 26, the gas molecules 28 to be film-formed are made to be plasma and vibrated in the direction of the arrow in the figure, whereby the gas molecules 28 to be film-formed on the surface of the substrate 23 to be film-formed. It forms a vapor growth film.
Compared with the plasma CVD method shown in FIG. 3B, the catalytic CVD method shown in FIG. 3A has substantially no plasma damage to the film formation target substrate, has a simple device structure, and has a low cost. It has the features that it can be easily scaled up. In particular, the film formation rate is, for example, 5 to 10 n.
A relatively high value of about m / sec, and a film of high quality can be obtained in a relatively short time by forming an amorphous silicon film or a microcrystalline silicon film.

On the surface of the intrinsic semiconductor film 12, a P-type impurity-doped conductive semiconductor layer 13 and an N-type impurity-doped conductive semiconductor layer 14 are alternately arranged. The semiconductor layers 13 and 14 are amorphous conductive silicon layers formed by catalytic CVD or plasma CVD using a metal mask, for example. Semiconductor layer 1
Electrodes 15 and 16 are arranged on 3 and 14, respectively. The electrodes 15 and 16 are formed, for example, by patterning a conductive paste such as silver by screen printing, and heating and curing the pattern. The P-type and N-type impurity-doped semiconductor layers 13 and 14 are insulated from each other by an insulating film 17 such as a polyimide resin film. An antireflection film 18 made of SiN is arranged on the light incident surface side of the semiconductor substrate 11.

FIG. 3 is a diagram schematically showing the back surface side of this solar cell, in which an electrode 15 connected to the P-type semiconductor layer 13 is formed.
And electrodes 16 connected to the N-type semiconductor layer 14 are alternately arranged in a comb-like shape and arranged in parallel with each other. A large number of comb tooth-shaped electrodes 15 are connected to a bus bar portion 15a that is a base thereof, and a large number of comb tooth-shaped electrodes 16 are connected to a bus bar portion 16a that is a base thereof. Therefore, the electromotive force of this solar cell is taken out between the electrodes 15a and 16a of the bus bar.

Next, the structural features of this solar cell will be described. This solar cell is provided with a thin amorphous intrinsic silicon layer (semiconductor film) 12 formed by catalytic CVD or plasma CVD on the back surface side of a substrate 11, and P-type and N-type formed by catalytic CVD or plasma CVD on the surface thereof.
The semiconductor layers 13 and 14 in which the mold is doped with impurities are provided. Therefore, the intrinsic semiconductor film 12 and the conductive semiconductor layer 13,
Both 14 use a film formed by a low temperature process such as catalytic CVD or plasma CVD. The insulating film 17 and the electrodes 15 and 16 are also formed by screen-printing or the like to form a coating film pattern, which is then heated and cured at a relatively low temperature of less than 400 ° C. Therefore, since the film is formed by the low temperature treatment of less than 400 ° C. in all the processes, the semiconductor substrate 1
In No. 1, it is possible to maintain a high quality state with a large carrier lifetime. Further, since the transparent electrode does not exist on the surface side, shielding loss due to this does not occur, and good photoelectric conversion characteristics such as high power generation efficiency can be obtained.

The intrinsic semiconductor film 12 and the P-type and N-type conductive semiconductor layers 13 and 14 are preferably formed by catalytic CVD. In the catalytic CVD, the substrate temperature is about 100 to 400 ° C., and the semiconductor substrate 11 is not damaged because it is a low temperature process. Further, the presence of high-concentration hydrogen radicals has a feature that defects inside the crystal can be repaired and the defect rank density can be reduced. Further, unlike plasma CVD, since it is not damaged by plasma, it can contribute to maintaining the carrier lifetime of the semiconductor substrate 11.

FIG. 4 shows a photovoltaic device according to another embodiment of the present invention. In this embodiment, the intrinsic semiconductor film 20 is also provided on the light incident surface side of the substrate 11. Other configurations are similar to those of the first embodiment shown in FIG. Here, the intrinsic semiconductor film 20 is the intrinsic semiconductor film 1 on the back surface side of the substrate.
It is preferable to form both the front and back surfaces and the side surface of the substrate 11 at the same time as 2. As a result, the light incident surface side and the side surface of the crystalline silicon substrate 11 are covered with the intrinsic semiconductor film, so that the interface order can be reduced and the electrical characteristics can be improved.

FIG. 5 shows a photovoltaic device according to still another embodiment of the present invention. In this embodiment, a layer 21 having a conductivity type opposite to that of the substrate 11 is provided on the light incident surface side of the substrate 11. This layer 21 is a P-type layer having a conductivity type opposite to that of the N-type semiconductor substrate 11, and has a function of preventing carrier recombination by utilizing an internal electric field of the substrate by charges of the opposite conductivity type. This makes it possible to improve electrical characteristics such as photoelectric conversion efficiency.

Next, a method of manufacturing the photovoltaic element of the present invention will be described with reference to FIG. First, as shown in FIG. 6A, an N-type single crystal or polycrystalline silicon substrate 11 is formed.
To prepare. This can use dendritic web crystals or ribbon polycrystals as described above. Then, cleaning is performed to remove the oxide film and the like adhering to the surface,
Keep the surface clean. Next, as shown in FIG. 6B, the non-crystalline intrinsic silicon films 12, 20 are formed by catalytic CVD.
Are formed on both front and back surfaces of the substrate 11. This thickness is 0.1
nm or more and 50 nm or less is preferable, but as an example, 10 n
It is formed to about m. An example of conditions for forming this amorphous intrinsic silicon film is as follows. Gas flow rate: SiH ₄ = 20 sccm Gas ratio: SiH ₄ / H ₂ = 1: 10 Film formation pressure: 1 Pa Substrate temperature: 250 ° C. Filament temperature: 1800 ° C.

Next, as shown in FIG. 6 (c), the catalyst CV is used.
The amorphous conductive silicon layer 13 is formed by D. Here, the conductive silicon layer 13 is P-type, and has a film thickness of 3
It is about 0 nm. This P-type amorphous silicon layer has a gas flow rate: SiH ₄ = 20 sccm, B ₂ H ₆ = 1 sc.
cm (1%, diluted with H ₂ ), gas ratio: SiH ₄ / H ₂ = 1: 10, film formation pressure: 1 Pa, substrate temperature: 250 ° C., filament temperature: 1800 ° C.

Next, as shown in FIG. 6D, an N type amorphous conductive silicon layer 14 is formed. Similarly, a large number of parallel patterns are formed between the conductive silicon layers 13 using a metal mask so as to be interleaved in the shape of comb teeth. The film thickness is, for example, about 30 nm. The conditions are as follows: gas flow rate: SiH ₄ = 20 sccm, PH ₃ = 1 scc
m (1%, diluted with H ₂ ), gas ratio: SiH ₄ / H ₂ = 1: 10, film forming pressure: 1 Pa, substrate temperature: 250 ° C., filament temperature: 1800 ° C.

Next, as shown in FIG. 6 (e), the protective film 1
Form 7. The conductive silicon layer 13, for example, is formed by screen-printing a polyimide resin paste, etc.
It is formed by embedding between 14 and heating and curing at a temperature of 250 ° C. or less. By forming this protective film 17, weather resistance and soldering resistance are improved. And
As shown in FIG. 6 (f), for example, silver paste is applied by screen printing, and this is similarly heat-cured at a relatively low temperature of 250 ° C. or lower, so that the teeth of the comb shown in FIG. 3 alternate. Interposed electrode patterns 15, 16, 15a, 1
6a is formed.

In the above process, although not shown, it is preferable to form an antireflection film on the surface of the substrate 11. The antireflection film is formed of, for example, Si by a high frequency sputtering method.
_{A 3} N ₄ film or the like is suitable, and is formed to have a film thickness of about 60 nm, for example. Further, as shown in FIG. 5, a diffusion layer having a conductivity type opposite to that of the substrate may be provided on the light incident surface side of the semiconductor substrate 11. This is preferably formed in advance on the semiconductor substrate 11 by a method such as thermal diffusion or ion implantation.

It should be noted that the above embodiment describes one mode of the embodiment of the present invention, and it is needless to say that various modified embodiments can be made without departing from the gist of the present invention.

[0027]

As described above, according to the present invention, it is possible to provide a photovoltaic element such as a back junction solar cell in which the semiconductor substrate has a large carrier lifetime and is excellent in electrical characteristics such as power generation efficiency.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a schematic configuration of a photovoltaic element according to an embodiment of the present invention.

FIG. 2A is a diagram showing a catalytic CVD method, and FIG.
FIG. 4 is a diagram showing a plasma CVD method.

FIG. 3 is a diagram showing an electrode configuration on the bottom surface of the photovoltaic element of FIG.

FIG. 4 is a sectional view showing a schematic configuration of a photovoltaic element according to another embodiment of the present invention.

FIG. 5 is a sectional view showing a schematic configuration of a photovoltaic element according to another embodiment of the present invention.

FIG. 6 is a diagram showing a manufacturing process of the photovoltaic element of the present invention.

[Explanation of symbols]

11 Crystalline semiconductor substrate 12,20 Intrinsic semiconductor film 13 P-type conductive silicon layer 14 N-type conductive silicon layer 15, 16 electrodes 17 Insulation layer 18 Antireflection film 21 Opposite conductivity type layer

Claims (9)

[Claims] 1. A PN is provided on a surface of a semiconductor substrate opposite to a light incident surface.
In a back surface junction type solar cell in which a junction and an electrode are formed, 0.1 nm or more and 50 n or more are formed on the entire surface forming the PN junction.
an intrinsic semiconductor film having a thickness of m or less, and P-type and N-type on the film.
A back junction type photovoltaic element comprising a conductive semiconductor layer of a positive type and an electrode provided on the semiconductor layer. 2. The photovoltaic element according to claim 1, wherein the electrodes provided on the P-type and N-type conductive semiconductor layers are alternately arranged in a comb-like shape. 3. The photovoltaic element according to claim 1, wherein the substrate is a single crystal semiconductor substrate or a polycrystalline semiconductor substrate. 4. Amorphous Si is used as the intrinsic semiconductor film.
The photovoltaic element according to claim 1, wherein a film, an amorphous Si / microcrystalline Si heterostructure film, an amorphous SiC film, or an amorphous SiC / microcrystalline Si heterostructure film is used. 5. The photovoltaic element according to claim 1, wherein the intrinsic semiconductor film is formed by using catalytic CVD. 6. The photovoltaic element according to claim 1, further comprising an antireflection film on a light incident surface of the semiconductor substrate. 7. The photovoltaic element according to claim 1, wherein a layer having a conductivity type opposite to that of the semiconductor substrate is provided on a light incident surface of the semiconductor substrate. 8. The photovoltaic device according to claim 1, wherein an intrinsic semiconductor film is provided on a light incident surface of the semiconductor substrate. 9. A semiconductor crystal substrate of one conductivity type is prepared, an intrinsic amorphous semiconductor film is deposited on at least one surface of the substrate, and a conductive semiconductor layer doped with impurities of P type and N type is formed on the film. A method for manufacturing a photovoltaic element, characterized in that the photovoltaic elements are arranged apart from each other.