JP2003298064A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the light resistance of a thin film transistor (TFT) using CG silicon films and to reduce off-current. <P>SOLUTION: Each of the channel layer 19a, source layer 19b, and drain layer 19c of the TFT formed on a quartz substrate 11 having an insulating surface is formed by laminating a p-type Si film 12 which is a first crystalline silicon film and a CG silicon film 13 which is a second crystalline silicon film upon another in this order. The thickness of the CG silicon film 13 is made thinner than that of the p-type Si film 12. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a thin film transistor for driving a liquid crystal of an active matrix liquid crystal display device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a thin liquid crystal display device driven with low power consumption, a thin film transistor (T
A liquid crystal display device using a (Hin Film Transistor: hereinafter referred to as a TFT) has high performance such as good image contrast and fast image signal response speed. It is used in the display section of portable TVs, etc., and its market size is growing significantly.

In such a TFT, a CG (Continuous Grain) silicon film may be used in an electrically active region of the TFT. The CG silicon film is
As disclosed in Japanese Patent Laid-Open No. 6-244103, an amorphous Si film (amorphous silicon film: a-
A silicon film with excellent crystallinity obtained by depositing a small amount of a catalytic element that promotes crystallization such as Ni (nickel) on the surface of (Si film), and then performing high-temperature treatment such as annealing treatment. is there.

The CG silicon film has a higher carrier mobility than the conventional a-Si film and polycrystalline silicon film (polysilicon film: hereinafter referred to as p-Si film).
Therefore, the CG silicon film is capable of driving with low power consumption and high-speed response of signals. In addition, since the CG silicon film has a high carrier mobility, it has a possibility of manufacturing a sheet computer using it in the future, and is a material for manufacturing a next-generation driver monolithic liquid crystal display device. Is seen as promising.

The CG silicon film is formed of a-Si as described above.
A metal element such as Ni that promotes crystallization is added to the film,
It is a crystalline silicon film formed by heating the a-Si film. The catalytic element such as Ni that promotes crystallization is necessary when the a-Si film is crystallized, but it should not be contained as much as an unnecessary impurity in the crystallized crystalline silicon film. Is desirable. Therefore, a method of removing the catalytic element such as Ni added in the crystalline silicon film has been actively studied.

For example, in Japanese Unexamined Patent Application Publication No. 10-223533, P (phosphorus) of a V group B element is doped at a high concentration in a partial region of the formed CG silicon film, and then heat treatment is performed to form P. N in the region doped with (phosphorus)
By moving (gettering) catalytic elements such as i, TFT
A method of removing the catalytic element from the active region of the is disclosed.

A TFT using such a CG silicon film
Has attracted attention as a device that can realize high density of pixels and high brightness of images, which are particularly required for a display device for projection, and development in this field has been actively conducted.

FIG. 3 is a structural sectional view of a semiconductor device having a TFT used in a general liquid crystal panel for projection. The semiconductor device shown in FIG. 3 has a peripheral drive circuit portion 40 and pixel portions 41 arranged in a matrix. Here, the TFT of the peripheral drive circuit section 40 is mainly formed of a CMOS transistor,
For simplification of description, only N-type MOS transistors are shown and P-type MOS transistors are omitted. Also,
The TFT of each pixel portion 41 is also formed by a MOS transistor.

The peripheral drive circuit section 40 and the pixel section 41 are
Both are formed on a transparent substrate 51 such as a glass substrate.
A source layer 52 and a drain layer 54, which are semiconductor layers of a source region and a drain region, each having a predetermined thickness are formed in a predetermined region on the transparent substrate 5 1. A channel layer 53, which is an active region, is formed in the semiconductor layer between the source layer 52 and the drain layer 54. A first silicon oxide film 55 is formed on the entire transparent substrate 51 so as to cover the source layer 52, the drain layer 54 and the channel layer 53 which form the MOS transistor. A first silicon oxide film 55 is formed on the channel layer 53.
The gate electrode 56 is formed through the first silicon oxide film 5 between the gate electrode 56 and the channel layer 53.
5 acts as a gate oxide film.

A second silicon oxide film 55a, which is an interlayer insulating film, is formed on the first silicon oxide film 55 of the peripheral drive circuit section 40 so as to cover the gate electrode 56. Contact holes are formed in the first silicon oxide film 55 and the second silicon oxide film 55a on the source layer 52 and the drain layer 54, respectively, so as to expose the surfaces of the source layer 52 and the drain layer 54, respectively. There is. An alloy layer is buried in each of the contact holes on the source layer 52 and the drain layer 54 so as to come into contact with the surfaces of the source layer 52 and the drain layer 54 to form a source electrode 58 and a drain electrode 59, respectively. As a result, an N-type MOS transistor is formed.

On the other hand, in the MOS transistor of the pixel portion 41, the drain layer 52 is laminated on the transparent substrate 51,
A first silicon oxide film 55 is formed on the drain layer 54.
The auxiliary capacitance line 57 is formed through the gate electrode 56
In addition, it is covered with a second silicon oxide film 55a. The drain electrode 59 is formed of the second silicon oxide film 5
It is formed on 5a so as to face a part of the auxiliary capacitance line 57. The other configuration of the MOS transistor of the pixel portion 41 is similar to that of the N-type MOS transistor of the peripheral drive circuit portion 1.

An interlayer film 55b formed of a nitride film is formed on the second silicon oxide film 55a so as to cover the source electrode 58 and the drain electrode 59. A pixel contact hole 63 is formed in a predetermined region of the interlayer film 55b on the drain electrode 59 of the MOS transistor of the pixel portion 41 so that the surface of the drain electrode 59 is exposed. Pixel contact hole 63 and interlayer film 55b
A pixel electrode 60 made of a transparent conductive film such as an ITO (Indium Tin Oxide) film is formed on the top of the pixel electrode 60 and is connected to the drain electrode 59 of the MOS transistor of the pixel portion 41. The pixel electrode 60 made of a transparent conductive film is arranged so as to cover the drain electrode 59, the gate electrode 56, etc. of the MOS transistor of the pixel portion 41.

[0013]

By the way, the liquid crystal panel for projection is required to have high brightness of an image and high density of pixels, which are the features of the liquid crystal panel, and as shown in FIG. Light with high intensity is incident on the TFT of the pixel portion 41.

In the material called silicon, when light is incident, photocarriers are generated by photoexcitation, and the photocarriers generate an electric potential. Therefore, for example, in an N-type MOS transistor, which is a TFT using silicon, a phenomenon occurs in which a current flows between the drain region and the source region even when the gate region is in the OFF state where no voltage is applied.

O of an N-type MOS transistor which is a TFT
When current flows between the drain region and the source region in the FF state, the voltage applied to the liquid crystal layer decreases due to a decrease in the charge in the drain region, and in the liquid crystal panel, the change in the liquid crystal display state over time and the liquid crystal display The quality of the state deteriorates.

Therefore, it is necessary for the TFT used in the pixel portion of the liquid crystal panel for projection to suppress the change of the liquid crystal display state with time and the deterioration of the liquid crystal display state, and the silicon film used for the TFT is It is necessary to have a property (hereinafter referred to as light resistance) in which photocarriers are less likely to be generated by photoexcitation when light is incident.

In general, the better the crystalline state of a silicon film, the easier the generation of photocarriers by photoexcitation.
For this reason, the TFT using the CG silicon film having an excellent crystalline state has a higher O than the TFT using the p-Si film.
The characteristics such as low-voltage driving and high-speed response in the N state are superior because the carrier mobility is large, but the characteristics in which the light resistance in the OFF state is important are inferior.

To solve such a problem, Japanese Patent Laid-Open No. 9-45
No. 931 discloses a TF of a pixel section and a peripheral drive circuit section.
Disclosed is a configuration of a semiconductor circuit used in a liquid crystal panel in which T is formed of a crystalline silicon film and a CG silicon film which are different from the CG silicon film, and a method of manufacturing the circuit.

However, in the structure of the semiconductor circuit and the method of manufacturing the circuit disclosed in Japanese Patent Laid-Open No. 9-45931, a catalyst element that promotes crystallization is added only to the a-Si film in the peripheral circuit region. And therefore a-Si
Since it is necessary to pattern the film, additional steps may be required, which may increase the manufacturing cost.

To solve the above problem, there is also a method of reducing the thickness of the semiconductor layer to be crystallized to suppress the generation of photocarriers by photoexcitation. The generation rate of photocarriers due to photoexcitation is proportional to the volume of the CG silicon film. If the volume of the CG silicon film is small, the generation rate of photocarriers due to photoexcitation also decreases, and the light resistance is inevitably improved.

In general, a TFT used for each pixel of a liquid crystal panel has an ON state and an OFF state of a channel region on a semiconductor layer (hereinafter referred to as a channel layer) which becomes a channel region via a gate insulating film. A gate electrode to be operated is formed. When a voltage is applied to this gate electrode, a current flows in the channel layer due to the electric field effect. In this case, most of the current flowing in the channel layer flows in the vicinity of the interface between the channel layer and the gate insulating film, and the thickness of the channel layer in which the current flows is about several nm from the interface between the channel layer and the gate insulating film.

As a result, the thickness of the semiconductor layer in the channel region of the TFT may be about 10 nm. Also, T
Unlike the current in the ON state (hereinafter, referred to as the ON current), the current in the FT in the OFF state (hereinafter, referred to as the OFF current) flows through the entire channel layer.
Reducing the thickness of the channel layer is also effective for reducing the OFF current of the TFT.

However, the TFT used in the liquid crystal panel
In the case of manufacturing a semiconductor layer in which the channel layer is formed, the semiconductor layer of the source region and the drain region (hereinafter,
A source layer and a drain layer) are also formed, and the source layer and the drain layer are electrically connected to the signal wiring and the pixel electrode, respectively. Therefore, as described above, when the thickness of the channel layer is about 10 nm, the contact resistance between the source layer and the drain layer and the signal wiring and the pixel electrode increases, and a sufficient voltage may not be applied to the pixel electrode. There is.

When contact holes are opened in the source layer and the drain layer for connecting the source layer and the signal electrode and for connecting the drain layer and the pixel electrode, the contact holes are formed on the source layer and the drain layer. Dry etching is performed on the insulating film to form a contact hole. In particular, since recent liquid crystal panels pursue higher image brightness and higher pixel apertures, dry etching is inevitably used instead of wet etching for forming contact holes. When dry etching is used to form the contact holes, it is difficult to set the etching ratio selection ratio between the insulating film such as a silicon oxide film and the CG silicon film used for the channel layer. Therefore, various kinds of etching gases have been studied for forming the contact hole by dry etching, but there is a possibility that the reduction in the thickness of the CG silicon film due to the etching of the contact hole portion cannot be completely prevented.

Further, since the insulating film in which the contact hole is formed is formed on the glass substrate for manufacturing the liquid crystal panel, the film thickness distribution of the insulating film varies.
Therefore, when the contact hole is formed by dry etching, the insulating film is overetched to some extent in order to expose the surface of the source layer and the drain layer in each TFT, and the CG silicon of the source layer and the drain layer is etched. As the film thickness decreases, the contact resistance between the source layer and the drain layer and the signal wiring and the pixel electrode, respectively, may increase.

As a result, the source layer forming the TFT,
The semiconductor layer forming the drain layer and the channel layer needs to have a certain thickness, which has an adverse effect on the improvement of the light resistance and the reduction of the OFF current of the TFT described above, and the TFT using the CG silicon film. Becomes a serious problem to.

The present invention is intended to solve such a problem, and an object thereof is to use a CG silicon film to form a TFT.
It is an object of the present invention to provide a semiconductor device capable of improving the light resistance of the device and reducing the OFF current, and simplifying the process, and a manufacturing method thereof.

[0028]

The semiconductor device of the present invention comprises:
A semiconductor device in which a plurality of thin film transistors are formed in a predetermined region on a substrate having an insulating surface, and the thin film transistor is provided with a drain layer, a source layer, and a channel layer, wherein the channel layer includes a first layer. The crystalline silicon film and the second crystalline silicon film are sequentially laminated.

The first crystalline silicon film is formed by subjecting the first amorphous silicon film to heat treatment, and the second crystalline silicon film is formed into a second amorphous silicon film. It is formed by performing heat treatment.

The thickness of the second crystalline silicon film is smaller than the thickness of the first crystalline silicon film.

An oxide film is formed between the first crystalline silicon film and the second crystalline silicon film.

The thickness of the oxide film is 1 nm or less.

A method of manufacturing a semiconductor device according to the present invention is the method of manufacturing a semiconductor device according to claim 1, wherein a first amorphous silicon film is formed on a substrate having an insulating surface,
A step of performing a heat treatment to form a first crystalline silicon film, a step of forming a second amorphous silicon film on the first crystalline silicon film, and a step of forming a second amorphous silicon film on the amorphous silicon film. A step of adding a catalytic metal that promotes crystal growth, a step of subjecting the amorphous silicon film to which the catalytic metal is added to a heat treatment to form a second crystalline silicon film, and a step of forming the first crystal. Forming a drain layer, a source layer and a channel layer by implanting ions into the crystalline silicon film and the second crystalline silicon film.

The removal of the catalyst metal is performed by adding a first element having an effect of selectively attracting the catalyst metal into the second crystalline silicon film, and heating the catalyst element to remove the catalyst element. The method includes moving to the region to which the first element has been added, and removing the region to which the first element has been added.

The catalyst metals are Fe, Co, Ni and P.
It is one or more kinds of elements selected from d, Pt, Cu, Au, In, and Sn.

The first element is a group V element.

The group V element is phosphorus (P).

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention. The semiconductor device shown in FIG. 1 has a peripheral drive circuit portion 1 and pixel portions 2 arranged in a matrix. Here, the TFT of the peripheral drive circuit unit 1
Are mainly formed of CMOS transistors, but only N-type MOS transistors are shown and P-type MOS transistors are omitted for simplification of description. The TFT of each pixel unit 2 is also formed by a MOS transistor.

The peripheral drive circuit section 1 and the pixel section 2 are both formed on a quartz substrate 11 which is an insulating substrate. A source layer 19b and a drain layer 19c, which are semiconductor layers of a source region and a drain region, each having a predetermined thickness are formed in predetermined regions on the quartz substrate 11. A channel layer 19a which is an active region is formed in the semiconductor layer between the source layer 19b and the drain layer 19c. The channel layer 19a has a laminated structure in which a p-Si film 12 which is a first crystalline silicon film and a CG silicon film 13 which is a second crystalline silicon film are sequentially formed on a quartz substrate 11, and p A natural silicon oxide film 14 having a thickness of 1 nm or less is formed between the -Si film 12 and the CG silicon film 13. Since the thickness of the native silicon oxide film 14 is 1 nm or less, the resistance value between the p-Si film 12 and the CG silicon film 13 is at a level without any problem. A source layer 19b, a drain layer 19c, and a channel layer 1 that form a MOS transistor are formed on the entire surface of the quartz substrate 11.
A first silicon oxide film 18 is formed so as to cover 9a. The gate electrode 20 is formed on the channel layer 19a via the first silicon oxide film 18, and the first silicon oxide film 18 between the gate electrode 20 and the channel layer 19a serves as a gate oxide film. To work.

On the first silicon oxide film 18 of the peripheral drive circuit portion 1, a second silicon oxide film 21 which is a layer insulation film is formed so as to cover the gate electrode 20. Contact holes are respectively formed in the first silicon oxide film 18 and the second silicon oxide film 21 on the source layer 19b and the drain layer 19c so as to expose the surfaces of the source layer 19b and the drain layer 19c, respectively. ing. Source layer 19b and drain layer 19
TiW / AlSi / T in each contact hole on c
An alloy of iW having a three-layer structure is embedded so as to come into contact with the surfaces of the source layer 19b and the drain layer 19c to form a source electrode 22 and a drain electrode 23, respectively. As a result, an N-type MOS transistor is formed.

On the other hand, the MOS transistor of the pixel section 2 is
The drain layer 19c is formed on the quartz substrate 11,
The first silicon oxide film 1 is formed on the drain layer 19c.
An auxiliary capacitance line 20a is formed via the gate electrode 8 and is covered with the second silicon oxide film 21 together with the gate electrode 20. The drain electrode 23 is formed on the second silicon oxide film 21 so as to face a part of the auxiliary capacitance line 20a. Other configurations of the MOS transistor of the pixel section 2 are similar to those of the N-type MOS transistor of the peripheral drive circuit section 1.

On the second silicon oxide film 21, an interlayer film 24 formed of a nitride film is formed so as to cover the source electrode 22 and the drain electrode 23. Pixel part 2
Film 2 on the drain electrode 23 of the MOS transistor
A pixel contact hole 28 is formed in a predetermined region of No. 4 so that the surface of the drain electrode 23 is exposed.
I is formed on the pixel contact hole 28 and the interlayer film 24.
The pixel electrode 25 made of a transparent conductive film such as a TO (Indium Tin Oxide) film is formed, and the MO of the pixel unit 2 is formed.
It is connected to the drain electrode 23 of the S transistor.
The pixel electrode 25 made of a transparent conductive film is used for the MOS of the pixel portion 2.
It is arranged so as to cover the drain electrode 23, the gate electrode 20 and the like of the transistor.

As shown in FIG. 1, in the semiconductor device of the embodiment of the present invention, since the channel layer 19a has a laminated structure of the p-Si film 12 and the CG silicon film 13, the upper C layer is formed.
The G silicon film 13 can be formed thin.

Therefore, the N-type MOS of the peripheral drive circuit unit 1 is
Transistor and MOS that is a TFT of the pixel unit 2
When the transistor is in the ON state, N of the peripheral drive circuit unit 1
Type MOS transistor and the MOS transistor which is the TFT of the pixel portion 2 has an ON current of the CG silicon film 1
3 flows only in the region near the first silicon oxide film 18 side, so that high-performance electrical characteristics such as high-speed response of signals can be obtained.

Further, the N-type MOS transistor of the peripheral drive circuit section 1 and the MOS transistor of the pixel section 2 are O.
In the FF state, the N-type MOS transistor of the peripheral drive circuit unit 1 and the MOS transistor of the pixel unit 2 are O
Most of the FF current flows through the thin CG silicon film 13. Therefore, the N-type MOS transistor of the peripheral drive circuit unit 1 and the MOS transistor of the pixel unit 2 have higher light resistance than MOS transistors such as TFTs in which only a CG silicon film is used for a normal channel layer.
Good electrical characteristics with reduced OFF current can be obtained.

FIGS. 2A to 2H are sectional views for explaining each step in the method of manufacturing the semiconductor device according to the embodiment of the present invention.

First, as shown in FIG. 2A, a plasma CVD method or LPCV method is performed on a quartz substrate 11 such as an insulating substrate on which the peripheral drive circuit section 1 and the pixel section 2 are formed.
D (LowPressure Chemical Vap
or Deposition) method, thickness 40nm
First a-Si film (amorphous Si film) is formed, and the quartz substrate 11 is further subjected to heat treatment at a temperature of 600 ° C. or higher to
The a-Si film is crystallized to form a p-Si film 12.
Then, the quartz substrate 11 on which the p-Si film 12 is formed is left in the atmosphere.

Next, as shown in FIG. 2B, p-Si
A thin native silicon oxide film 14 is formed on the surface of the film 12 by natural oxidation by leaving it in the atmosphere. After that, a thickness of 30 n is formed on the entire p-Si film 12 through the native silicon oxide film 14 by plasma CVD or the like.
m second a-Si film is formed, and the second a-S film is further formed.
1 Ni (CH ₃ COOH) ₂ (nickel acetate) on the i film
An aqueous solution of 0 ppm was spin-coated and the second a-S
Ni is added as a catalytic metal element that promotes crystallization of the i film. In this case, the Ni concentration on the surface of the second a-Si film is set to be about 2 × 10 ¹² atms / cm ² . Further, Ni, which is a catalytic metal element, is added to the second a-Si.
As a method of adding to the surface of the film, sputtering method, CVD
Any of the method, the plasma treatment method, the vapor deposition method and the like may be used.

Then, the quartz substrate 11 is placed in a nitrogen atmosphere.
Is heat-treated to crystallize the second a-Si film,
A silicon film 13 is formed. In this case, the heat treatment may be performed at a temperature of 500 ° C. to 700 ° C., for example, a temperature of 600 ° C. for 12 hours. Where p-Si
A natural silicon oxide film 14 having a thickness of 1 nm or less is formed between the film 12 and the CG silicon film 13. The natural silicon oxide film 14 is p-Si during heat treatment.
P-Si film 12 at the interface between the film 12 and the second a-Si film
To prevent epitaxial growth of the second a-Si film along the plane orientation of.

Next, as shown in FIG. 2 (c), the catalyst metal
On the CG silicon film 13 containing the element Ni, the atmospheric pressure CVD method is used.
A protective film 15 having a thickness of 200 nm is formed by
Photolithography and wet etching
Patterning is performed, and a CG film is formed on a predetermined area of the protective film 15.
An opening 16 exposing the surface of the recon film 13 is formed.
After that, the entire surface of the quartz substrate 11 is removed by an ion implantation method or the like.
The surface was implanted with phosphorus (P) ions, which are Group V elements,
Therefore, the p-Si film 12 in the opening 16 and the CG silicon film
Phosphorus (P) ions are implanted into 13 to increase the concentration of phosphorus (P).
Then, the phosphorus (P) implantation region 16a is formed. phosphorus
The dose amount of (P) is 2 × 10¹⁵atms / cm ²degree
Is. In this case, the protective film 15 does not resist the implantation of phosphorus (P).
Acts as a mask to protect the CG silicon under the protective film 15.
Phosphorus (P) is not implanted into the tungsten film 13. Also, phosphorus (P)
Is a catalyst metal element Ni in the CG silicon film 13
(P) Getter for moving (gettering) to the implantation region 16a
Acts as a tattering element.

Next, as shown in FIG. 2D, a temperature of 600 is applied to the quartz substrate 11 on which the CG silicon film 13 is grown.
The catalyst metal element Ni contained in the CG silicon film 13 is subjected to heat treatment under the heating condition of 24 ° C. for 24 hours.
The phosphorus (P) is moved (gettering) to the phosphorus (P) implantation region 16a containing a high concentration. By such a gettering process, Ni of the catalytic metal element is almost removed from the CG silicon film 13 below the protective film 15. The temperature of the heat treatment for gettering is preferably in the range of 500 ° C. to 800 ° C., and the gettering effect increases as the temperature increases.

Next, the protective film 15 on the CG silicon film 13 is entirely removed using buffered hydrofluoric acid, and phosphorus (P) is added to a high concentration by general photolithography and dry etching. Darrin (P) implantation region 16a
Then, the p-Si film 12 and the CG silicon film 13 are simultaneously patterned into a predetermined shape. After that, the p-Si film 12 and the CG silicon film 1 on the quartz substrate 11 are formed.
3 is subjected to heat treatment at a temperature of 950 ° C. in an oxygen (O ₂ ) atmosphere, and as shown in FIG. 2E, a thermal oxide film is formed so as to cover the surfaces of the p-Si film 12 and the CG silicon film 13. Form 17.

This process is called the second gettering process, and the crystal defects in the CG silicon film 13 are removed by the oxidation process for forming the thermal oxide film 17 on the surfaces of the p-Si film 12 and the CG silicon film 13. At the same time as the reducing effect, the catalytic metal element (N
It has an effect of further removing i). This second gettering process is performed with HCl, HF, HBr, Cl ₂ , F ₂ , Br.
_The gettering effect is more remarkable when the heat treatment is performed in an oxidizing atmosphere containing at least one kind of halogen element such as ₂ . In this case, the temperature range of the heat treatment is preferably 900 ° C. to 1150 ° C., and the higher the heating temperature, the catalytic metal element (Ni) in the thermal oxide film 17 is increased.
Is promoted, and the gettering effect on the catalytic metal element (Ni) is increased.

Next, the thermal oxide film 17 covering the surfaces of the p-Si film 12 and the CG silicon film 13 is removed by using buffered hydrofluoric acid, and further, on the quartz substrate 11, p.
A first silicon oxide film 18 having a thickness of about 60 nm is formed by the CVD method so as to fill the -Si film 12 and the CG silicon film 13. First silicon oxide film 18
Acts as a gate insulating film. After that, by performing a heat treatment at a temperature of 950 ° C. in an atmosphere containing oxygen atoms, a part of the CG silicon film 13 near the interface with the first silicon oxide film 18 is oxidized and the first The thickness of the silicon oxide film 18 is increased to about 80 nm. By this oxidation treatment, the crystal defects in the CG silicon film 13 are reduced, and the interface between the CG silicon film 13 and the first silicon oxide film 18 is improved. By using such a CG silicon film 13, a TFT having high reliability and high performance can be obtained.

After that, as shown in FIG. 2F, at least the p-Si film 12 and the CG silicon are formed by general photolithography in order to form the auxiliary capacitance electrode of the MOS transistor which is the TFT of the pixel portion 2. Membrane 1
The region of 3 to be the channel layer 19a is covered with a resist via the first silicon oxide film 18. afterwards,
Phosphorus (P) ions are implanted into the p-Si film 12 and the CG silicon film 13 by ion implantation from above the first silicon oxide film 18 to form a part of the drain region 19c. Has a function as an auxiliary capacitance electrode. The dose of phosphorus (P) ions is 2 ×
It is about 10 ¹⁵ atms / cm ² .

Thereafter, the resist is removed, and a p-Si film having a thickness of 50 nm is formed on the entire surface of the first silicon oxide film 18.
A WSi film having a thickness of 100 nm is sequentially formed, and the laminated p-Si film / WSi film is patterned by using general photolithography and dry etching to form an N-type MOS transistor and a pixel in the peripheral drive circuit unit 1. Part 2
The gate electrode 20 of the MOS transistor and the auxiliary capacitance wiring 20a of the MOS transistor of the pixel portion 2 are formed.

Next, using the gate electrode 20 as a mask, phosphorus (P) ions are implanted into the CG silicon film 13 and the p-Si film 12 from above the first silicon oxide film 18 by ion implantation to form the source layer. 9b and the drain layer 19c are formed. The channel layer 19a is formed below the gate electrode 20 in which phosphorus (P) ions are not implanted.
Is formed. The dose amount of phosphorus (P) ions is 2 × 10
It is about ¹⁵ atms / cm ² . Further, a second silicon oxide film 21 having a thickness of 600 nm which acts as an interlayer insulating film is formed on the first silicon oxide film 18 by the CVD method. Then, the source layer 19b and the drain layer 1
In order to electrically activate the phosphorus (P) ions implanted in 9c, the temperature is 950 ° C. and the temperature is 30 ° C. in a nitrogen (N ₂ ) atmosphere.
2H, heat treatment for 1 minute is performed, and general photolithography and dry etching are used to form the first layer on the source layer 19b and the drain layer 19c as shown in FIG.
Silicon oxide film 18 and second silicon oxide film 21 of
Then, the source contact hole 26 and the drain contact hole 27 are formed so that the surfaces of the source layer 19b and the drain layer 19c are exposed.

Next, a three-layer film of TiW / AlSi / TiW is formed on the second silicon oxide film 21, inside the source contact hole 26 and the drain contact hole 27, and general photolithography and dry etching are used. Patterning, TiW / AlSi / TiW
Source electrode 22 and drain electrode 2 composed of a three-layer film of
3 is formed. The source electrode 22 and the drain electrode 23 are connected to the source layer 19 via the source contact hole 26 and the drain contact hole 27, respectively.
b and the drain layer 19c. afterwards,
A 400 nm-thickness interlayer film 24 of a nitride film is formed on the second silicon oxide film 21, the source electrode 22, and the drain electrode 23, and the MOS transistor of the pixel portion 2 is formed by using general photolithography and dry etching. A pixel contact hole 28 is formed in the interlayer film 24 on the drain electrode 23. Further, a transparent conductive film (ITO) having a thickness of 80 nm is formed on the interlayer film 24 and in the pixel contact hole 28, and patterned by using general photolithography and dry etching.
The pixel electrode 25 made of a transparent conductive film (ITO) is formed.

As described above, in the semiconductor device manufacturing method of the present invention shown in FIGS. 2A to 2H, the CG silicon film 13 is formed.
And channel layer 1 having a two-layer structure of p-Si film 12
By forming 9a, it has high-performance electrical characteristics such as high-speed response of signals, and has improved light resistance, so that OF
The TFT in which the F current is also reduced is provided at the same time in the peripheral drive circuit unit 1 and the pixel unit 2 without adding a special process. Thereby, T using the CG silicon film 13
The FT process can be simplified.

Normally, in the liquid crystal panel for projection, the peripheral drive circuit section needs a TFT having high-performance electrical characteristics such as high-speed response of signals, and the pixel section has improved light resistance and is turned off. A TFT with reduced current is needed. Therefore, the peripheral drive circuit section and the TFT of the pixel section
However, by using the method for manufacturing a semiconductor device of the present invention, the TFTs of the peripheral drive circuit section and the pixel section can be formed in the same step. A liquid crystal panel for projection with improved durability and good image display quality can be obtained at a low price.

The present embodiment is an example of a TFT manufactured by the method for manufacturing a semiconductor device of the present invention, and the materials, film thicknesses, forming methods, etc. of parts other than those described in the present embodiment are as described above. Not as long as the.

[0063]

According to the semiconductor device of the present invention, the channel layers of a plurality of thin film transistors formed on a substrate having an insulating surface have a first crystalline silicon film and a second crystalline silicon film in this order. With such a laminated structure, the light resistance of the TFT can be improved and the OFF current can be reduced.

According to the method of manufacturing a semiconductor device of the present invention, the first amorphous silicon film formed on the substrate having an insulating surface is heat-treated to form a first crystalline silicon film, and then the first crystalline silicon film is formed. On the crystalline silicon film, and the second amorphous silicon film formed by heating the second amorphous silicon to which a catalytic metal that promotes crystal growth is added to form a second crystalline silicon film. By ion-implanting the crystalline silicon film and the second crystalline silicon film to form the drain layer, the source layer, and the channel layer, the process can be simplified.

[Brief description of drawings]

FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention.

FIG. 2A to FIG. 2H are cross-sectional views for explaining each step in the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 3 is a structural cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

1 Peripheral drive circuit 2 pixels 11 Quartz substrate 12 p-Si film 13 CG silicon film 14 Natural silicon oxide film 15 Protective film 16 openings 16a Phosphorus (P) implantation region 17 Thermal oxide film 18 First silicon oxide film 19a channel layer 19b source layer 19c drain layer 20 gate electrode 20a auxiliary capacitance wiring 21 Second silicon oxide film 22 Source electrode 23 Drain electrode 24 Interlayer film 25 pixel electrodes 26 Source contact hole 27 Drain contact hole 28 pixel contact hole 40 Peripheral drive circuit 41 pixels 51 transparent substrate 52 Source layer 53 channel layer 54 drain layer 55 First silicon oxide film 55a Second silicon oxide film 55b Interlayer film 56 gate electrode 57 auxiliary capacitance wiring 58 source electrode 59 drain electrode 60 pixel electrodes

Continued front page    F term (reference) 5F052 AA11 AA17 DA02 DB01 DB02                       DB03 DB07 EA16 FA06 FA19                       HA06 JA01                 5F110 AA06 AA16 BB02 BB04 CC02                       DD03 EE05 EE09 EE14 FF02                       FF23 FF29 GG02 GG13 GG19                       GG25 GG39 GG45 GG47 HJ01                       HJ04 HJ13 HJ23 HL06 HL12                       NN04 NN23 NN24 NN35 NN73                       PP01 PP10 PP13 PP26 PP34                       QQ11 QQ28

Claims (10)

[Claims] 1. A semiconductor device in which a plurality of thin film transistors are formed in a predetermined region on a substrate having an insulating surface, and a drain layer, a source layer, and a channel layer are provided in the thin film transistor. The semiconductor device is characterized in that the layer has a structure in which a first crystalline silicon film and a second crystalline silicon film are sequentially stacked. 2. The first crystalline silicon film is formed by performing heat treatment on the first amorphous silicon film, and the second crystalline silicon film is formed of the second amorphous silicon film. The semiconductor device according to claim 1, which is formed by performing heat treatment on the film. 3. The thickness of the second crystalline silicon film is:
The thickness is thinner than that of the first crystalline silicon film.
The semiconductor device according to. 4. The first crystalline silicon film and the second crystalline silicon film.
The semiconductor device according to claim 1, wherein an oxide film is formed between the oxide film and the crystalline silicon film. 5. The semiconductor device according to claim 4, wherein the oxide film has a thickness of 1 nm or less. 6. The method for manufacturing a semiconductor device according to claim 1, wherein a first amorphous silicon film is formed on a substrate having an insulating surface, and heat treatment is performed to form a first crystal. A crystalline silicon film, a step of forming a second amorphous silicon film on the first crystalline silicon film, and a crystal growth of the second amorphous silicon film. A step of adding a catalytic metal, a step of subjecting the amorphous silicon film to which the catalytic metal is added to a heat treatment to form a second crystalline silicon film, the first crystalline silicon film and the And a step of forming a drain layer, a source layer, and a channel layer by implanting ions into the second crystalline silicon film. 7. The catalyst metal is removed by adding a first element having an effect of selectively attracting the catalyst metal into the second crystalline silicon film, and heat-treating the catalyst. 7. The method of manufacturing a semiconductor device according to claim 6, further comprising: a step of moving the element to the region to which the first element is added, and a step of removing the region to which the first element is added. 8. The catalyst metal is Fe, Co, Ni, P
8. The method of manufacturing a semiconductor device according to claim 6, wherein the element is one or more elements selected from d, Pt, Cu, Au, In, and Sn. 9. The method of manufacturing a semiconductor device according to claim 7, wherein the first element is a group V element. 10. The method for manufacturing a semiconductor device according to claim 9, wherein the group V element is phosphorus (P).