JP2003283587A - Receiver for radio communications - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiver for radio communications in which arithmetic processing and circuit scale can be reduced. <P>SOLUTION: The receiver for the radio communications is provided with A/D converters (1-1 and 1-2) for converting an analog received signal to a digital signal, bit shift circuits (2-1 and 2-2) for reducing the number of bits of the digital signal, a superimpose signal generator 3 for generating a 1-bit superimpose signal for reducing the quantization error of the bit reduced digital signal based upon information on the reduced bits, adders (4-1 and 4-2) for adding the bit reduced digital signal and the 1-bit superimpose signal, a low-pass filter 5 for removing the 1-bit superimpose signal contained in the added digital signal, and a matched filter 6 for matching the phase of the digital signal after the 1-bit superimpose signal is removed. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wireless communication receiver used in various communication systems including a mobile communication system and a satellite communication system, and more particularly to a circuit for reducing the number of bits of a digital signal. The present invention relates to a wireless communication receiver capable of reducing a quantization error even when it is downsized and power consumption is reduced.

[0002]

2. Description of the Related Art A conventional wireless communication receiver will be described below. Receivers used in various communication systems are
With digitalization in recent years, an A / D converter for converting an analog reception signal into a digital signal is provided, and a reception function such as demodulation using digital signal processing is realized in the receiver. In digital signal processing, the resolution increases as the number of bits of the digital signal increases, but the circuit scale of the receiver increases and power consumption also increases. On the other hand, by reducing the number of bits of the digital signal, the circuit scale and power consumption can be reduced, but with the reduction of the number of bits, a quantization error occurs and the signal detection accuracy deteriorates.

As a conventional technique for reducing the quantization error when the number of bits is reduced, for example, Japanese Patent Laid-Open No. 2000-23790.
There is a "receiver" described in Japanese Patent No. Here, the superposition signal is added before the number of bits of the digital signal is reduced to reduce the quantization error when the number of bits is reduced.

FIG. 5 is a diagram showing the configuration of the quantization error reduction circuit described in the above publication. In FIG. 5, 101-1,
101-2 is an A / D converter, 102 is a superimposed signal generator, 103-1 and 103-2 are adders,
Bits 104-1 and 104-2 are bit shift circuits,
Reference numeral 05 is a low-pass filter, 106 is a matched filter, and 107 is a demodulation unit.

In the A / D converters 101-1 and 101-2, the in-phase component I and the quadrature component Q of the analog received signal are N (> 1) bit digital signals S101-1 and S10-1, respectively.
Convert to S101-2. In the superimposed signal generator 102,
L-bit (> 1) digital superimposed signals S102-1 and S102-2 having a frequency higher than the highest frequencies of the digital signals S101-1 and S101-2 are generated. At this time, the digital superimposed signals S102-1 and S1
No. 02-2 has the best quantization error suppression characteristic when it is a uniformly distributed signal with an average value of 0, but other than that, for example, a random signal may be used as long as the characteristic deterioration is allowed. However, in any case, the sum of the digital superimposition signals S102-1 and S102-2 and the digital signals S101-1 and S101-2 is always a threshold value that is deleted when the number of bits is reduced (deleted). (The maximum value that can be represented by the number of bits to be represented), and the digital superimposition signal S102-1.
The amplitude value of S102-2 needs to be adjusted so that the above condition is always satisfied.

The adders 103-1 and 103-2 add the digital signals S101-1 and S101-2 and the digital superimposed signals S102-1 and S102-2, respectively. In the bit shift circuits 104-1 and 104-2, the number of bits of the N-bit digital signals S103-1 and S103-2 output by the adders 103-1 and 103-2 is changed to N ′ bits (N ′ < The digital signal of N) is output. The low-pass filter 105 averages the digital superimposed signals from the digital signals output by the bit shift circuits 104-1 and 104-2,
1, 104-2 restores the signal before the number of bits is reduced. After that, the matched filter 106 and the demodulation unit 107 perform demodulation processing.

Bit shift circuits 104-1, 104-2
Then, when the number of bits of the digital signals S103-1 and S103-2 is reduced, a correlation occurs between the digital signal and the quantization error when the number of bits of the digital signal is reduced. Although this correlation causes deterioration of the signal detection accuracy, the digital superimposition signals S102-1 and S10 are respectively added to the digital signals S101-1 and S101-2.
By adding 2-2, the digital signal and
It is possible to cancel the correlation with the quantization error due to the reduction of the number of bits of the digital signal. However, the sum of the digital superimposition signals S102-1 and S102-2 and the digital signals S101-1 and S101-2 may fluctuate between a value larger and smaller than a threshold value deleted when the number of bits is reduced. This is a mandatory condition. If this condition is not satisfied, the digital superimposed signals S102-1 and S102-2 themselves are deleted when the number of bits is reduced, and the above correlation cannot be canceled.

As described above, in the conventional radio communication receiving apparatus, by reducing the influence of the quantization error due to the reduction of the number of bits, it is possible to suppress the deterioration of the signal detection accuracy due to the reduction of the number of bits. Further, even if the number of bits is reduced, it is possible to reduce the number of bits while maintaining the signal detection accuracy, because it has the effect of suppressing the deterioration of the signal detection accuracy. Power can be suppressed.

[0009]

However, the above
In the conventional receiver, the added value of the digital superimposition signal to be added to the digital signal before the bit number reduction and the digital signal is between a value larger and a smaller value than the threshold value deleted when the bit number is reduced. There is a problem that it is necessary to set the amplitude value of the digital superimposed signal so as to change. Further, when the number of bits to be reduced changes, it is necessary to reset the amplitude value of the digital superimposed signal in accordance with the change.

Further, the larger the number of bits of the digital superposed signal, the larger the circuit scale of the superposed signal generator and the adder for adding the digital superposed signal and the digital input signal. Further, when the reduction amount of the number of bits fluctuates, there is a problem that the circuit scale of the adder needs to be adjusted to the number of bits that the digital superimposed signal can take.

The present invention has been made in view of the above, and the calculation of the amplitude value of the digital superimposition signal and the setting work can be omitted, and the circuit for generating the digital superimposition signal and the digital superimposition signal are added. It is an object of the present invention to obtain a wireless communication receiver capable of reducing the circuit scale of an adder for doing so.

[0012]

[Means for Solving the Problems]
In order to achieve the object, in the wireless communication receiving device according to the present invention, an analog reception signal is converted into a digital signal, and the digital signal is used as a configuration for demodulating the digital signal in a predetermined procedure. A bit number reducing means for reducing the number of bits, and a superimposition signal generating means for generating a 1-bit superimposition signal for reducing the quantization error of the digital signal after the bit reduction based on the information on the reduced bits, Adding means for adding the digital signal after the bit reduction and the 1-bit superimposed signal;
Low-pass filter means for removing the 1-bit superposed signal included in the digital signal after the addition, and matched filter means for adjusting the phase of the digital signal after the removal of the 1-bit superposed signal. .

In the receiver for wireless communication according to the next invention, the number of bits of the digital signal is set as a structure for converting the analog received signal into a digital signal and demodulating the digital signal in a predetermined procedure. Bit number reducing means for reducing, superimposition signal generating means for generating a 1-bit superimposition signal for reducing the quantization error of the digital signal after the bit reduction based on the information on the reduced bits, and the bit reduction Adder means for adding the subsequent digital signal and the 1-bit superimposed signal, matched filter means for adjusting the phase of the added digital signal, and removal of the 1-bit superimposed signal included in the phase-adjusted digital signal. Low pass filter means for

In the receiver for wireless communication according to the next invention, the bit of the digital signal has a structure for converting the spread spectrum analog received signal into a digital signal and demodulating the digital signal in a predetermined procedure. A bit number reducing means for reducing the number, a superimposition signal generating means for generating a 1-bit superimposition signal for reducing a quantization error of the digital signal after the bit reduction, based on the information on the reduced bits, Adding means for adding the bit-reduced digital signal and the 1-bit superimposed signal, despreading means for despreading the added digital signal, and integration processing for the despread digital signal And an integration processing unit for performing.

In the receiver for wireless communication according to the next invention, the 1-bit superposed signal has the number of bits reduced by the number-of-bits reducing means is (N−N ′) (N is a natural number, N
′ Is a natural number that satisfies N ′ <N, and when the information value regarding the reduced bits is M (M is an integer), M / (2 ^
(N-N ')) is 1 for all other ratios, and 0 for all other ratios.
It is characterized by outputting.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a wireless communication receiving apparatus according to the present invention will be described below in detail with reference to the drawings. The present invention is not limited to this embodiment.

Embodiment 1. FIG. 1 is a diagram showing a configuration of a first embodiment of a wireless communication reception device according to the present invention. In FIG. 1, 1-1 and 1-2 are A / D converters, 2-1 and 2-2 are bit shift circuits, 3 is a superimposition signal generator, and 4-1 and 4-2. Is an adder,
Reference numeral 5 is a low-pass filter, 6 is a matched filter, and 7 is a demodulation circuit.

The in-phase component I and the quadrature component Q of the detected analog reception signal are A / D converters 1-1 and 1-, respectively.
2, and the A / D converters 1-1 and 1-2 convert the analog reception signals into N-bit digital signals S1-1 and S1-2, respectively.

In the bit shift circuits 2-1, 2-2, the number of bits N of the received digital signals S1-1, S1-2 is reduced to the number of bits N '(N'<N), and N'-bit signals are obtained. The signals S2-3 and S2-4 and the reduced (NN ′)-bit signals S2-1 and S2-2 are output. In the superposition signal generator 3, the N′-bit digital signal S2-1,
S2-2 information is received, 1-bit superimposition signal S3-1,
Outputs S3-2.

Here, the bit shift circuits 2-1 and 2-2 are provided.
-2 and the operation of the superimposed signal generator 3 will be described in detail. Here, the 1-bit superimposed signals S3-1 and S3-2 are specified. Specifically, the bit shift circuits 2-1 and 2-2
When the number of bits reduced in step S1 is set to (NN ′) and the reduced bit information value is set to M, the 1-bit superimposed signal is set to M /
1 at the rate of (2 ^ (NN)), 0 at other rates
Stipulate. This ratio matches the ratio of becoming larger than the threshold for reducing the number of bits and the ratio of becoming smaller than the threshold when the digitally superimposed signal of uniform distribution is added to the digital signal in the prior art. Therefore, in the present embodiment, if the above ratio is observed, it is possible to obtain the same effect as the conventional technique.

Specifically, the bit shift circuit 2-
In 1 and 2-2, the number of bits to be reduced is (NN ′),
When the reduced bit information value is M, signals S2-1 and S2-2 representing these pieces of information are output. Superposed signal generator 3
Then, based on the received signals S2-1 and S2-2,
The 1-bit superimposed signals S3-1 and S3-2 are converted into M / (2
^ (NN ′)) is set to 1 and other ratios are set to 0
And is generated at a higher frequency than the digital signals S1-1 and S1-2. The 1-bit superimposed signal S3-1,
The generation rule of S3-2 may be random or periodic as long as the above ratio is observed.

FIG. 2 is a diagram showing an example of the bit to be reduced and the 1-bit superimposed signal as described above. As illustrated, the signals S2-1 and S2-2 are the lower (N-
N ') bits. Then, the number of bits to be reduced (N-
When N ′) is 3 and the reduced information value is 3, the superimposed signal generator 3 outputs 1 as a 1-bit superimposed signal with a probability of 3/8 and 0 with a probability of 5/8. To do.

Although the above contents are satisfied when the operation rate of the circuit is 2 ^ (NN ') times or more of the reception signal rate, the operation rate of the circuit is 2 ^ of the reception signal rate.
When it is less than (NN ′) times, a plurality of bit information values M
Are averaged, and the superimposed signal generator 3 is operated according to the operation rate.

Next, the 1-bit superimposed signals S3-1 and S3-2 generated as described above and the N'-bit signal S2-.
In the adders 4-1, 4-2 having received S3, S2-4, the signal S2-3, the 1-bit superposed signal S3-1, the signal S
2-4 and 1-bit superimposed signal S3-2 are added respectively. The signal S4 as the addition result is input to the low-pass filter 5, and the low-pass filter 5 restores the digital signal before the number of bits is reduced by the bit shift circuits 2-1 and 2-2.

As described above, in the present embodiment, the adder 4
-1, 4-2 are the 1-bit superposed signals S3- defined above.
After adding 1, S3-2 to the digital signals S2-3, S2-4, the averaging process by the low-pass filter 5 is performed. As a result, the bit shift circuit 2-
The digital signal before the number of bits is reduced by 1 and 2 can be accurately restored. Further, since the 1-bit superimposed signal defined above is a signal based on the bit information value reduced by the bit shift circuits 2-1, 2-2, the restoration of the signal component lost due to the reduction in the number of bits can be performed more reliably. It can be carried out.

If the characteristic deterioration is tolerated, the 1-bit superimposition signal, for example, 0, 1, 0, 1, 0, .. Value or random value.

Next, the matched filter 6 that has received the restored digital signal S5 adjusts the phase of the digital signal S5, and outputs the phase-adjusted signal S6 to the demodulation circuit 7. Finally, the demodulation circuit 7 uses the output signal S6 of the matched filter 6 to perform demodulation processing. Although the low-pass filter 5 and the matched filter 6 are separately configured in FIG. 1, one circuit having the characteristics of these two circuits should be used instead of the low-pass filter 5 and the matched filter 6. May be

As described above, in the present embodiment, even if there is a signal that cannot be observed due to the reduction of the number of bits by the bit shift circuits 2-1, 2-2, the adder 4
1-bit superposed signals S3-1, S3 by -1, 4-2
-2 is added, the digital signals S1-1 and S1 are added.
The correlation between -2 and the quantization error due to the reduction in the number of bits is canceled. As a result, signal deterioration due to quantization is suppressed, so that it is possible to maintain the signal detection accuracy before the reduction in the number of bits. In addition, it is possible to reduce the circuit scale and power consumption of the entire device while preventing a decrease in signal detection accuracy due to the reduction in the number of bits.

Further, in the present embodiment, the 1-bit superimposed signal is added to the digital signal after the number of bits is reduced. In this case, the addition result when the 1-bit superposed signal is 0 is a “value smaller than the threshold value” for reducing the number of bits in the conventional technique.
And the addition result when the 1-bit superimposed signal is 1 is
This corresponds to the “value larger than the threshold value” for reducing the number of bits in the conventional technique. Then, the low pass filter averages the addition results. As a result, the same effect as that of the conventional technique can be obtained, and further, it is not necessary to set the amplitude value of the superimposed signal, and the calculation and setting process of the amplitude value can be omitted, so that the calculation process and the circuit scale can be reduced. .

Further, in the present embodiment, even if the number of bits after the bit number reduction processing is changed, it is not necessary to reset the amplitude value of the superimposed signal, so that the processing can be greatly reduced. Furthermore, since the superimposed signal is fixed at 1 bit,
The circuit scale of the superimposed signal generator and the adder can be significantly reduced compared to the conventional case.

Embodiment 2. FIG. 3 is a diagram showing the configuration of the second embodiment of the wireless communication receiving apparatus according to the present invention. The same components as those in the first embodiment described above are designated by the same reference numerals and the description thereof is omitted. Here, only operations and effects different from those of the first embodiment will be described.

The signal S4, which is the addition result of the adders 4-1 and 4-2, is input to the matched filter 6, and the matched filter 6 adjusts the phase of the input signal S4 and lowers the signal S6 after the phase adjustment. Output to the band pass filter 5. In the low pass filter 5, the bit shift circuits 2-1 and 2-2
Restores the digital signal before the number of bits is reduced by. The demodulation circuit 7 uses the output signal S5 of the low pass filter 5 to perform demodulation processing.

As described above, in this embodiment, since the low-pass filter 5 is arranged in the subsequent stage of the matched filter 6, the low-pass filter is output only when the matched filter 6 outputs the phase-adjusted signal. The filter 5 starts operating. As a result, the operation of the low-pass filter 5 is minimized and the number of operations of the low-pass filter 5 is reduced, so that the power consumption of the entire device can be suppressed as compared with the first embodiment described above.

Embodiment 3. FIG. 4 is a diagram showing the configuration of the third embodiment of the wireless communication reception device according to the present invention. In FIG. 4, reference numeral 15 is a despreading circuit, 16 is an integration processing circuit, and 17 is a demodulation circuit. In the third embodiment, particularly, the quantization error due to the reduction in the number of bits in the receiving device used in the spread spectrum communication system is effectively reduced. The same components as those in the first and second embodiments described above are designated by the same reference numerals and the description thereof will be omitted. Here, only the operation different from that of the first embodiment will be described.

The in-phase component I and the quadrature component Q of the detected spread spectrum analog reception signal are input to the A / D converters 1-1 and 1-2, respectively, and the A / D converters 1-1 and 1- are provided.
In 2, the received signal is converted into N-bit digital signals S1-1 and S1-2, respectively.

The bit shift circuits 2-1 and 2-2 receive the received digital signals S1-1 and S1-2 as described above.
The number of bits N of N to N ′ (N ′ <N)
'Bit signals S2-3 and S2-4 and reduced (N-
N ′)-bit signals S2-1 and S2-2 are output.

In the superposed signal generator 3, as shown in FIG. 2, the received N'-bit digital signal S2-
1-bit superimposed signals S3-1 and S based on S1 and S2-2
Output 3-2. In the adders 4-1, 4-2, the signal S
2-3 and 1-bit superimposed signal S3-1, signals S2-4 and 1
The bit superposition signals S3-2 are added respectively.

The despreading circuit 15 despreads the received digital signal S4 by the spreading code used on the transmitting side, and the integration processing circuit 16 performs correlation processing on the despread signal S15. I do. In this correlation processing, the digital signal before the number of bits is reduced is restored by the bit shift circuits 2-1 and 2-2. The demodulation circuit 17 performs demodulation processing based on the restored signal S16. A low pass filter may be provided immediately before the despreading circuit 15.

As described above, in the present embodiment, in particular, in the receiving device used in the spread spectrum communication system, a signal that becomes unobservable due to the reduction of the number of bits by the bit shift circuits 2-1 and 2-2 is generated. Even if they exist, the 1-bit superimposed signals S3-1 and S3-2 are added by the adders 4-1 and 4-2, so that the digital signals S1-1 and S1-2 and the number of bits are reduced. The correlation with the accompanying quantization error is canceled. As a result, signal deterioration due to quantization is suppressed, so that it is possible to maintain the signal detection accuracy before the reduction in the number of bits. In addition, it is possible to reduce the circuit scale and power consumption of the entire device while preventing a decrease in signal detection accuracy due to the reduction in the number of bits.

Further, in the present embodiment, the 1-bit superimposed signal is added to the digital signal after the number of bits is reduced. In this case, the addition result when the 1-bit superposed signal is 0 is a “value smaller than the threshold value” for reducing the number of bits in the conventional technique.
And the addition result when the 1-bit superimposed signal is 1 is
This corresponds to the “value larger than the threshold value” for reducing the number of bits in the conventional technique. Then, the low pass filter averages the addition results. As a result, the same effect as that of the conventional technique can be obtained, and further, it is not necessary to set the amplitude value of the superimposed signal, and the calculation and setting process of the amplitude value can be omitted, so that the calculation process and the circuit scale can be reduced. .

Further, in the present embodiment, even if the number of bits after the bit number reduction processing is changed, it is not necessary to reset the amplitude value of the superimposed signal, so that the processing can be greatly reduced. Furthermore, since the superimposed signal is fixed at 1 bit,
The circuit scale of the superimposed signal generator and the adder can be significantly reduced compared to the conventional case.

[0042]

As described above, according to the present invention, even if there is a signal that cannot be observed due to the reduction in the number of bits, a predetermined 1-bit superimposed signal is added, The correlation between the digital received signal and the quantization error due to the reduction in the number of bits is canceled. This allows
Since the signal deterioration due to the quantization is suppressed, it is possible to maintain the signal detection accuracy before the reduction of the number of bits. Further, there is an effect that it is possible to reduce the circuit scale and power consumption of the entire device while preventing a decrease in signal detection accuracy due to the reduction in the number of bits. Further, it is not necessary to set the amplitude value of the superimposed signal, and the calculation and setting process of the amplitude value can be omitted, so that it is possible to reduce the calculation process. Further, even if the number of bits after the bit number reduction process is changed, it is not necessary to reset the amplitude value of the superposed signal, so that the process can be significantly reduced.

According to the next invention, since the low-pass filter means is arranged after the matched filter means, the low-pass filter means is activated only when the matched filter means outputs the phase-adjusted signal. Start operation. As a result, the operation of the low-pass filter means is minimized and the number of operations of the low-pass filter means is reduced, so that the power consumption of the entire apparatus can be further suppressed.

According to the next invention, in particular, in the receiving device used in the spread spectrum communication system, even if there is a signal that cannot be observed due to the reduction of the number of bits, a predetermined 1-bit superposed signal is obtained. Is added, the correlation between the digital received signal and the quantization error due to the reduction in the number of bits is canceled. As a result, signal deterioration due to quantization is suppressed, so that it is possible to maintain the signal detection accuracy before the reduction of the number of bits. Further, there is an effect that it is possible to reduce the circuit scale and power consumption of the entire device while preventing a decrease in signal detection accuracy due to the reduction in the number of bits. Further, it is not necessary to set the amplitude value of the superimposed signal, and the calculation and setting process of the amplitude value can be omitted, so that it is possible to reduce the calculation process. Further, even if the number of bits after the bit number reduction process is changed, it is not necessary to reset the amplitude value of the superposed signal, so that the process can be significantly reduced.

According to the next invention, the averaging process is performed after adding the predetermined 1-bit superimposed signal to the digital received signal. As a result, it is possible to accurately restore the digital signal before the number of bits is reduced. Further, since the predetermined 1-bit superposed signal is a signal based on the reduced bit information value, it is possible to more reliably restore the signal component lost due to the reduction in the number of bits.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment of a wireless communication reception device according to the present invention.

FIG. 2 is a diagram showing an example of bits to be reduced and a 1-bit superimposed signal.

FIG. 3 is a diagram showing a configuration of a second embodiment of a wireless communication reception device according to the present invention.

FIG. 4 is a diagram showing a configuration of a third embodiment of a wireless communication reception device according to the present invention.

FIG. 5 is a diagram showing a configuration of a conventional quantization error reduction circuit.

[Explanation of symbols]

1-1, 1-2 A / D converter, 2-1 and 2-2 bit shift circuit, 3 superposition signal generator, 4-1 and 4-2
Adder, 5 low pass filter, 6 matched filter, 7 demodulation circuit, 15 despreading circuit, 16 integration processing circuit, 17 demodulation circuit.

Claims (4)

[Claims] 1. A wireless communication receiver for converting an analog received signal into a digital signal and demodulating the digital signal in a predetermined procedure, and a bit number reducing means for reducing the bit number of the digital signal, and the reduced number. Superimposition signal generation means for generating a 1-bit superimposition signal for reducing a quantization error of the digital signal after the bit reduction, based on information about the bits, the digital signal after the bit reduction, and the 1-bit superimposition signal Adding means for adding, a low-pass filter means for removing the 1-bit superimposed signal included in the added digital signal, and a matched filter means for adjusting the phase of the digital signal after removing the 1-bit superimposed signal. A receiver for wireless communication, comprising: 2. A wireless communication receiving apparatus for converting an analog received signal into a digital signal and demodulating the digital signal in a predetermined procedure, the bit number reducing means for reducing the number of bits of the digital signal, and the reduced number. Superimposition signal generation means for generating a 1-bit superimposition signal for reducing a quantization error of the digital signal after the bit reduction, based on information about the bits, the digital signal after the bit reduction, and the 1-bit superimposition signal And a matched filter means for adjusting the phase of the digital signal after the addition, and a low-pass filter means for removing a 1-bit superimposed signal included in the digital signal after the phase adjustment. A wireless communication receiver. 3. A wireless communication receiver for converting a spread spectrum analog received signal into a digital signal and demodulating the digital signal in a predetermined procedure, and a bit number reducing means for reducing the bit number of the digital signal, Superimposition signal generation means for generating a 1-bit superimposition signal for reducing the quantization error of the digital signal after the bit reduction, based on the information on the reduced bits, the digital signal after the bit reduction and the 1-bit superposition An addition means for adding a signal, a despreading means for despreading the digital signal after the addition, and an integration processing means for performing an integration process on the digital signal after the despreading. A wireless communication receiver. 4. The 1-bit superimposed signal has the number of bits reduced by the number-of-bits reducing means is (N−N ′) (N is a natural number, N ′ is a natural number satisfying N ′ <N), and reduced. When the information value regarding the selected bit is M (M is an integer), M /
4. Outputting 1 at a ratio of (2 ^ (N-N ')) and outputting 0 at a ratio other than that, 4.
The receiver for wireless communication according to.