JP2003283495A - Signal processor, its method and communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processor for transmitting a serial signal by encrypting it and for enabling proper synchronization of the serial signal on the transmitting/receiving side in a simple structure. <P>SOLUTION: For a base band signal S24 received by a transmitting part 25 in a receiver, a part coincident with a partial synchronization pattern constituting a part of a synchronization pattern to be used on the receiving side is detected in a base band signal S42 by a detection processing circuit 43, and a signal S43 having a part with a fixed length following the detected part in the signal S42 as a part corresponding to a signal S41 is generated. The synchronization pattern is inserted into a signal S44 by a P/S conversion circuit 45 and a synchronization processing is performed based on the synchronization pattern by an S/P conversion circuit 51 on the receiving side. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus and method capable of appropriately performing transmission / reception processing using a synchronization pattern.

[0002]

2. Description of the Related Art A transmitting side encrypts a parallel format digital signal using predetermined cryptographic key data, converts it into a serial format signal, and transmits the serial format signal.
There is a communication system in which a signal in the serial format is converted into a parallel format on the receiving side and then decoded. In such a communication system, the synchronization pattern used in the receiving process is inserted in the converting process on the transmitting side. The same code as such a synchronization pattern is prohibited from being inserted into the digital signal by the user.

[0003]

However, in the above-mentioned conventional communication system, when the existing encryption algorithm is used when the digital signal is encrypted at the transmitting side,
The above sync pattern may occur in the encrypted digital signal. In this case, the conversion process cannot be properly performed on the receiving side. Further, if an original encryption algorithm that does not generate the above synchronization pattern is developed, there is a problem that the development burden and the correction burden when the vulnerability is recognized are heavy.

The present invention has been made in view of the above-mentioned problems of the prior art, and a signal processing device which has a simple structure and can serially encrypt and transmit a serial signal, and also enables proper synchronization on the transmitting and receiving side. It is an object to provide a method and a communication system.

[0005]

In order to solve the above-mentioned problems of the prior art and to achieve the above-mentioned object, the signal processing apparatus of the first invention encrypts the first digital signal to generate the second digital signal. Of the encryption circuit for generating the digital signal of the second digital signal and a part of the synchronization pattern which is added before transmission and constitutes a part of the synchronization pattern used on the reception side, and which is detected in the second digital signal. And a signal processing circuit for generating a third digital signal in which a portion having a predetermined length following the detected portion in the second digital signal is set as a corresponding portion in the first digital signal.

The operation of the signal processor of the first invention is as follows. An encryption circuit encrypts the first digital signal to generate a second digital signal. Next, the signal processing circuit detects, in the second digital signal, a portion that coincides with the partial synchronization pattern that constitutes a portion of the synchronization pattern used on the receiving side. Next, the signal processing circuit generates a third digital signal in which a portion having a predetermined length following the detected portion in the second digital signal is a corresponding portion in the first digital signal.

In the signal processing device of the first invention, preferably, the signal processing circuit divides the second digital signal into modules having the same number of bits as the partial synchronization pattern, and the partial synchronization is sequentially performed for each module. The pattern is compared, and as a result of the comparison, when the partial synchronization pattern and the module match, the third part using the corresponding part in the first digital signal as a module next to the matched module. To generate a digital signal of. Further, the signal processing device of the first invention is preferably
The signal processing circuit uses the flag data as a first value as an initial value.
When the flag data indicates the second logic value, the corresponding portion in the first digital signal is output as the third digital signal, and the first portion is added to the flag data. Set a logical value, and the flag data is first
The corresponding portion of the second digital signal is output as the third digital signal, and the module of the corresponding portion of the second digital signal matches the partial synchronization pattern. If it is determined that they match, a second logical value is set in the flag data.

Further, in the signal processing apparatus of the first invention, preferably, the encryption circuit is a block cipher circuit for generating new key series data by using fed back key series data, and the block cipher circuit. And an arithmetic circuit that performs an arithmetic operation using the key sequence data generated in step 1 and the first digital signal to generate the second digital signal. In the signal processing device of the first invention, preferably, the arithmetic circuit adds the key sequence data and the first digital signal to generate the second digital signal. Further, in the signal processing device of the first invention, preferably, the encryption circuit performs a calculation by using a random number generation circuit that generates a random number, and the second random number and the first digital signal. And an arithmetic circuit that generates a digital signal of. Further, in the signal processing device of the first invention, preferably, the digital signal is a baseband signal, and the signal generation circuit generates the third digital signal in a parallel format in units of a plurality of bits, The signal processing device outputs the third digital signal in the parallel format,
It further has a conversion circuit for converting into a serial format including the synchronization pattern. Further, in the signal processing device of the first invention, preferably, the synchronization pattern is a pattern including a plurality of the partial synchronization patterns.

The signal processing apparatus of the second invention is obtained by encrypting the first digital signal and the first digital signal so that the synchronization pattern used for the synchronization processing at the receiving side does not occur. A signal processing device that decodes a received third digital signal generated by mixing two digital signals based on a predetermined rule, and decodes the third digital signal to obtain a fourth digital signal. A decoding circuit for generating a digital signal and a part of the sync pattern that matches the partial sync pattern are detected in the third digital signal and correspond to the detected part in the fourth digital signal. And a signal processing circuit for generating a fifth digital signal, which has a portion of a predetermined length following the portion to be the corresponding portion in the third digital signal.

The operation of the signal processor of the second invention is as follows. A decoding circuit decodes the third digital signal to generate a fourth digital signal. Next, the signal processing circuit detects, in the third digital signal, a portion that matches the partial synchronization pattern that forms a portion of the synchronization pattern. Next, the signal processing circuit sets a portion having a predetermined length following the portion corresponding to the detected portion in the fourth digital signal as a corresponding portion in the third digital signal, and a fifth digital signal. To generate.

Further, in the signal processing apparatus of the second invention, preferably, the signal processing circuit divides the third digital signal into modules having the same number of bits as the partial synchronization pattern, and the modules are sequentially processed for each module. The partial synchronization pattern is compared, and as a result of the comparison, if the partial synchronization pattern and the module match, the third module is set as the section corresponding to the module next to the matched module in the fourth digital signal. To generate the fifth digital signal using a corresponding portion of the digital signal of. Further, in the signal processing device of the second invention, preferably, the signal processing circuit sets a first logical value as an initial value in the flag data, and when the flag data indicates a second logical value, Outputting a corresponding portion of the third digital signal as the fifth digital signal, setting a first logical value in the flag data, and the flag data indicating a first logical value, Outputting a corresponding portion of the fourth digital signal as the fifth digital signal;
It is determined whether or not the module of the corresponding portion of the digital signal of (1) matches the partial synchronization pattern, and if it is determined that the module matches, the second logical value is set to the flag data.

A signal processing device according to a third aspect of the present invention is an encryption circuit for encrypting a first digital signal to generate a second digital signal, and the same logical value used on the receiving side for the first number of bits. A sync pattern including a continuous partial sync pattern is defined, and when the partial sync pattern is detected in the second digital signal, the detected partial sync pattern in the second digital signal. And a signal processing circuit for generating a third digital signal for transmission using a corresponding portion of the first digital signal as a portion from the next bit to the bit corresponding to the second bit number.

The operation of the signal processor of the third invention is as follows. An encryption circuit encrypts the first digital signal to generate a second digital signal. Next, a signal processing circuit detects the partial synchronization pattern in the second digital signal. Then, a signal processing circuit corresponds to the first digital signal as a part from the next bit following the detected partial synchronization pattern in the second digital signal to a bit for a second bit number. Generate a third digital signal for transmission using the portion.

The signal processing apparatus according to the fourth aspect of the present invention prevents the occurrence of a sync pattern including a partial sync pattern which is used on the receiving side and continuously shows the same logical value for the first bit number. And a second digital signal obtained by encrypting the first digital signal in a mixed manner based on a predetermined rule, and is a signal processing device for decoding a received third digital signal. And a decoding circuit that decodes the third digital signal to generate a fourth digital signal, and detects a portion in the third digital signal where the logical value continuously appears for the first number of bits. , Using the corresponding portion of the third digital signal as the portion from the next bit following the portion corresponding to the detected portion in the fourth digital signal to the second number of bits 5 digital signal Generating a and a signal processing circuit.

The operation of the signal processor of the fourth invention is as follows. A decoding circuit decodes the third digital signal to generate a fourth digital signal. Next, the signal processing circuit determines that the logical value is the first in the third digital signal.
The part that appears continuously for the number of bits of is detected. Next, a signal processing circuit outputs a portion of the third digital signal as a portion from the next bit following the portion corresponding to the detected portion in the fourth digital signal to the second bit number of bits. Generate a fifth digital signal using the corresponding portion.

According to a fifth aspect of the present invention, there is provided a signal processing device comprising a first digital signal and a second digital signal obtained by encrypting the first digital signal.
And a block cipher circuit that generates key sequence data by using the third digital signal.
An operation circuit that performs an operation using the key sequence data and the first digital signal to generate the second digital signal, wherein the signal processing circuit is one of the synchronization patterns used on the receiving side. A portion of the second digital signal that matches the partial synchronization pattern forming the portion is detected, and a portion of the second digital signal having a predetermined length following the detected portion is detected in the first digital signal. To generate the third digital signal corresponding to

The operation of the signal processor of the fifth invention is as follows. The signal processing circuit includes a first digital signal,
A second digital signal obtained by encrypting the first digital signal is input, and a portion that matches a partial synchronization pattern that constitutes a part of a synchronization pattern used on the receiving side is the second portion.
Detect in the digital signal of. Next, the signal processing circuit
The third digital signal is generated by setting a portion having a predetermined length following the detected portion in the second digital signal as a corresponding portion in the first digital signal. Next, the block cipher circuit generates key sequence data using the third digital signal. Next, the arithmetic circuit performs an arithmetic operation using the key series data and the first digital signal to generate the second digital signal, and outputs the second digital signal to the signal processing circuit.

In the signal processing device of the sixth invention, the first digital signal and the second digital signal obtained by encrypting the first digital signal are obtained so that the synchronization pattern used for the synchronization processing on the receiving side does not occur. A signal processing device that decodes a received third digital signal generated by mixing patterns included in the digital signal and the digital signal according to a predetermined rule, and uses the third digital signal as a key. A block decryption circuit for generating sequence data, an operation circuit for performing an operation using the key sequence data and the third digital signal to generate the fourth digital signal, the third digital signal and the third digital signal A fourth digital signal and a signal processing circuit for generating a fifth digital signal for transmission, and the signal processing circuit includes a partial synchronization pattern forming a part of the synchronization pattern; A matching portion is detected in the third digital signal, and a portion of a predetermined length following the portion corresponding to the detected portion in the fourth digital signal is added to the corresponding portion in the third digital signal. And a fifth digital signal is generated.

The operation of the signal processor of the sixth invention is as follows. The block decryption circuit generates key sequence data using the third digital signal. Next, an arithmetic circuit performs an arithmetic operation using the key series data and the third digital signal to generate the fourth digital signal. next,
A signal processing circuit detects, in the third digital signal, a portion that matches a partial synchronization pattern that forms a portion of the synchronization pattern. Then, the signal processing circuit sets a fifth digital signal in which a portion of a predetermined length following the portion corresponding to the detected portion in the fourth digital signal is set as a corresponding portion in the third digital signal. To generate.

According to a seventh aspect of the present invention, there is provided a signal processing device comprising: a first digital signal; and a second digital signal obtained by encrypting the first digital signal.
And a block cipher circuit that generates key sequence data by using the third digital signal.
An arithmetic circuit that performs an operation using the key sequence data and the first digital signal to generate the second digital signal, wherein the signal processing circuit uses the same logical value on the receiving side. A synchronization pattern including a partial synchronization pattern continuously shown for the first number of bits is defined, and when the partial synchronization pattern is detected in the second digital signal, the synchronization signal in the second digital signal is detected. The third digital signal is generated using the corresponding portion of the first digital signal as the portion from the next bit following the detected partial synchronization pattern to the bit for the second bit number.

The operation of the signal processor of the seventh invention is as follows. When the signal processing circuit defines a synchronization pattern including a partial synchronization pattern which is used on the receiving side and continuously shows the same logical value for the first bit number, the second
The partial synchronization pattern is detected in the digital signal.
Next, a signal processing circuit associates the first digital signal as a portion from the next bit following the detected partial synchronization pattern in the second digital signal to a bit of a second bit number. The third digital signal using the portion to be generated is generated. Next, the block cipher circuit generates key sequence data using the third digital signal. Next, an arithmetic circuit performs an arithmetic operation using the key series data and the first digital signal to generate the second digital signal.

In the signal processing device of the eighth invention, the first digital signal and the second digital signal obtained by encrypting the first digital signal are obtained so that the synchronization pattern used for the synchronization processing on the receiving side does not occur. A signal processing device that decodes a received third digital signal generated by mixing patterns included in the digital signal and the digital signal according to a predetermined rule, and uses the third digital signal as a key. A block decryption circuit for generating sequence data, an operation circuit for performing an operation using the key sequence data and the third digital signal to generate the fourth digital signal, the third digital signal and the third digital signal And a signal processing circuit that inputs a fourth digital signal and generates a fifth digital signal for transmission, wherein the signal processing circuit has the first logical value within the third digital signal. bit Detects a part that appears to minute continuous,
The third portion of the third digital signal is used as the portion from the next bit following the portion corresponding to the detected portion in the fourth digital signal to the second number of bits. 5 digital signals are generated.

The operation of the signal processor of the eighth invention is as follows. The block decryption circuit generates key sequence data using the third digital signal. Next, the arithmetic circuit
An operation is performed using the key sequence data and the third digital signal to generate the fourth digital signal. Next, the signal processing circuit detects a portion in the third digital signal where the logical value continuously appears for the first bit number. Then, the signal processing circuit corresponds to the third digital signal as a part from the next bit following the part corresponding to the detected part in the fourth digital signal to the second number of bits. The fifth digital signal using the portion to be generated is generated.

A signal processing method according to a ninth aspect of the present invention is a signal processing method performed by a signal processing device, wherein a first digital signal is encrypted to generate a second digital signal, and a synchronization pattern used on the receiving side. A part of the second digital signal that matches the partial synchronization pattern forming a part of
A third digital signal is generated in which a portion having a predetermined length following the detected portion in the second digital signal is set as a corresponding portion in the first digital signal.

In the signal processing method of the tenth invention, the receiving side does not generate a synchronization pattern used for the synchronization processing,
The first digital signal and the second digital signal obtained by encrypting the first digital signal are mixed and generated based on a predetermined rule, and the received third digital signal is decoded. A signal processing method performed by a processing device,
The third digital signal is decoded to generate a fourth digital signal, and a portion that matches a partial sync pattern forming a part of the sync pattern is detected in the third digital signal, and the fourth digital signal is detected. A fifth digital signal is generated in which a portion of a predetermined length following the portion corresponding to the detected portion in the digital signal is set as the corresponding portion in the third digital signal.

The signal processing method of the eleventh invention is a signal processing method performed by a signal processing device, wherein the first digital signal is encrypted to generate a second digital signal, and the same logic used on the receiving side is used. When a synchronization pattern including a partial synchronization pattern that continuously indicates a value for the first number of bits is defined, the partial synchronization pattern is detected in the second digital signal, and the partial synchronization pattern is detected in the second digital signal. Generating a third digital signal for transmission using the corresponding portion of the first digital signal as the portion from the next bit following the detected partial synchronization pattern to the second number of bits. To do.

In the signal processing method of the twelfth invention, the first digital signal is generated so that a sync pattern including a partial sync pattern continuously showing the same logical value used on the receiving side for the first bit number is not generated. And a second digital signal obtained by encrypting the first digital signal in a mixed manner based on a predetermined rule, and generated by a signal processing device for decoding a received third digital signal. A signal processing method, wherein the third digital signal is decoded to generate a fourth digital signal, and a portion in which the logical value continuously appears for the first number of bits in the third digital signal. Detect and
A fifth part using the corresponding part of the third digital signal as the part from the next bit following the part corresponding to the detected part in the fourth digital signal to the second number of bits. To generate a digital signal of.

In the signal processing method of the thirteenth invention, a first digital signal and a second digital signal obtained by encrypting the first digital signal are input, and a third digital signal for transmission is output. And a second step of generating key sequence data using the third digital signal, and an operation using the key sequence data and the first digital signal to perform the second process. And a third step of generating a digital signal of the second digital signal, wherein in the first step, a portion that coincides with a partial synchronization pattern forming a part of the synchronization pattern used on the receiving side is included in the second digital signal. Then, the third digital signal is generated by setting the portion having a predetermined length following the detected portion in the second digital signal as the corresponding portion in the first digital signal.

In the signal processing method of the fourteenth invention, the receiving side does not generate a synchronization pattern used for synchronization processing,
A third digital signal generated and received by mixing patterns included in the first digital signal and the second digital signal obtained by encrypting the first digital signal based on a predetermined rule. Is a signal processing method performed by a signal processing device for decoding the key sequence data, the first step of generating key sequence data using the third digital signal, and the key sequence data and the third digital signal. A second step of performing an operation to generate the fourth digital signal, and inputting the third digital signal and the fourth digital signal to generate a fifth digital signal for transmission A third step, in the third step, detecting a portion in the third digital signal, which coincides with a partial synchronization pattern forming a part of the synchronization pattern, and outputs the fourth digital signal. Within the detection And the predetermined length portion of the following portion corresponding to the portion to produce a fifth digital signal corresponding to those in the third digital signal.

In the signal processing method of the fifteenth invention, a first digital signal and a second digital signal obtained by encrypting the first digital signal are input, and a third digital signal for transmission is output. And a second step of performing block encryption using the third digital signal to generate key sequence data, and an operation using the key sequence data and the first digital signal. And a third step of generating the second digital signal, and in the first step, the partial synchronization pattern continuously showing the same logical value used by the receiving side for the first bit number. Is defined in the second digital signal, and when the partial synchronization pattern is detected in the second digital signal, from the next bit following the detected partial synchronization pattern in the second digital signal, 2 bits As part of the previous bits, generating the third digital signal using a corresponding portion of the first digital signal.

In the signal processing method according to the 16th aspect of the invention, the receiving side does not generate a synchronization pattern used for the synchronization processing,
A third digital signal generated and received by mixing patterns included in the first digital signal and the second digital signal obtained by encrypting the first digital signal based on a predetermined rule. A signal processing method performed by a signal processing device that performs the decryption of the first key, wherein the key sequence data is generated by performing the flock encryption using the third digital signal.
And a second step of performing an operation using the key sequence data and the third digital signal to generate the fourth digital signal, the third digital signal and the fourth digital signal.
And a third step of generating a fifth digital signal for transmission, wherein the logical value is the first in the third digital signal. A portion that continuously appears for the number of bits is detected, and the third bit is the portion from the next bit following the portion corresponding to the detected portion in the fourth digital signal to the second bit number of bits. To generate the fifth digital signal using a corresponding portion of the digital signal.

A communication system according to a seventeenth aspect of the invention is a communication system having a receiving device for encrypting and transmitting a received baseband signal, and an output device for decoding and outputting the baseband signal transmitted by the receiving device. And the receiving device includes receiving means for receiving the first digital signal,
The received first digital signal is encrypted to generate a second
An encryption circuit for generating a digital signal of, and a portion of the synchronization pattern used on the receiving side that matches a partial synchronization pattern, and a portion in the second digital signal is detected,
A signal processing circuit for generating a third digital signal in which a portion of a predetermined length following the detected portion in the second digital signal is a corresponding portion in the first digital signal, The output device detects, in the third digital signal, a decoding circuit that decodes the received third digital signal to generate a fourth digital signal, and a part that matches the partial synchronization pattern in the third digital signal. A signal processing circuit for generating a fifth digital signal having a portion of a predetermined length following a portion corresponding to the detected portion in the fourth digital signal as a corresponding portion in the third digital signal; 5
And an output means for outputting according to the digital signal. Here, the receiving device has the same operation as the signal processing device of the first invention, and the output device has the same operation as the signal processing device of the second invention.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Background Art of the Invention] FIG.
It is the whole communication system 401 lineblock diagram concerning the background art of the present invention. As shown in FIG. 25, the communication system 401
Has a transmitting device 2, a receiving device 403, and a projector device 404, for example. In the communication system 401,
For example, the transmitter 2 is arranged in a service center that distributes baseband signals such as movies to a plurality of movie theaters, the receiver 403 is arranged in a management room in the movie theater, and the projector 404 is, for example, behind a screen. Etc.

In the communication system 401, a baseband signal S5 such as a content signal such as an image (video) or audio (voice) or an auxiliary signal is input to the transmitter 2 from an external device such as a video generation device. And
In the transmitter 2, the baseband signal S5 is encoded by the encoder 11 and then encrypted by the encryption unit 12, and the baseband signal S2 obtained thereby is wirelessly or wired transmitted to the receiver 403. Then, in the receiving apparatus 403, the baseband signal S2 received by the receiving unit 21 is stored in the storage unit 22, then read from the storage unit 22 and decoded by the decoding unit 23. Baseband signal S23 obtained by the decoding
However, after being decoded by the decoder 24, a serial format HD-SDI (Higt Definition bit Seir
al Digital Interface) signal S403, which is transmitted to the projector device 404 via the serial transmission line. Then, in the projector device 404, the HD-SDI signal S403 received by the receiving unit 31.
Is converted into a video signal S31, and the projector processing unit 32
The output unit 33 outputs an image corresponding to the image signal S31.

However, in the above-described conventional communication system 401, the baseband signal S2 transmitted from the transmitting device 2 to the receiving device 403 is encrypted, but H transmitted from the receiving device 403 to the projector device 404.
The D-SDI signal S403 is not encrypted. Therefore, the HD-SDI signal S403 may be illegally acquired by a third party.

In order to solve the above-mentioned problem, in the transmitting unit 425 of the receiving apparatus 403, the encrypted HD-SD is used.
It is also conceivable that the I signal S403 is transmitted to the projector apparatus 404 and the receiving unit 431 of the projector apparatus 404 decrypts the encrypted HD-SDI signal S403. Here, the HD-SDI signal is SMPTE.
(Society of Motion Picture and Television Engineer
s) Since it is a signal defined by 292M and is a baseband serial signal, parallel / serial conversion is performed on the transmitting side and serial / parallel conversion is performed on the receiving side.

In this case, the EAV (End) is added to the data used as the synchronization signal for serial / parallel conversion on the receiving side.
of Active Video), SAV (Start of Active Video)
). As shown in FIG. 26, each of EAV and SAV includes a 10-bit C (Cb, Cr) signal and a 1-bit signal.
It is composed of a 0-bit Y signal and is defined by four 20-bit signals 1, 2, 3, and 4. And
“3FF 3FF 000 000 00” in the signal
60 bits of "0000" are used as a synchronization pattern for detecting synchronization of serial / parallel conversion on the receiving side. However, when the HD-SDI signal S403 is encrypted using the existing algorithm, the synchronization pattern is generated in the encrypted HD-SDI signal S403, and the synchronization process cannot be properly performed on the receiving side. There is a problem that sometimes.

In order to solve the above-mentioned problem, it may be considered to develop a new encryption algorithm other than the existing encryption algorithm that does not generate a synchronization pattern and encrypt the HD-SDI signal S403 using the encryption algorithm. However, in this case, it is very difficult to guarantee the encryption strength, and it is not easy to change to another algorithm when a vulnerability is found.

[Embodiment of the Invention] A communication system according to an embodiment of the present invention will be described below. First Embodiment The present embodiment is the first, second, ninth, tenth, and first.
It is an embodiment corresponding to the seventh invention. FIG. 1 is an overall configuration diagram of a communication system 1 of this embodiment. As shown in FIG. 1, the communication system 1 includes, for example, a transmission device 2, a reception device 3, and a projector device 4. In the communication system 1, for example, the transmitting device 2 is arranged in a service center that distributes baseband signals such as movies to a plurality of movie theaters, the receiving device 3 is arranged in a management room in the movie theater, and the projector device 4 is used. Is disposed, for example, on the back of the screen. The transmission device 2 includes, for example, an encoder 11, an encryption unit 12, and a transmission unit 13. The reception device 3 includes, for example, a reception unit 21, a storage unit 22, a decoding unit 23, a decoder 24, and a transmission unit 25. Projector device 4
Has a receiving unit 31, a projector processing unit 32, and an output unit 33, for example. A wired or wireless digital baseband signal is transmitted from the transmitter 2 to the receiver 3, and a digital baseband signal (digital signal of the present invention) is transmitted from the receiver 3 to the projector 4 via a serial communication line. It is transmitted in serial format. The present embodiment is characterized by the encryption process and the decryption process of the HD-SDI signal S3 transmitted from the receiving device 3 to the projector device 4.

In the communication system 1, for example, a baseband signal S5 such as a content signal such as an image (video) or audio (voice) or an auxiliary signal is input to the transmitting device 2 from an external device such as a video generating device. Then, in the transmitter 2, the baseband signal S5 is encoded by the encoder 11 and then encrypted by the encryption unit 12, and the baseband signal S2 obtained thereby is transmitted to the receiver 3. Then, in the receiving device 3, the baseband signal S2 received by the receiving unit 21 is stored in the storage unit 22, then read from the storage unit 22 and decoded by the decoding unit 23. The baseband signal S23 obtained by the decoding is decoded by the decoder 24, and then transmitted by the transmitter 25 in HD-SDI (Higt Definition b).
It Seiral Digital Interface) signal S3 is converted and transmitted to the projector device 4 in a serial format. Then, in the projector device 4, the HD-SDI signal S3 received by the receiving unit 31 is converted into the video signal S31, and the projector processing unit 32 outputs the video corresponding to the video signal S31 from the output unit 33. Where HD
-The SDI signal S3 is a serial signal in which various signals are mixed and transmitted by replacing all image signals, audio signals and auxiliary signals with bit signals and attaching appropriate marks, and which can be combined on the receiving side. Is.

Hereinafter, the configuration and operation of the communication system 1 will be described in detail, centering on the configurations of the transmitting unit 25 and the receiving unit 31 shown in FIG. FIG. 2 is a configuration diagram of the transmitter 25 and the receiver 31 shown in FIG. [Transmission Unit 25] As shown in FIG. 2, the transmission unit 25 includes, for example, a bit conversion circuit 41, an encryption circuit 42, a detection processing circuit 43, a bit conversion circuit 44, and a P / S conversion circuit 45.
And sends an HD-SDI signal. Here, the transmission unit 25 corresponds to the signal processing device of the first invention, the encryption circuit 42 corresponds to the encryption circuit of the present invention, and the detection processing circuit 43.
Corresponds to the signal processing circuit of the present invention. The bit conversion circuit 41 inputs the 20-bit baseband signal S24 from the decoder 24, converts it into a 120-bit baseband signal S41, and outputs the baseband signal S41 to the encryption circuit 42 and the detection processing circuit 43. ..

The encryption circuit 42 uses, for example, a common key block cipher AES (Advanced Encryption Standard),
OFB (Out Feed Back) specified by ISO08372
In the mode, the baseband signal S41 is encrypted to generate the baseband signal S42, and the baseband signal S42 is output to the detection processing circuit 43.

FIG. 3 is a block diagram of the encryption circuit 42 shown in FIG. As shown in FIG. 3, the encryption circuit 42 includes, for example, an M sequence generation circuit 61, an addition circuit 62, a memory 63,
It has a random number generation circuit 64 and an addition circuit 66. The M-sequence generation circuit 61 generates the M-sequence signal S61 and outputs it to the addition circuit 62. The adder circuit 62 performs an exclusive OR (EXOR) of the baseband signal S41 input from the bit conversion circuit 41 shown in FIG. 2 and the M sequence signal S61 for stirring.
The baseband signal S62 is calculated and output to the adder circuit 66.

The memory 63 stores initial value data S63a and key data S63b used in the random number generation circuit 64. The random number generation circuit 64 has a register 67 and a block cipher circuit 68, as shown in FIG. In the random number generation circuit 64, the data S6 stored in the register 67
7 and the key data S63b read from the memory 63, the block cipher circuit 68 performs the block cipher processing, and the upper predetermined bits of the resulting data S68 are extracted and output to the addition circuit 66. The register 67 stores the initial value data S63a read from the memory 63.
Is stored as an initial value, and then the data S68 is sequentially stored.

The adder circuit 66 performs an exclusive OR operation of the upper predetermined bits of the data S68 and the baseband signal S62 to generate the baseband signal S42 and outputs it to the detection processing circuit 43 shown in FIG.

The detection processing circuit 43 uses the baseband signal S
In 42, a portion that coincides with a synchronization pattern added by a P / S conversion circuit 45 described later is set in a predetermined detection unit, for example, 1
Detection is performed with 0 bit as a unit. Then, the detection processing circuit 43 generates a baseband signal S43 in which a portion of the baseband signal S42, which has a predetermined length following the detected portion, corresponds to the baseband signal S41. In the present embodiment, in the detection processing circuit 43, the receiving unit 31
As a synchronization pattern used for synchronization detection in
"3FF 3FF 000000 000000" is illustrated.

FIG. 4 is a diagram for explaining an example of processing in the detection processing circuit 43, and FIG. 5 is a flowchart for explaining the processing. As shown in FIG. 4, the detection processing circuit 43 uses the 120-bit baseband signal S4.
1 and S42 are processed in units of 10-bit modules to generate a 120-bit baseband signal S43. In FIG. 4, when n is an integer that satisfies 0 ≦ n ≦ 11, X [n], E [n], and Y [n] are 10-bit signals that form the baseband signals S41, S42, and S43, respectively. It is a module. The detection processing circuit 43 holds the flag data flag and sets the logical value “0” as its initial value. Detection processing circuit 43
Increments the integer n satisfying 0 ≦ n ≦ 11 from the initial value “0” to “11” in order, and sequentially performs the process illustrated in FIG. 5 for each module.

Step ST1: The detection processing circuit 43 determines whether or not the flag data flag indicates the logical value "1". If the flag data flag indicates the logical value "1", the process proceeds to step ST2, and the logical value "0". , The process proceeds to step ST4.

Step ST2: The detection processing circuit 43 selects and outputs the module X [n] of the input baseband signal S41 as the module Y [n] of the baseband signal S43. Step ST3: The detection processing circuit 43 causes the flag data f
The logical value “0” is set in lag.

Step ST4: The detection processing circuit 43 selects and outputs the encrypted module E [n] of the input baseband signal S42 as the module Y [n] of the baseband signal S43. Step ST5: The detection processing circuit 43 uses the module E
It is determined whether or not [n] is "0", and if it is "0", the process proceeds to step ST6, and if it is not "0", the process ends. That is, the detection processing circuit 43 determines whether or not the module E [n] matches the 10-bit logical value “0” that is a part of the synchronization pattern. The detection processing circuit 43 causes the flag data fl
The logical value "1" is set in ag.

As described above, the detection processing circuit 43 includes the 10-bit logical value "0" which is a part of the synchronization pattern (partial synchronization pattern of the present invention) in units of 10 bits for the baseband signal S42. If it is included, the flag data flag is set to the logical value "1". When the flag data flag indicates the logical value "1", the detection processing circuit 43 determines that the module Y [n] of the baseband signal S43 is not the module E [n] of the encrypted baseband signal S42. , Module X [n] of the unencrypted baseband signal S41 is output. As a result, the synchronization pattern "3FF 3FF 000" is added to the baseband signal S42.
Even if "000,000,000" occurs, the synchronization pattern is not included in the baseband signal S43.

The bit conversion circuit 44 is a detection processing circuit 43.
The 120-bit baseband signal S43 input from is converted into a 20-bit baseband signal S44, and the baseband signal S44 is output to the P / S conversion circuit 45. P
The / S conversion circuit 45 converts the parallel format baseband signal S44 into a serial format HD-SDI signal S3, and transmits this to the projector device 4. The P / S conversion circuit 45 inserts the above synchronization pattern used in the synchronization processing of the S / P conversion circuit 51 into the HD-SDI signal S3.

[Reception Unit 31] As shown in FIG. 2, the reception unit 31 has, for example, an S / P conversion circuit 51, a bit conversion circuit 52, a decoding circuit 53, a detection processing circuit 54, and a bit conversion circuit 55. , HD-SDI signal S3 is received.
Here, the receiving unit 31 corresponds to the signal processing device of the second invention, the decoding circuit 53 corresponds to the decoding circuit of the present invention, and the detection processing circuit 54 corresponds to the signal processing circuit of the present invention. S
The / P conversion circuit 51 converts the HD-SDI signal S3 in serial format received from the receiving device 3 into the HD-SD signal S.
Synchronization processing is performed based on the synchronization pattern of No. 3 to convert the baseband signal S51 into a parallel format, and the baseband signal S51 is output to the bit conversion circuit 52. The bit conversion circuit 52 converts the 20-bit baseband signal S51 into 1
It is converted into a 20-bit baseband signal S52, and the baseband signal S52 is decoded by the decoding circuit 53 and the detection processing circuit 5.
Output to 4.

The decryption circuit 53 uses, for example, the common key block cipher AES, and the OF specified by ISO08372.
In the B mode, the baseband signal S52 is decoded to generate the baseband signal S53, and the baseband signal S53 is output to the detection processing circuit 54. The decryption circuit 53 has the same configuration as the encryption circuit 42 described above.

FIG. 6 is a block diagram of the decoding circuit 53 shown in FIG. As shown in FIG. 6, the decoding circuit 53, for example,
It has an M-sequence generation circuit 71, an addition circuit 72, a memory 73, a random number generation circuit 74, and an addition circuit 76. The M-sequence generation circuit 71 generates the M-sequence signal S71 and adds it to the addition circuit 72.
Output to. The adder circuit 72 performs an exclusive OR (EXOR) operation of the baseband signal S52 input from the bit conversion circuit 52 shown in FIG. 2 and the M sequence signal S71 for stirring to generate the baseband signal S72. Adder circuit 7
Output to 6.

The memory 73 stores initial value data S73a and key data S73b used in the random number generation circuit 74. As shown in FIG. 6, the random number generation circuit 74 has a register 77 and a block decoding circuit 78. In the random number generation circuit 74, the data S7 stored in the register 77 is stored.
7 and the key data S73b read from the memory 73, the block decryption circuit 78 performs the block encryption process, and the upper predetermined bits of the resulting data S78 are extracted and output to the addition circuit 76. The register 77 stores the initial value data S73a read from the memory 73.
Is stored as an initial value, and then the data S78 is sequentially stored.

The adder circuit 76 performs an exclusive OR operation of the upper predetermined bits of the data S78 and the baseband signal S72 to generate the baseband signal S72 and outputs it to the detection processing circuit 54 shown in FIG.

The detection processing circuit 54 uses the baseband signal S
In the 52, the synchronization pattern "3FF3FF 000 00
Whether or not the partial synchronization pattern (10-bit logical value “0”) that is part of “0000000” is included is detected in the above-described detection unit, for example, 10 bits. Then, the detection processing circuit 54 causes the baseband signal S
A baseband signal S54 is generated by setting a portion of a predetermined length following the portion corresponding to the detected portion in 53 as a corresponding portion in the baseband signal S52.

FIG. 7 is a diagram for explaining an example of the processing in the detection processing circuit 54, and FIG. 8 is a flowchart for explaining the processing. As shown in FIG. 7, the detection processing circuit 54 uses the 120-bit baseband signal S5.
2, S53 are processed in units of 10-bit modules to generate a 120-bit baseband signal S54. In FIG. 7, when n is an integer that satisfies 0 ≦ n ≦ 11, Y [n], D [n], and X [n] are 10-bit signals that form the baseband signals S52, S53, and S54, respectively. It is a module. The detection processing circuit 54 holds the flag data flag and sets a logical value “0” as an initial value thereof. Detection processing circuit 54
Increments the integer n satisfying 0 ≦ n ≦ 11 from the initial value “0” to “11” in order, and sequentially performs the process illustrated in FIG. 8 for each module.

Step ST11: The detection processing circuit 54
It is determined whether or not the flag data flag indicates a logical value "1". When the flag data flag indicates a logical value "1", the process proceeds to step ST12, and when it indicates a logical value "0", step ST14.
Go to processing.

Step ST12: The detection processing circuit 54
As the module X [n] of the baseband signal S54,
Module Y [n] of the input baseband signal S52
To output. Step ST13: The detection processing circuit 54 sets the logical value “0” to the flag data flag.

Step ST14: The detection processing circuit 54
As the module X [n] of the baseband signal S54,
The encrypted module D [n] of the input baseband signal S53 is selected and output. Step ST15: The detection processing circuit 54 is the module Y
It is determined whether or not [n] is “0”, and if it is determined to be “0”, the process proceeds to step ST16, and “0” is determined.
If it is determined that it is not, the process ends. That is, the detection processing circuit 43 determines whether or not the module Y [n] matches the 10-bit logical value “0” that is the partial synchronization pattern. The detection processing circuit 54 causes the flag data fl
The logical value "1" is set in ag.

As described above, the detection processing circuit 54 detects the partial synchronization pattern in 10-bit units for the baseband signal S52, and when the partial synchronization pattern is detected, the flag data flag is set to the logical value "1". To
Further, the detection processing circuit 54 outputs the module Y [n] of the undecoded baseband signal S52 as the module X [n] of the baseband signal S54 when the flag data flag indicates the logical value "1". To do. As a result, the original baseband signal S41 shown in FIG. 4 is obtained as the baseband signal S54.

The bit conversion circuit 55 is a detection processing circuit 54.
The 120-bit baseband signal S54 input from is converted into a 20-bit baseband signal S31 and output.

An example of the overall operation of the communication system 1 shown in FIG. 1 will be described below. For example, a baseband signal S5 such as a content signal such as an image (video) or audio (voice) or an auxiliary signal is input to the transmission device 2 from an external device such as a video generation device. Then, in the encoder 11 of the transmitter 2, the baseband signal S5 is transmitted to the encoder 1
The baseband signal S12 is encoded by being encoded with 1, and the baseband signal S12 is output to the transmission unit 13.

Then, the transmitting section 13 transmits the baseband signal S2 generated by modulating the baseband signal S12 to the receiving device 3 in a wired or wireless manner. The baseband signal S2 is received by the receiving unit 21 of the receiving device 3,
The baseband signal S21 demodulated by the receiving unit 21 is output to the decoding unit 23 via the storage unit 22. Then, in the decoding unit 23, the baseband signal S21 is decoded to generate the baseband signal S23, and the baseband signal S23 is output to the decoder 24.

Then, in the decoder 24, the baseband signal S23 is decoded to obtain the baseband signal S2.
4 is generated and output to the transmission unit 25. Then, in the bit conversion circuit 41 of the transmission unit 25, the 20-bit baseband signal S24 is converted into a 120-bit baseband signal S41, and the baseband signal S41 is output to the encryption circuit 42 and the detection processing circuit 43. Then, in the encryption circuit 42, the baseband signal S41
Is encrypted to generate a baseband signal S42, and the baseband signal S42 is output to the detection processing circuit 43. Then, in the detection processing circuit 43, a portion matching the synchronization pattern added by the P / S conversion circuit 45 is detected in the baseband signal S42 by a predetermined detection unit, for example, 10
Detect in units of bits. Then, the detection processing circuit 4
3, a portion of a predetermined length following the detected portion in the baseband signal S42 is generated as a corresponding portion of the baseband signal S41, and a baseband signal S43 is generated. The band signal S43 is converted into a 20-bit baseband signal S44, and the baseband signal S44 is converted to P /
It is output to the S conversion circuit 45. Then, in the P / S conversion circuit 45, the parallel baseband signal S44
Is converted into a serial format HD-SDI signal S3, which is transmitted to the projector device 4. At this time, P /
The S conversion circuit 45 inserts the synchronization pattern used in the synchronization processing of the S / P conversion circuit 51 into the HD-SDI signal S3. Then, in the S / P conversion circuit 51 of the reception unit 31 of the projector device 4, the HD-S of the serial format is used.
The DI signal S3 is synchronously processed based on the synchronization pattern in the HD-SDI signal S3, converted into a parallel format baseband signal S51, and the baseband signal S51 is output to the bit conversion circuit 52. Then, in the bit conversion circuit 52, the 20-bit baseband signal S51
Is converted to a 120-bit baseband signal S52,
The baseband signal S52 is output to the decoding circuit 53 and the detection processing circuit 54. Then, in the decryption circuit 53, the baseband signal S52 is decrypted in the OFB mode of the common key block cipher AES to obtain the baseband signal S5.
3 is generated, and the baseband signal S53 is output to the detection processing circuit 54.

Then, in the detection processing circuit 54, it is determined whether the baseband signal S52 includes a partial synchronization pattern (10-bit logical value "0") which is a part of the synchronization pattern, for example, 10 bits. It is detected as a unit. Then, the detection processing circuit 54 generates a baseband signal S54 in which a portion having a predetermined length following the portion corresponding to the detected portion in the baseband signal S53 is set as the corresponding portion in the baseband signal S52. Then, in the bit conversion circuit 55, the 120-bit baseband signal S54 is converted into a 20-bit baseband video signal S31 and output to the projector processing unit 32. Then, the projector processing unit 32 outputs an image corresponding to the image signal S31 from the output unit 33.

As described above, according to the communication system 1, since the baseband signal itself transmitted and received between the receiving device 3 and the projector device 4 is encrypted,
It is possible to avoid illegal acquisition of transmitted / received content data.

Further, according to the communication system 1, even if the transmitter 25 of the receiver 3 encrypts and transmits the baseband signal based on the existing encryption algorithm, the S / P of the receiver 31 of the projector 4 is used. It is possible to prevent the synchronization pattern used for the synchronization processing in the conversion circuit 51 from occurring at an improper position in the baseband signal S3. Therefore, the synchronization detection in the S / P conversion circuit 51 of the projector device 4 can be accurately performed. Further, in the communication system 1, as described above, the existing encryption algorithm whose strength is already guaranteed can be used, and it is not necessary to newly develop the algorithm. Also, even if you find a vulnerability in the encryption algorithm you are using, or as a countermeasure against pirates, if you use a new encryption algorithm that suppresses the occurrence of prohibited code, just change to another existing encryption algorithm, There is no need to develop a new cryptographic algorithm.

Further, according to the communication system 1, when the projector device 4 is compatible with the communication of HD-SDI signals, the receiver 31 is mounted on the substrate and the substrate is simply mounted on the projector device 4. Then, the decoding function can be added to the projector device 4. This is the projector device 4
However, the same applies to other output devices.

Further, according to the communication system 1, it is possible to use CXG8001 manufactured by Sony Corporation as the P / S conversion circuit 45. As the S / P conversion circuit 51, it is possible to use CXG8002 manufactured by Sony Corporation. Furthermore, Sony Corporation's Multiplex / De-Mul
The tiplex device CXD9000 can be used before the encryption circuit 42 and the detection processing circuit 43 and after the decryption circuit 53 and the detection processing circuit 54.

Further, according to the communication system 1, the projector device 4 can be provided with the decoding function with a simple structure. Further, according to the communication system 1, since the projector function and the video distribution device function are separated, it is not necessary to store the content data in the projector arranged behind the screen in a movie theater or the like, and It becomes possible to centrally manage the content data in a remote place. That is, the content data can be stored in a physically secure room or the like, and the safety can be further increased. In the conventional system, the content data is stored in an encrypted state in the place where the projector is installed. That is,
When content data exists in the projector device arranged behind each screen and there are a plurality of screens in one movie theater, many content data storage locations exist.

Second Embodiment This embodiment is an embodiment corresponding to the third, fourth, eleventh and twelfth inventions. In the above-described first embodiment, the case where a part of the synchronization pattern is detected in 10-bit units is illustrated, but in the present embodiment, a case in which it is performed in 1-bit units is illustrated. FIG. 9 is an overall configuration diagram of the communication system 101 of this embodiment. As shown in FIG. 9, the communication system 101 includes, for example, a transmitter 2 and a receiver 103.
And a projector device 104. Receiver 10
3 includes, for example, the receiving unit 21, the storage unit 22, the decoding unit 23,
It has a decoder 24 and a transmitter 125. The projector device 104 includes a projector processing unit 32 and a receiving unit 131. In FIG. 9, constituent elements given the same reference numerals as those in FIG. 1 are the same as those described in the first embodiment. The present embodiment is characterized by the encryption process and the decryption process of the HD-SDI signal S103 transmitted from the receiving device 103 to the projector device 104.

In the communication system 101, for example, a baseband signal S5 such as a content signal such as an image (video) or audio (voice) or an auxiliary signal is input to the transmitting device 2 from an external device such as a video generating device. And
In the transmitter 2, the baseband signal S5 is encoded by the encoder 11 and then encrypted by the encryption unit 12, and the baseband signal S2 obtained thereby is transmitted to the receiver 103. Then, in the receiving device 103, the baseband signal S2 received by the receiving unit 21 is received.
Is stored in the storage unit 22, then read from the storage unit 22 and decoded by the decoding unit 23. After the baseband signal S23 obtained by the decoding is decoded by the decoder 24, the HD-SDI signal S23 is transmitted by the transmitter 125.
It is converted to 103 and output to the projector device 104. Then, in the projector device 104, the HD-SDI signal S103 received by the receiving unit 131 is converted into the video signal S31, and the projector processing unit 32 outputs the video corresponding to the video signal S31 from the output unit 33.

Hereinafter, the configuration and operation of the communication system 101 will be described in detail, centering on the configurations of the transmitting unit 125 and the receiving unit 131 shown in FIG. FIG. 10 is a configuration diagram of the transmission unit 125 and the reception unit 131 illustrated in FIG. In FIG. 10, the components denoted by the same reference numerals as those in FIG. 2 are the same as those described in the first embodiment.

[Transmission Unit 125] As shown in FIG. 10, the transmission unit 125 has, for example, a bit conversion circuit 41, an encryption circuit 42, a detection processing circuit 143, a bit conversion circuit 44, and a P / S conversion circuit 45. . Here, the transmission unit 125
Corresponds to the signal processing device of the third invention, and corresponds to the encryption circuit 42.
Corresponds to the encryption circuit of the present invention, and the detection processing circuit 143 corresponds to the signal processing circuit of the present invention. The detection processing circuit 143 is
It is determined whether or not a partial synchronization pattern showing a logical value "0" appears continuously in the baseband signal S42 for 23 bits. When the detection processing circuit 143 determines that the partial synchronization pattern appears, the detection processing circuit 143 starts from the bit next to the 23rd bit in the module to which the bit in the baseband signal S42 in which the partial synchronization pattern appears belongs. A baseband signal S143 for transmission using the corresponding bits of the baseband signal S41 is generated as the remaining bits in the module and all the bits of the next module. The detection processing circuit 143 uses the baseband signal S
143 is output to the bit conversion circuit 44.

11 to 13 are diagrams for explaining an example of the processing in the detection processing circuit 143, and FIG. 14 is a flowchart for explaining the processing. As shown in FIGS. 11 to 13, the detection processing circuit 143 processes the 120-bit baseband signals S41 and S42 in units of 10-bit modules to generate a 120-bit baseband signal S143. 11 to 13, when n is an integer satisfying 0 ≦ n ≦ 11,
X [n], E [n], and Y [n] are 10-bit modules that form the baseband signals S41, S42, and S143, respectively. The detection processing circuit 143 holds the flag data flag and sets a logical value “0” as an initial value thereof. Further, the detection processing circuit 143 is
Holds the bit indication data m, and its initial value is "0"
Is set. The detection processing circuit 143 has 0 ≦ n ≦ 11.
The integer n that satisfies the condition is incremented from the initial value “0” to “11” in order, and the processing illustrated in FIG. 5 is sequentially performed for each module. In FIG. 14, m is 10
The mth bit in the module of bits is shown.

Step ST30: Detection processing circuit 143
However, when performing processing for a new 10-bit module, the initial value “0” is set in the bit designation data m. Step ST31: The detection processing circuit 143 determines whether or not the bit designation data m is smaller than 10. If it is determined to be smaller, the process proceeds to step ST32, and if not, the process ends. That is, the process of step ST30 is performed again for the next 10-bit module.

Step ST32: Detection processing circuit 143
Determines whether or not the flag data flag indicates a logical value "1". If it is determined that the flag data flag indicates a logical value "1", the process proceeds to step ST33. If not, the process proceeds to step ST42. move on. Step ST33: The detection processing circuit 143 inputs the baseband signal S input as the mth bit Y [n] [m] in the nth module of the baseband signal S143.
Mth bit X [n] in the nth module of 41
Select [m] and output.

Step ST34: Detection processing circuit 143
Determines whether Y [n] [m] indicates the logical value "1". If the logical value indicates "1", the process proceeds to step ST35, and if the logical value indicates "0". Is step ST4
Proceed to the process of 3. Step ST35: The detection processing circuit 143 sets “0” to the continuous zero value data dc. Step ST36: The detection processing circuit 143 determines whether or not the continuous zero value data dc is “23”, that is, whether or not the partial synchronization pattern is detected, and when it is determined that the partial synchronization pattern is detected. If not, the process proceeds to step ST37.

Step ST37: Detection processing circuit 143
Sets "0" to the continuous zero value data dc. Step ST38: The detection processing circuit 143 displays “(9-
m) +10 ", and the result is set in the module zero insertion remaining number data bc. Step ST39: The detection processing circuit 143 determines whether or not the in-module zero insertion remaining number data bc is “0 or more”, and if it is “0 or more”, step S39.
The process proceeds to T40, and if not, step ST
Proceed to the processing of 44.

Step ST40: Detection processing circuit 143
Sets the logical value "1" to the flag data flag. Step ST41: The detection processing circuit 143 decrements the in-module zero insertion remaining number data bc by “1”.

Step ST42: Detection processing circuit 143
As the m-th bit Y [n] [m] in the n-th module of the baseband signal S143, the m-th bit E [n] [m] in the n-th module of the input baseband signal S42. To output.

Step ST43: Detection processing circuit 143
However, the continuous zero value data dc is incremented by "1".

Step ST44: Detection processing circuit 143
Sets a logical value "0" to the flag data flag.

Step ST45: Detection processing circuit 143
However, the bit instruction data m is incremented.

As described above, the detection processing circuit 143 is
For the baseband signal S42, the flag data flag is set to the logical value "1" when a partial synchronization pattern that is a part of the synchronization pattern is detected in 1-bit units. Further, the detection processing circuit 143, when the flag data flag indicates a logical value “1”, uses the encrypted base as the mth bit Y [n] [m] of the nth module of the baseband signal S143. Not the corresponding bit E [n] [m] of the band signal S42 but the corresponding bit X [n] [m] of the unencrypted baseband signal S41.
Is output. As a result, the synchronization pattern “3FF 3FF 000 000 00” is included in the baseband signal S42.
Even if "0000" occurs, the synchronization pattern is not included in the baseband signal S143.

[Reception Unit 131] As shown in FIG. 10, the reception unit 131 has, for example, an S / P conversion circuit 51, a bit conversion circuit 52, a decoding circuit 53, a detection processing circuit 154, and a bit conversion circuit 55. Here, the receiving unit 131 corresponds to the signal processing device of the fourth invention, the decoding circuit 53 corresponds to the decoding circuit of the present invention, and the detection processing circuit 154 corresponds to the signal processing circuit of the present invention. Detection processing circuit 154
Determines whether or not a partial synchronization pattern showing a logical value "0" appears in the baseband signal S52 continuously for 23 bits. Then, when the detection processing circuit 154 determines that the partial synchronization pattern appears, the baseband signal S5 is detected.
In the module to which the bit in which the partial synchronization pattern appears in 3 belongs, the baseband signal S52 is used as all the bits of the remaining module in the module from the bit next to the bit of the 23rd bit. Baseband signal S15 for transmission using corresponding bits of
4 is generated. The detection processing circuit 154 outputs the baseband signal S154 to the bit conversion circuit 55.

15 to 17 are diagrams for explaining an example of the process in the detection processing circuit 154, and FIG. 18 is a flowchart for explaining the process. As shown in FIGS. 15 to 17, the detection processing circuit 154 processes the 120-bit baseband signals S52 and S53 in units of 10-bit modules to generate a 120-bit baseband signal S154. 15 to 17, when n is an integer that satisfies 0 ≦ n ≦ 11,
Y [n], D [n], and X [n] are 10-bit modules that form the baseband signals S52, S53, and S154, respectively. The detection processing circuit 154 holds the flag data flag and sets the logical value “0” as its initial value. Further, the detection processing circuit 154 is
Holds the bit indication data m, and its initial value is "0"
Is set. The detection processing circuit 154 has 0 ≦ n ≦ 11.
The integer n that satisfies the condition is incremented from the initial value “0” to “11” in order, and the processing illustrated in FIG. 18 is sequentially performed for each module. In FIG. 18, m is 1
The m-th bit in a 0-bit module is shown.

Step ST50: Detection processing circuit 154
However, when performing processing for a new 10-bit module, the initial value “0” is set in the bit designation data m. Step ST51: The detection processing circuit 154 determines whether or not the bit designation data m is smaller than 10. If it is determined to be smaller, the process proceeds to step ST52, and if not, the process ends. That is, the process of step ST50 is performed again for the next 10-bit module.

Step ST52: Detection processing circuit 154
Determines whether the flag data flag indicates a logical value "1". If it is determined that the flag data flag indicates a logical value "1", the process proceeds to step ST53. If not, the process proceeds to step ST62. move on. Step ST53: The detection processing circuit 154 inputs the baseband signal S input as the mth bit X [n] [m] in the nth module of the baseband signal S154.
M-th bit Y [n] in the n-th module of 52
Select [m] and output.

Step ST54: Detection processing circuit 154
Determines whether Y [n] [m] indicates a logical value "1", and if it indicates a logical value "1", the process proceeds to step ST55, and if it indicates a logical value "0". Is step ST6
Proceed to the process of 3. Step ST55: The detection processing circuit 154 sets “0” to the continuous zero value data dc. Step ST56: The detection processing circuit 154 determines whether or not the continuous zero-value data dc is “23”, that is, whether or not the partial synchronization pattern is detected, and when it is determined that the partial synchronization pattern is detected, If not, the process proceeds to step ST57.

Step ST57: Detection processing circuit 154
Sets "0" to the continuous zero value data dc. Step ST58: The detection processing circuit 154 displays “(9-
m) +10 ", and the result is set in the module zero insertion remaining number data bc. Step ST59: The detection processing circuit 154 determines whether or not the in-module zero insertion remaining number data bc is “0 or more”, and if it is determined to be “0 or more”, step S59.
Proceed to the process of T60, and if not, step ST
Proceed to 64.

Step ST60: Detection processing circuit 154
Sets the logical value "1" to the flag data flag. Step ST61: The detection processing circuit 154 decrements the in-module zero insertion remaining number data bc by “1”.

Step ST62: Detection processing circuit 154
As the m-th bit X [n] [m] in the n-th module of the baseband signal S154, the m-th bit D [n] [m] in the n-th module of the input baseband signal S53. To output.

Step ST63: Detection processing circuit 154
However, the continuous zero value data dc is incremented by "1".

Step ST64: Detection processing circuit 154
Sets a logical value "0" to the flag data flag.

Step ST65: Detection processing circuit 154
However, the bit instruction data m is incremented.

As described above, the detection processing circuit 154 is
For the baseband signal S52, the flag data flag is set to the logical value "1" when a partial synchronization pattern that is a part of the synchronization pattern is detected in 1-bit units. In addition, the detection processing circuit 154, when the flag data flag indicates a logical value “1”, determines the decoded baseband as the mth bit X [n] [m] of the nth module of the baseband signal S154. Instead of the corresponding bit D [n] [m] of the signal S53, the corresponding bit Y [n] [m] of the baseband signal S52 before decoding is output.
Thereby, the same baseband signal S154 as the baseband signal S41 can be obtained.

The overall operation example of the communication system 101 described above is the same as the overall operation of the communication system 1 of the first embodiment described above except that the processing in the detection processing circuit 143 and the detection processing circuit 154 is performed as described above. Same as the example. Further, the communication system 101 can obtain the same effect as that of the communication system 1 of the first embodiment.

Modification of the Present Embodiment In the above-described embodiments, the case where the detection unit of the partial synchronization pattern is 10 bits and the case where the detection unit is 1 bit are illustrated. It is not particularly limited as long as it is configured, and for example, a continuous 20-bit logical value “1” and the following 23 consecutive logical values.
A 43-bit partial synchronization pattern in which bit logical values “0” are consecutive may be used. Moreover, as the encryption circuit 42 and the decryption circuit 53, those using a stream cipher or a random number generator may be used.

Third Embodiment In the above-described first embodiment, the case where the OFB mode is used as the encryption and decryption method of the HD-SDI signal transmitted from the receiving device to the projector device has been illustrated. , CFB (Cipher FeedBack) mode is used as an example. The said embodiment is 5th, 6th, 1st.
It is an embodiment corresponding to the third and fourteenth inventions. FIG. 19
FIG. 1 is an overall configuration diagram of a communication system 201 of this embodiment. As shown in FIG. 19, the communication system 201 includes, for example, a transmission device 2, a reception device 203, and a projector device 204. The reception device 203 includes, for example, a reception unit 21, a storage unit 22, a decoding unit 23, a decoder 24, and a transmission unit 225. The projector device 204 has a projector processing unit 32 and a receiving unit 231. Figure 1
9, the components denoted by the same reference numerals as those in FIG.
It is the same as that described in the embodiment.

In the communication system 201, the transmitting unit 225 and the receiving unit 231 are different from those in the first embodiment. Hereinafter, the configuration and operation of the communication system 201 will be described in detail centering on the configurations of the transmission unit 225 and the reception unit 231 illustrated in FIG. FIG. 20 is a diagram for explaining the transmission unit 225 and the reception unit 231 shown in FIG. 20, constituent elements given the same reference numerals as those in FIG. 2 are the same as those described in the first embodiment.

[Transmission Unit 225] As shown in FIG. 20, the transmission unit 225 includes, for example, a bit conversion circuit 41, an encryption / decryption circuit.
Detection processing circuit 243, bit conversion circuit 44 and P / S
It has a conversion circuit 45. FIG. 21 is a block diagram of the encryption / detection processing circuit 243. As shown in FIG. 21, the encryption / detection processing circuit 243 has, for example, a memory 261, a shift register 262, a block encryption circuit 263, an addition circuit 264, and a detection processing circuit 43. Here, the encryption / detection processing circuit 243 corresponds to the signal processing device of the fifth invention, the block encryption circuit 263 corresponds to the block encryption circuit of the present invention, and the addition circuit 264 corresponds to the arithmetic circuit of the present invention. The detection processing circuit 43 is the same as that described in the first embodiment with reference to FIGS. 4 and 5, and the baseband signal S264 shown in FIG. 4 is used as the baseband signal S42.
Is used.

The memory 261 is a block cipher circuit 263.
Initial value data S261a and key data S used in
261b is stored. The shift register 262 shifts this to, for example, 120 bits higher toward the MSB,
1 output by the detection processing circuit 43 to the LSB 120 bits
Input 20-bit baseband signal S243,
The 8-bit baseband signal S262 is generated and output to the block encryption circuit 263. Shift register 2
In 62, initial value data S261a read from the memory 261 is set as an initial value. The block encryption circuit 263 performs block encryption processing based on the baseband signal S262 input from the shift register 262 and the key data S261b read from the memory 261 to generate a baseband signal S263. Then, the upper 120 bits of the baseband signal S263 are extracted and output to the adding circuit 264.

The adder circuit 264 performs an exclusive OR (EXOR) operation of the baseband signal S41 input from the bit conversion circuit 41 and the signal obtained by extracting the upper 120 bits of the baseband signal S263 to perform the baseband signal SEX. S264 is generated and output to the detection processing circuit 265.

The detection processing circuit 43 uses the baseband signal S264 as the baseband signal S42 shown in FIG. 4 to perform the processing described in the first embodiment with reference to FIGS. 4 and 5 to obtain the baseband signal S243. It is generated and output to the bit conversion circuit 44 shown in FIG.

An operation example of the encryption / detection processing circuit 243 will be described below. The baseband signal S243 generated by the detection processing circuit 43 is stored in the lower 120 bits of the shift register 262 which is shifted by 120 bits toward the MSB, and the baseband signal S262 is output to the block encryption circuit 263. Then, the block cipher circuit 263
, The baseband signal S262 and the memory 261
Block encryption processing is performed on the basis of the key data S261b read from to generate the baseband signal S263. Then, the 128-bit baseband signal S2
The upper 120 bits of 63 are output to the adder circuit 264. Then, in the adder circuit 264, an exclusive OR (EXOR) operation of the baseband signal S41 input from the bit conversion circuit 41 and the upper 120 bits of the baseband signal S263 is performed to perform the baseband signal S264.
Is generated and is output to the detection processing circuit 43. Then, in the detection processing circuit 43, the baseband signal S264 shown in FIG. 4 is used as the baseband signal S264, and the processing described in the first embodiment with reference to FIGS. 4 and 5 is performed to obtain the baseband signal S243. It is generated and output to the bit conversion circuit 44 shown in FIG.

[Reception Unit 231] As shown in FIG. 20, the reception unit 231 has, for example, an S / P conversion circuit 51, a bit conversion circuit 52, a decoding / detection processing circuit 254, and a bit conversion circuit 55. FIG. 22 shows the decoding / detection processing circuit 2
It is a block diagram of 54. As shown in FIG. 22, the decoding / detection processing circuit 254 includes, for example, a memory 271, a shift register 272, a block decoding circuit 273, and an adding circuit 274.
And a detection processing circuit 54. Here, the decoding / detection processing circuit 254 corresponds to the signal processing device of the sixth invention,
The block decoding circuit 273 is the block decoding circuit of the present invention,
The adder circuit 274 corresponds to the arithmetic circuit of the present invention. The detection processing circuit 54 is the same as that described in the first embodiment with reference to FIGS. 7 and 8, and uses the baseband signal S274 as the baseband signal S53 shown in FIG.

The memory 271 has a block decoding circuit 273.
Initial value data S271a and key data S used in
271b is stored. The shift register 272 shifts this to, for example, 120 bits higher toward the MSB,
The bit conversion circuit 5 shown in FIG.
120-bit baseband signal S52 input from 2
Is input to generate a 128-bit baseband signal S262, which is output to the block decoding circuit. Initial value data S271a read from the memory 271 is set in the shift register 272 as an initial value. The block decryption circuit 273 performs block decryption processing based on the baseband signal S272 input from the shift register 272 and the key data S271b read from the memory 271 to generate a baseband signal S273. Then, the upper 120 bits of the baseband signal S273 are extracted and output to the adding circuit 274.

The adder circuit 274 performs an exclusive OR (EXOR) operation of the baseband signal S52 input from the bit conversion circuit 52 and the signal in which the upper 120 bits of the baseband signal S273 is extracted to perform a baseband signal. S274 is generated and output to the detection processing circuit 54.

The detection processing circuit 54 uses the baseband signal S274 as the baseband signal S53 shown in FIG. 7 to perform the processing described in the first embodiment with reference to FIGS. 7 and 8 to obtain the baseband signal S254. It is generated and output to the bit conversion circuit 55 shown in FIG.

An operation example of the decoding / detection processing circuit 254 will be described below. The 120-bit baseband signal S52 input from the bit conversion circuit 52 shown in FIG.
Shift register 27 shifted by 120 bits toward
Is stored in the lower 120 bits of 2 and the addition circuit 2
74 and the detection processing circuit 54. Then, in the block decoding circuit 273, the baseband signal S2
72 and the key data S27 read from the memory 271.
A block encryption process is performed based on 1b and a baseband signal S273 is generated. Then, the upper 120 bits of the 128-bit baseband signal S273 is output to the adding circuit 274. Then, in the adding circuit 274, the baseband signal S52 and the baseband signal S2 are added.
Exclusive OR with the upper 120 bits of 73 (EXOR)
Calculation is performed to generate a baseband signal S274,
This is output to the detection processing circuit 54. Then, in the detection processing circuit 54, the baseband signal S5 shown in FIG.
Using the baseband signal S274 as 3, the process described in the first embodiment with reference to FIGS. 7 and 8 is performed to generate the baseband signal S254, which is output to the bit conversion circuit 55 shown in FIG. It

An example of the overall operation of the communication system 201 shown in FIGS. 19 and 20 will be described below. For example, a baseband signal S5 such as a content signal such as an image (video) or audio (voice) or an auxiliary signal is input to the transmission device 2 from an external device such as a video generation device. Then, in the encoder 11 of the transmitter 2, the baseband signal S5 is encoded by the encoder 11 to generate the baseband signal S11, which is output to the encryption unit 12. Then, the encryption unit 12 encrypts the baseband signal S11 to generate the baseband signal S12, which is output to the transmission unit 13.

Then, the transmitting unit 13 transmits the baseband signal S2 generated by modulating the baseband signal S2 to the receiving device 203 in a wired or wireless manner. The baseband signal S2 is received by the receiving unit 21 of the receiving device 203 and demodulated by the receiving unit 21.
Is output to the decoding unit 23 via the storage unit 22. Then, after the baseband signal S21 is decoded in the decoding unit 23, it is decoded in the decoder 24 and the baseband signal S24 generated thereby is transmitted in the transmission unit 225.
Is output to. Then, in the transmitter 225, the serial baseband signal S24 is converted into the bit conversion circuit 4
1 and the 120-bit baseband signal S41
And is output to the encryption / detection processing circuit 243. Then, the encryption / detection processing circuit 243 performs the above-described processing to generate the baseband signal S243, which is output to the bit conversion circuit 44. Then, in the bit conversion circuit 44, the 120-bit baseband signal S243 is converted into the 20-bit baseband signal S44 and output to the P / S conversion circuit 45. And P
In the / S conversion circuit 45, the baseband signal S44 is a serial format HD-SDI signal S including a synchronization pattern.
It is converted into 203 and transmitted.

The HD-SDI signal S203 is received by the receiver 231 of the projector device 204. Then, in the S / P conversion circuit 51 of the projector device 204,
The HD-SDI signal S203 is synchronously processed based on the synchronization pattern in the HD-SDI signal, converted into a parallel format baseband signal S51, and the baseband signal S51.
Is output to the bit conversion circuit 52. Then, in the bit conversion circuit 52, the 20-bit baseband signal S
51 is converted into a 120-bit baseband signal S52, and the baseband signal S52 is decoded / detected by the decoding / detection processing circuit 25.
4 is output. Then, in the decoding / detection processing circuit 254, the above-described processing is performed and the baseband signal S2
54 is generated and is output to the bit conversion circuit 55. Then, in the bit conversion circuit 55, the 120-bit baseband signal S254 is converted into the 20-bit HD-S.
The DI signal S231 is converted to the projector processing unit 32.
Is output to. Then, the projector processing unit 32 outputs an image corresponding to the image signal S231 from the output unit 33.

With the communication system 201, the same effect as that of the communication system 1 of the first embodiment can be obtained.

Modification of Third Embodiment In the above-described third embodiment, the first and second detection processing circuits 43 and 54 shown in FIGS.
Although what has been described in the embodiment has been illustrated, as shown in FIGS. 23 and 24, the detection processing circuit 143 and the detection processing circuit 154 described in the second embodiment may be used instead of them. In this case, the operations described in the first embodiment are performed as the operations of the detection processing circuit 143 and the detection processing circuit 154, and the other operations are the same as those described in the third embodiment. The modification is an embodiment corresponding to the seventh, eighth, fifteenth and sixteenth inventions.

The present invention is not limited to the above embodiments. In the embodiment described above, the transmitter 25 and the receiver 3
Although AES of common key block cipher was mentioned as the encryption method of No. 1, other than AES, DES (Data Encryption
Common key cryptography such as Standard) or triple DES may be used as well. In this case, the encryption process and the decryption process are performed using the 60-bit baseband signal.

Further, in the above-described embodiment, the case where the present invention is applied to the receiving device and the projector device is illustrated, but it may be a communication device that encrypts and transmits a baseband signal and performs processing based on a synchronization pattern. For example, the present invention can be applied to other communication devices (signal processing devices). The baseband signal of the present invention may be a signal such as an audio signal or a control signal in addition to the video signal.

[0122]

As described above, according to the present invention,
It is possible to provide a signal processing device, a method thereof, and a communication system capable of encrypting and transmitting a serial signal with a simple configuration and enabling proper synchronization on the transmitting / receiving side.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a communication system according to a first embodiment of the present invention.

FIG. 2 is a transmission unit (HD-) of the receiving apparatus shown in FIG.
SDI) and the receiver of the projector device (HD-SD
It is a block diagram of I).

FIG. 3 is a block diagram of the encryption circuit shown in FIG.

FIG. 4 is a diagram for explaining an example of processing in a detection processing circuit of the transmission unit shown in FIG.

5 is a flow chart for explaining the processing shown in FIG.

FIG. 6 is a block diagram of the decoding circuit shown in FIG.

FIG. 7 is a diagram for explaining an example of processing in the detection processing circuit of the receiving unit shown in FIG.

FIG. 8 is a flow chart for explaining the processing shown in FIG.

FIG. 9 is an overall configuration diagram of a communication system according to a second embodiment of the present invention.

10 is a diagram illustrating a transmitter (H of the receiving device illustrated in FIG. 9;
D-SDI) and the receiver of the projector device (HD-
It is a block diagram of SDI).

11 is a diagram for explaining an example of processing in the detection processing circuit of the transmission unit shown in FIG. 10, and is a diagram for explaining a baseband signal S41.

12 is a diagram for explaining an example of processing in the detection processing circuit of the transmission unit shown in FIG. 10, and is a diagram for explaining a baseband signal S42.

13 is a diagram for explaining an example of processing in the detection processing circuit of the transmission unit shown in FIG. 10, and is a diagram for explaining a baseband signal S43.

FIG. 14 is a flowchart for explaining processing of the detection processing circuit of the transmission unit shown in FIG.

15 is a diagram for explaining an example of a process in the detection processing circuit of the reception unit of the projector device shown in FIG. 10, and is a diagram for explaining a baseband signal S52.

16 is a diagram for explaining an example of a process in the detection processing circuit of the reception unit of the projector device shown in FIG. 10, and is a diagram for explaining a baseband signal S53.

17 is a perspective view of the projector device 4 shown in FIG.
FIG. 6 is a diagram for explaining an example of processing in the receiving unit of FIG. 4 and a diagram for explaining a baseband signal S154.

18 is a flowchart for explaining the process of the receiving section of the projector device 4 shown in FIG. 10 shown in FIG. 10;

FIG. 19 is an overall configuration diagram of a communication system according to a third embodiment of the present invention.

20 is a transmission unit (HD-SDI) of the reception device and a reception unit (H of the projector device shown in FIG.
It is a block diagram of D-SDI).

21 is a configuration diagram of the encryption / detection processing circuit of the transmission unit shown in FIG. 20.

22 is a configuration diagram of the decoding / detection processing circuit of the receiving unit shown in FIG. 20.

FIG. 23 is a block diagram of an encryption / detection processing circuit of the transmission unit shown in FIG. 20 according to a modification of the third embodiment of the present invention.

FIG. 24 is a configuration diagram of a decoding / detection processing circuit of a receiving unit shown in FIG. 20 according to a modification of the third embodiment of the present invention.

FIG. 25 is an overall configuration diagram of a communication system according to a conventional technique.

FIG. 26 is a diagram for explaining a synchronization signal.

[Explanation of symbols]

1, 101, 201 ... Communication system, 2 ... Transmitting device,
3, 103, 203 ... Receiving device, 4, 104, 204 ...
Projector device, 11 ... Encoder, 12 ... Encryption unit, 13 ... Transmission unit, 21 ... Reception unit, 22 ... Storage unit, 23
... Decoding section, 24 ... Decoder, 25, 125, 225 ... Transmitting section, 31, 131, 231 ... Receiving section, 32 ... Projector processing section

Claims (31)

[Claims] 1. An encryption circuit for encrypting a first digital signal to generate a second digital signal, and a partial synchronization pattern which is added before transmission and constitutes a part of a synchronization pattern used on the receiving side. A portion having a predetermined length following the detected portion in the second digital signal is detected in the first digital signal, and the first portion is detected in the second digital signal.
And a signal processing circuit for generating a third digital signal corresponding to the corresponding portion of the digital signal. 2. The signal processing circuit divides the second digital signal into modules having the same number of bits as the partial synchronization pattern, compares each module in sequence with the partial synchronization pattern, and as a result of the comparison, the partial synchronization pattern is obtained. The third digital signal using the corresponding part in the first digital signal is generated as a module next to the matched module when the synchronization pattern and the module match. Signal processing equipment. 3. The signal processing circuit sets a first logic value as an initial value in the flag data, and when the flag data indicates a second logic value, the corresponding one in the first digital signal Outputting a portion as the third digital signal, setting a first logical value in the flag data, and if the flag data indicates a first logical value, the corresponding portion in the second digital signal Is output as the third digital signal, and it is determined whether the module of the corresponding portion of the second digital signal matches the partial synchronization pattern. The signal processing device according to claim 2, wherein the value is set. 4. The block cipher circuit for generating new key series data by using the fed back key series data, the key series data generated by the block cipher circuit, and the first digital circuit. The signal processing device according to claim 1, further comprising an arithmetic circuit that performs an arithmetic operation using the signal and generates the second digital signal. 5. The signal processing device according to claim 4, wherein the arithmetic circuit adds the key sequence data and the first digital signal to generate the second digital signal. 6. The encryption circuit includes a random number generation circuit that generates a random number, and an arithmetic circuit that performs an operation using the random number and the first digital signal to generate the second digital signal. The signal processing device according to claim 1, comprising. 7. The digital signal is a baseband signal, the signal generation circuit generates the third digital signal in a parallel format in units of a plurality of bits, and the signal processing device includes the parallel format. 2. The signal processing device according to claim 1, further comprising a conversion circuit that converts the third digital signal of 1. into a serial format including the synchronization pattern. 8. The signal processing device according to claim 1, wherein the synchronization pattern is a pattern including a plurality of the partial synchronization patterns. 9. The signal processing apparatus according to claim 1, wherein the encryption circuit independently encrypts image data, audio data and auxiliary data in the baseband signal. 10. A first digital signal and a second digital signal obtained by encrypting the first digital signal so as not to generate a synchronization pattern are mixed and generated based on a predetermined rule, A signal processing device for decoding a received third digital signal, comprising: a decoding circuit for decoding the third digital signal to generate a fourth digital signal; and a portion forming a part of a synchronization pattern. A portion matching the synchronization pattern is detected in the third digital signal, and a portion of a predetermined length following the portion corresponding to the detected portion in the fourth digital signal is added to the third digital signal. And a signal processing circuit that generates a fifth digital signal as a corresponding portion. 11. The signal processing circuit divides the third digital signal into modules having the same number of bits as the partial synchronization pattern, and sequentially compares each module with the partial synchronization pattern. When the synchronization pattern and the module match, the third portion using the corresponding portion in the third digital signal as the portion corresponding to the module next to the matched module in the fourth digital signal. The signal processing device according to claim 10, which generates a digital signal of No. 5. 12. The signal processing circuit sets a first logical value as an initial value in the flag data, and when the flag data indicates a second logical value, the corresponding in the third digital signal is obtained. Outputting a portion as the fifth digital signal, setting a first logical value in the flag data, and if the flag data indicates the first logical value, the corresponding portion in the fourth digital signal Is output as the fifth digital signal, it is determined whether the module of the corresponding portion of the third digital signal matches the partial synchronization pattern, and if it is determined that the second logic is added to the flag data. The signal processing device according to claim 11, wherein a value is set. 13. The block decoding circuit, wherein the decoding circuit generates new key series data using the fed back key series data, the key series data generated by the block decoding circuit, and the third digital signal. 11. An arithmetic circuit for performing an arithmetic operation by using and to generate the fourth digital signal.
The signal processing device according to. 14. The signal processing device according to claim 13, wherein the arithmetic circuit adds the key sequence data and the third digital signal to generate the fourth digital signal. 15. The encryption circuit includes: a random number generation circuit that generates a random number; and an arithmetic circuit that performs an arithmetic operation using the random number and the third digital signal to generate the fourth digital signal. The signal processing device according to claim 10, which has. 16. The digital signal is a baseband signal, and when the third digital signal in a serial format including the synchronization pattern is received, the third digital signal is serialized based on the synchronization pattern. The signal processing device according to claim 10, further comprising a conversion circuit for converting the format. 17. An encryption circuit for encrypting a first digital signal to generate a second digital signal, and the same logical value continuously shown for a first bit number and added before transmission and used by a receiving side. A sync pattern including a partial sync pattern to be detected is defined, and when the partial sync pattern is detected in the second digital signal, the next partial sync pattern in the second digital signal is detected. Third bit for transmission using the corresponding part of the first digital signal as the part from the bit of the first digital signal to the bit of the second bit number.
And a signal processing circuit for generating the digital signal. 18. The first digital signal and the first digital signal are encrypted so as not to generate a synchronization pattern including a partial synchronization pattern that continuously shows the same logical value for the first bit number. A second digital signal mixed with a second digital signal based on a predetermined rule, and decoding the received third digital signal. A decoding circuit for generating a digital signal of No. 4, and detecting a portion in which the logical value continuously appears for the first number of bits in the third digital signal, and detecting the portion in the fourth digital signal. As a part from the next bit following the part corresponding to to the bit for the second bit number,
A signal processing circuit for generating a fifth digital signal using a corresponding portion of the third digital signal. 19. A first digital signal and a second digital signal obtained by encrypting the first digital signal are input,
A signal processing circuit that outputs a third digital signal for transmission, a block cipher circuit that generates key sequence data using the third digital signal, and the key sequence data and the first digital signal are used. And a calculation circuit for performing the calculation to generate the second digital signal, wherein the signal processing circuit is used on the receiving side and forms a part of a synchronization pattern added before transmission, and a partial synchronization pattern. The matching portion is detected in the second digital signal, and a portion of the predetermined length following the detected portion in the second digital signal is set as a corresponding portion in the first digital signal. A signal processing device having a digital signal of 3. 20. The first digital signal and the first digital signal are provided so that a synchronization pattern used for synchronization processing on the receiving side does not occur.
Is a signal processing device that decodes a received third digital signal generated by mixing a pattern included in the second digital signal obtained by encrypting the digital signal of 1) based on a predetermined rule. And a block decryption circuit for generating key sequence data using the third digital signal, and an operation using the key sequence data and the third digital signal to generate the fourth digital signal. An arithmetic circuit; and a signal processing circuit that receives the third digital signal and the fourth digital signal and generates a fifth digital signal for transmission, wherein the signal processing circuit includes the synchronization pattern. A part of the third digital signal which coincides with the partial synchronization pattern forming a part of the third digital signal is detected, and a part of a predetermined length following the part corresponding to the detected part in the fourth digital signal is detected. , A signal processing device for generating a fifth digital signal which is a corresponding part of the third digital signal. 21. Inputting a first digital signal and a second digital signal obtained by encrypting the first digital signal,
A signal processing circuit that outputs a third digital signal for transmission, a block cipher circuit that generates key sequence data using the third digital signal, and the key sequence data and the first digital signal are used. An arithmetic circuit for performing the arithmetic operation to generate the second digital signal, wherein the signal processing circuit includes a partial synchronization pattern continuously showing the same logical value for the first bit number and is added before transmission. And a sync pattern used on the receiving side is defined, and when the partial sync pattern is detected in the second digital signal, the next partial sync pattern in the second digital signal is detected. Signal processing device for generating the third digital signal by using the corresponding portion of the first digital signal as the portion from the bit to the second number of bits. 22. A first digital signal and a second digital signal obtained by encrypting the first digital signal are mixed and generated so that a synchronization pattern used for the synchronization processing does not occur, and reception is performed. And a block decoding circuit for generating key sequence data using the third digital signal, the key sequence data and the third digital signal. An arithmetic circuit for performing an arithmetic operation to generate the fourth digital signal, and a signal for inputting the third digital signal and the fourth digital signal to generate a fifth digital signal for transmission. A processing circuit, wherein the signal processing circuit detects a portion in the third digital signal where the logical value continuously appears for the first bit number, and detects the portion in the fourth digital signal. did As part of the next bit following the portion corresponding to the min up bits of the second number of bits minutes,
A signal processing device for generating the fifth digital signal using a corresponding portion of the third digital signal. 23. A signal processing method performed by a signal processing device, wherein a first digital signal is encrypted to generate a second digital signal, and a part of a synchronization pattern which is added before transmission and used on the receiving side. A part of the first digital signal that matches the partial synchronization pattern forming the second digital signal is detected, and a part of the second digital signal that has a predetermined length following the detected part is included in the first digital signal. A signal processing method for generating a third digital signal as a corresponding portion. 24. The first digital signal and the second digital signal obtained by encrypting the first digital signal are prescribed in a prescribed manner so that a synchronization pattern used for synchronization processing on the receiving side does not occur. A signal processing method in which a signal processing device performs decoding of a received third digital signal mixedly generated based on the above, wherein the third digital signal is decoded to generate a fourth digital signal, A part of the sync pattern that matches the partial sync pattern is detected in the third digital signal, and a part of a predetermined length following the part in the fourth digital signal corresponding to the detected part is detected. , A signal processing method for generating a fifth digital signal, which is a corresponding part of the third digital signal. 25. A signal processing method carried out by a signal processing device, wherein a first digital signal is encrypted to generate a second digital signal, and the same logical value is continuously shown for a first number of bits. Detecting a partial sync pattern in the second digital signal when a sync pattern including a sync pattern that is added before transmission and used on the receiving side is defined; and the partial sync pattern is detected in the second digital signal. Signal processing for generating a third digital signal for transmission using a corresponding portion of the first digital signal as a portion from the next bit to the bit of the second bit number following the partial synchronization pattern Method. 26. The first digital signal and the first digital signal so as not to generate a synchronization pattern which includes a partial synchronization pattern continuously showing the same logical value for the first bit number and which is added before transmission and used on the receiving side. And a second digital signal obtained by encrypting the second digital signal are mixed based on a predetermined rule, and a signal processing method performed by a signal processing device that decodes a received third digital signal is performed. And decoding the third digital signal to generate a fourth digital signal, detecting a portion in the third digital signal where the logical value continuously appears for the first bit number, A fifth part using the corresponding part of the third digital signal as the part from the next bit following the part corresponding to the detected part in the fourth digital signal to the bit of the second bit number. Digital signal Signal processing method for generating. 27. Inputting a first digital signal and a second digital signal obtained by encrypting the first digital signal,
A first step of outputting a third digital signal for transmission, a second step of generating key sequence data using the third digital signal, the key sequence data and the first digital signal And a third step of performing an operation to generate the second digital signal, and in the first step, constitutes a part of a synchronization pattern that is added before transmission and is used on the receiving side. A portion that matches the partial synchronization pattern is detected in the second digital signal, and a portion of the predetermined length following the detected portion in the second digital signal corresponds to the corresponding portion in the first digital signal. And a signal processing method for generating the third digital signal. 28. A first digital signal and a second digital signal obtained by encrypting the first digital signal are mixed and generated so that a synchronization pattern used for synchronization processing on the receiving side does not occur. A signal processing method performed by a signal processing device that decodes a received third digital signal, the first step of generating key sequence data using the third digital signal; And a second digital signal for performing a calculation using the third digital signal to generate the fourth digital signal, and inputting the third digital signal and the fourth digital signal for transmission And a third step of generating a fifth digital signal of, wherein in the third step, a portion that matches a partial synchronization pattern forming a part of the synchronization pattern is included in the third digital signal. Detect and before A portion of a predetermined length following the portion corresponding to the detected portion in the fourth digital signal,
A signal processing method for generating a fifth digital signal which is a corresponding part of the third digital signal. 29. A first digital signal and a second digital signal obtained by encrypting the first digital signal are input,
A first step of outputting a third digital signal for transmission, a second step of generating key sequence data by performing block encryption using the third digital signal, the key sequence data and the And a third step of performing an operation using the first digital signal to generate the second digital signal, wherein the same logical value is continuously output for the first bit number in the first step. The sync pattern that is added before transmission and is used on the receiving side is specified.
When the partial synchronization pattern is detected in the second digital signal, the portion from the next bit to the second number of bits following the detected partial synchronization pattern in the second digital signal And a signal processing method for generating the third digital signal using a corresponding portion of the first digital signal. 30. A first digital signal and a second digital signal obtained by encrypting the first digital signal are generated in a mixed manner so that a synchronization pattern used for synchronization processing on the receiving side does not occur. A signal processing method performed by a signal processing device for decoding a received and received third digital signal, comprising: a first signal generating a key sequence data by performing a flock encryption using the third digital signal. A second step of performing an operation using the key sequence data and the third digital signal to generate the fourth digital signal, the third digital signal and the fourth digital signal And a third step of generating a fifth digital signal for transmission, wherein in the third step, the logical value is equal to the first bit number in the third digital signal. Check the part that appears continuously Then, the corresponding portion of the third digital signal is used as the portion from the next bit following the portion corresponding to the detected portion in the fourth digital signal to the second number of bits. A signal processing method for generating the fifth digital signal. 31. A communication system comprising: a receiving device that encrypts and transmits a received baseband signal; and an output device that decodes and outputs the baseband signal transmitted by the receiving device, wherein the receiving device. Receiving means for receiving the first digital signal, and a second means for encrypting the received first digital signal
Of the encryption circuit for generating the digital signal and the part of the synchronization pattern used on the receiving side that matches the partial synchronization pattern are detected in the second digital signal, and the second digital signal is detected. A signal processing circuit for generating a third digital signal in which a portion of a predetermined length following the detected portion of is a corresponding portion in the first digital signal, and the output device receives the received digital signal. A decoding circuit that decodes a third digital signal to generate a fourth digital signal, a part that matches the partial synchronization pattern is detected in the third digital signal, and the part in the fourth digital signal is detected. A signal processing circuit for generating a fifth digital signal, in which a portion having a predetermined length following the portion corresponding to the detected portion is set as the corresponding portion in the third digital signal; and the fifth digital signal. Communication system and an output unit for performing corresponding output.