JP2003283369A - Correlation detecting device of spread spectrum communication system and correlation detecting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the electric power consumption by stopping a part of a matched filter in response to the reception quality of received signals. <P>SOLUTION: The matched filter 6 for examining the correlation of a received row of spread spectrum received codes with back diffusion codes is composed of a shift register in which each bit of the row of spread spectrum received codes is individually inputted, bitwise filters MF<SB>0</SB>-MFM<SB>-1</SB>each composed of an exclusive logical add circuit and an adder and an adder AD which adds their outputs. Demodulated data signals before error correction which are obtained by demodulating the row of spread spectrum received codes and demodulated data signals after error compensation are supplied to a bit error number counter 12 for calculating the number of bit errors. According to the result, a bit error rate is calculated by a reception quality judging circuit 13 and is compared to the bit error rate threshold value and the reception quality is judged. On the basis of the result of judgment, bitwise filters to be actuated are selected by a search controlling circuit 14. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication system correlation detection device and a correlation for obtaining a correlation output for detecting a correlation peak between a spread spectrum received signal and a spread code sequence in a spread spectrum communication system. Regarding the detection method, the power consumption is particularly reduced.

[0002]

2. Description of the Related Art As a correlation detecting device in a conventional spread spectrum communication system, for example, Japanese Patent Laid-Open No. 9-46173 is used.
Japanese Patent Laid-Open No. 9-32 (hereinafter referred to as a first conventional example).
What is described in Japanese Patent No. 1667 (hereinafter referred to as a second conventional example) is known. In the first conventional example, a plurality of N sample and hold circuits that hold an input signal while shifting it, a plurality of N multipliers that multiply the output of this sample and hold circuit by a multiplier registered in a register, and each multiplication A matched filter with an adder that adds the multiplier output of the multiplier, and supplies only the sample-and-hold circuit with a predetermined window width centered on the peak of the output of the matched filter after the completion of the initial synchronization acquisition. Then, after that, power is sequentially supplied to the sample-and-hold circuits in the subsequent stages, and when the signal holding by all the sample-and-hold circuits is completed, calculation is performed by the entire circuit to suppress power consumption.

In the second conventional example, the received spread spectrum signal is demodulated by a multiplier into a baseband signal, and the demodulated signal is input to a complex type matched filter which is intermittently driven by a power supply control unit and synchronized. When the power calculator detects that the output of this complex matched filter has a peak output of a predetermined value or more, the correlator controller operates the n correlators to receive the signals. The signals are synchronously tracked and inversely converted, and the outputs of the correlators are RAKE-combined by the RAKE combining and demodulation unit and demodulated.

[0004]

However, in the first conventional example, after the completion of the initial synchronization acquisition,
Power is supplied only to the sample-and-hold circuit with a predetermined window width centered on the peak of the output of the matched filter, and then sequentially to the sample-and-hold circuits in the subsequent stages, so that all sample-and-hold circuits can hold the signal. Power consumption can be suppressed by performing calculation by the entire circuit at the time of completion, but since the set predetermined power supply pattern is repeated regardless of the reception quality of the received signal,
There is an unsolved problem that there is a limit to the suppression of power consumption.

Further, in the second conventional example, since the complex matched filter is driven intermittently to perform synchronization acquisition, the complex matched filter is in a drive state after receiving the reception signal. If there is a large timing deviation until it becomes, it will affect the demodulation of the received signal, so there is a limit to how long the intermittent drive interval of the complex matched filter can be, so there is a limit to the suppression of power consumption. There is an unsolved problem.

Therefore, the present invention has been made by paying attention to the unsolved problem of the above-mentioned conventional example, and it is intended to reduce the power consumption by stopping a part of the matched filter according to the reception quality of the received signal. It is an object of the present invention to provide a correlation detection device and a correlation detection method of the spread spectrum communication system.

[0007]

In order to achieve the above object, a spread spectrum communication type correlation detection apparatus according to a first aspect of the present invention performs despreading by filtering a spread spectrum received signal of a predetermined bit with a matched filter. In a correlation detection device of a spread spectrum communication system for obtaining a correlation output with a code sequence, the matched filter, a bit unit filter unit for filtering each bit unit of the spread spectrum received signal, and the bit unit filter unit And a reception quality judging means for judging reception quality based on a demodulated signal of the spread spectrum received signal, and a judgment of the reception quality judging means. When the result shows that the reception quality is good, a correlation peak that is stronger than the current correlation peak is detected. Is characterized in that a filter unit selection operation control means which requires to select a minimum bitwise filter unit operating conditions as possible.

According to a second aspect of the present invention, in the correlation detecting device of the spread spectrum communication system, in the invention according to the first aspect, the bit unit filter section inputs the spread spectrum received signal every time the system clock signal is input. When the despreading code length for shifting the bit unit is N, N-
One shift register, N exclusive OR circuits for calculating an exclusive OR of an input bit, an output bit of each shift register, and an N-bit despread code of a matched filter, and each exclusive OR It is characterized by being configured with an adder that adds the outputs of the circuits.

Further, in the correlation detecting device of the spread spectrum communication system according to claim 3, in the invention according to claim 1 or 2, the reception quality judging means is a demodulated signal of the spread spectrum received signal and an error of the demodulated signal. It has a bit error number counter for counting the number of bit errors with the demodulated signal after correction, and that the reception quality is good when the bit error rate based on the count value of the bit error counter is less than or equal to the bit error rate threshold value. It is characterized in that it is configured to make a determination.

Further, in the correlation detecting device of the spread spectrum communication system according to a fourth aspect, in the invention according to any one of the first to third aspects, the filter section selection operation control means is a system clock signal for the bit unit filter section. It is characterized by having a gate circuit for controlling the supply of. Furthermore, in the correlation detection method of the spread spectrum communication system according to claim 5, the spectrum is obtained by filtering the predetermined M-bit spread spectrum received signal with a matched filter to obtain a correlation detection output with the despread code sequence. In the correlation detection method of the spread spectrum communication method, the spread spectrum received signal is filtered by the matched filter for each bit unit, the output of each filter is added to output the correlation detection value, and the demodulated signal of the spread spectrum received signal is added. A reception quality judging step for judging the reception quality based on the above, and a judgment result of the reception quality judging step, when the reception quality is good, a minimum necessary bit unit capable of detecting a correlation peak stronger than the current correlation peak. And a step of selecting a filter portion to activate it. That.

According to a sixth aspect of the present invention, in the correlation detection method of the spread spectrum communication system, in the invention of the fifth aspect, the reception quality judgment step is performed based on the bit error rate of the demodulated signal of the spread spectrum received signal. It is characterized by judging quality.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, RT is a CDMA receiver, has an A / D converter 1 for converting a spread spectrum code sequence received by a radio receiving unit (not shown) into a digital signal, and is output from this A / D converter 1. Is supplied to the low-pass filter 2 to remove high frequency components such as image frequency components, and then supplied to the correlator 3. The correlator 3 converts the replica spread code from the replica spread code generator described later. The spread modulation signal is despread by using it and supplied to the demodulation processing circuit 4 for demodulation. The output signal of the demodulation processing circuit 4 is supplied to the error correction circuit 5 for error correction and output as a demodulation data signal. It

On the other hand, the output signal of the low-pass filter 2 is supplied to the matched filter 6 which obtains the correlation output with the despread code, and the correlation output outputted from this matched filter 6 is supplied to the correlation peak detection circuit 7 to obtain the correlation peak. The value is detected. The correlation peak value detected by the correlation peak detection circuit 7 is supplied to the synchronization tracking circuit 8 to which the despread signal output from the correlator 3 is supplied, and based on the correlation peak value input by the synchronization tracking circuit 8. A control signal for controlling the generation timing of the replica spread code is output to the replica spread code generator 9, and the replica spread code generated by the replica spread code generator 9 is supplied to the correlator 3.

In the matched filter 6, the M-bit digital spread spectrum code sequence x _{t, 0 to} x _{t, M-1} output from the low pass filter 2 is sequentially input bit by bit from the lower bits individually. The bit unit filter units MF _{0 to} MF _M-1 and the adder A that adds the correlation outputs output from the bit unit filter units MF _{0 to} MF _M-1 . Bit unit filter section MF ₀
2 to MF _M-1 , each of the matched filter despreading codes is p _i (i = 0 to N−1), as shown in FIG.
The system clock signal CK has N-1 shift registers SR ₁ to SR _N-1 connected in series with the input,
The digital spread spectrum code sequence x _{t, j} (j = 0 to M−1) is input to the first-stage shift register SR ₁ .

Further, the bit unit filter sections MF _{0 to} M
F _M-1, the digital spread spectrum code sequence x _{t inputted, j} despreading code p ₀ exclusive OR of computing the exclusive OR circuit EO ₀ and the shift registers SR ₁ ~
An exclusive OR circuit EO ₁ ~EO _M-1 for calculating an exclusive OR of the output reverse spread code p ₁ ~p _M-1 of the SR _N-1,
And an adder AD _OM for adding the exclusive OR outputs of the exclusive OR circuits EO _{0 to} EO _M-1 .

Further, the adder AD is provided for each bit unit fill.
Part MF₀~ MF_M-2Adder AD _OPhase output from
Function output weighting factor 2⁰~ 2^M-2Multiplier M for multiplying by
U₀~ MU_M-2And the bit unit filter section MF_M-1Addition of
Calculator AD_O-2 in the correlation output output from^M-1Multiply by
Multiplier MU_M-1And each multiplier MU₀~ MU_M-1Multiplication of
Adder AD that adds outputs_OAIt consists of and.

Here, the matched filter 6 is set as described above.
The reason for configuring the above is that the matched filter 6 is used as described above.
Despread code of p_iAnd Here, the despreading code p_iof
Possible values are "0" or "-1" corresponding to "+1"
Corresponding "1". Match doff at a certain timing t
The received signal input to the filter 6 is x_tAnd this x_tIs
It is assumed that the bit width M is two's complement representation. Received signal x_t
Each bit of x _{t, k}When expressed by (k = 0 to M-1), reception
Signal x_tCan be expressed by the following equation (1). x_t= X_{t, 0}* 2⁰+ X_{t, 1}* 2¹+ ... + x_{t, M-2}* 2^M-2-X_{t, M-1}* 2^M-1                                                         ………… (1) Therefore, the output Y of the matched filter 6_tIs the following
It is expressed by equation (2).

[0018]

[Equation 1] Here, ^ represents an exclusive OR. By embodying this equation (2), as shown in FIG. 2, each bit x _{t, 0} ~x t of the received signal x _t, may be configured to separate each _M-1.

By configuring the matched filter 6 in this way, it is possible to stop the operation in units of bit unit filter units MF _{0 to} MF _M-1 , and to stop this operation, the bit unit filter unit MF _0. It is only necessary to stop the supply of the system clock signal to ˜MF _M−1 , and it is possible to reduce the power consumption by stopping the calculation of the specific bit of the received signal x _t .

The bit unit filter sections MF _{0 to} MF
_In order to control the operation of _M-1 , as shown in FIG. 1, a filter section selection operation control circuit 11 as a filter section selection operation control means is provided. The filter section selection operation control circuit 11 compares each bit of the demodulated data before and after the error correction circuit 5 with the demodulated data after the error correction before and after the error correction circuit 5 to calculate the bit error number, and to calculate the bit error number. The bit error number counter 12 for counting, and the bit error rate BER based on the count value of the bit error number counter 12
And a reception quality determination circuit 13 for determining whether the reception quality is good or bad depending on whether the calculated bit error rate BER is equal to or more than a preset bit error rate threshold value, and the reception quality The determination result of the determination circuit 13 is input, and when the reception quality is poor based on the reception quality determination result and when the synchronization acquisition is started, all the bit unit filter units MF _{0 to} MF _M-1 are in the operating state, and the reception quality is When it is good, the minimum necessary bit unit filter units MFk _{+ 1 to} MF on the higher-order bit side that can detect a correlation peak value higher than the current correlation peak value based on empirical rules, experimental values, etc.
Operation control signal C for maintaining the operation state of _M-1 and stopping the operation of the other bit unit filter units MF _{0 to} MF _k
A search control circuit 14 that outputs S _{0 to} CS _M-1 and an operation control signal CS ₀ that is output from this search control circuit 14.
~ CS _M-1 is input to each bit unit filter MF _{0 to} M
AND gates AND _{0 to} AND _M-1 for controlling passage of the shift clock signal CK supplied to F _M-1 .

Here, the bit unit filter sections MF _{0 to} MF _K , which stop the operation when the search control circuit 14 has a good reception quality, are set in advance based on an empirical rule or are simulated. Desired bit error rate B
The correlation output of the matched filter 6 required to obtain the ER is determined, and based on this, the deletion bit unit that can maintain the reception quality is determined.

Next, the operation of the above embodiment will be described.
Now, when the spread spectrum code sequence is received by the radio receiving section of the CDMA receiver RT, this spectrum dispersal code sequence is converted into a digital signal by the A / D converter 1, and the high frequency component is converted from this digital signal by the low pass filter 2. For each bit of the digital spread spectrum code sequence, and the bit unit filter unit MF of the matched filter 6 is removed.
_{0 to} MF _M-1 .

At this time, since the reception of the spread spectrum code sequence is started and the synchronization acquisition is started, the search control circuit 14 of the filter section selection operation control circuit 11 selects all AND gates AND _{0 to} AND _M-1. operation control signal with respect to for example a logic value "1" and outputs the CS ₀ ~CS _M-1. Therefore, the AND gates AND _{0 to} AND _M-1 are opened and the system clock signal CK is supplied to all the bit unit filter units MF _{0 to} MF _M-1 , and these bit unit filter units MF _{0 to} MF _{M-. 1} is activated.

Then, each bit unit filter section MF₀~
MF_M-1Shift register SR₁Sequentially received signal x
_{t + 0,0}~ X_{t + 0, M-1}, And then sequentially receive the received signal x
_{t + 1,0}~ X _{t + 1, M-1}...... x_{t + N-1,0}~ X_{t + N-1, M-1}Received
By receiving the shift register SR at the final stage_N-1so
First received signal x_{t + 0,0}~ X_{t + 0, M-1}The state of remembering
Then, each bit unit filter unit MF₀~ MF_M-1Addition of
Calculator AD_OMSupply the correlation signal output from the adder AD
By doing so, the calculation of the equation (2) is performed, and the correlation
Output Y_tIs output, and then the received signal x_{t + N, 0}~ X
_{t + N, M-1}, X_{t + N + 1,0}~ X _{t + N + 1, M-1}…… Every time you receive
Sequential correlation output Y_{t + 1}, Y_{t + 2}... is output.

The correlation outputs Y _t , Y _{t + 1} , Y _{t + 2,} ... Output from the matched filter 6 are as shown in FIG. The peak value is detected. Ideally, only one peak should appear in the correlation output between the received signal and the despread code sequence, but in reality, the signal transmitted from the transmission side should be a building wave other than the direct wave that reaches the antenna. There is a reflected wave that arrives after being reflected by the ground or the like, and a signal that has passed through a large number of propagation paths (multipath) reaches the receiving antenna. Since these received signals are received with the propagation delay time corresponding to each propagation path, a plurality of correlation peaks appear as shown in FIG. In FIG. 3, CO1 represents a correlation peak due to a direct wave,
CO2 and CO3 represent the peaks of the correlation due to the first and second delayed waves, respectively.

Then, the correlation peak value detected by the correlation peak detection circuit 7 is supplied to the synchronization tracking circuit 8, so that the synchronization tracking circuit 8 controls the generation timing of the replica spreading code based on the correlation peak value. To the replica spreading code generator 9, and the replica spreading code generated by this replica spreading code generator 9 is output to the correlator 3
Is supplied to. Therefore, the correlator 3 despreads the digital spread spectrum received signal output from the low-pass filter 2 using the replica spreading code, and supplies the despread signal to the demodulation processing circuit 4. The demodulation process is performed, the demodulated data is supplied to the error correction circuit 5, and the error correction circuit 5 corrects the code error and outputs it as a normal demodulated data signal.

At this time, the demodulated data signal before and after the error correction circuit 5 before and after the error correction and the demodulated data signal for each error correction are supplied to the bit error number counter, and both are compared to determine the bit error number. By counting and supplying this bit error number to the reception quality judgment circuit 13, the reception quality judgment circuit 13 calculates the bit error rate BER based on the bit error number, and the calculated bit error rate BER is preset. Bit error rate threshold BER _TH
When R ≦ BER _TH , for example, a reception quality signal QS having a logical value “1” indicating that the reception quality is good is set to BER.
When> BER _TH , the reception quality signal QS of, for example, a logical value "0" indicating that the reception quality is poor is output to the search control circuit 14, respectively.

Therefore, in the search control circuit 14, when the reception quality signal QS input from the reception quality judgment circuit 13 has the logical value "1", the reception quality is good, and therefore, it is larger than the current correlation peak value. Since only the correlation peak needs to be detected by the matched filter 6, for example, only the upper bit side of the digital spread spectrum received code sequence x _{t, 0 to} x _{t, M-1} output from the preset low-pass filter 2 Control signals CS _{0 to} CS _k having a logical value “0” are output to the lower bit side and control signals CS _{k + 1 to} CS having a logical value “1” are output to the upper bit side. Output _{M- 1} .

Therefore, the AND gates AND _{0 to} AND _k corresponding to the lower bits have the system clock signal CK.
Of the system clock signal CK in the AND gates AND _{k + 1 to} AND _M-1 corresponding to the upper bits.
Since the system clock signal CK is not input to the bit unit filter units MF _{0 to} MF _k corresponding to the lower bits in the matched filter 6, these operations are stopped and the bit unit filter units corresponding to the upper bits are supplied. The filter processing is performed only in MF _{k + 1 to} MF _M-1 , and the low power consumption mode is set in which only the correlation peak value larger than the current state is searched in the state where the reception quality is good.

Therefore, for example, by performing radio communication with a radio base station closer to the present radio base station, the correlation output output from the matched filter 6 becomes the correlation peak detection circuit 7.
When a correlation peak value larger than the current correlation peak value is detected, the correlation peak value is updated to the synchronization tracking circuit 8 and the replica spreading code generated by the replica spreading code generator 9 is supplied to the synchronization spreading circuit 8. Occurrence timing is changed, despreading processing is performed in correlator 3 using this changed replica spreading code, and reception quality is improved.

When the radio transmission environment deteriorates from the state where the reception quality is good and the number of error codes code-corrected by the error correction circuit 5 increases, the bit error number counter 12
When the bit error rate BER calculated by the reception quality determination circuit 13 increases and exceeds the bit error rate threshold BER _TH , the received product determination circuit 13 outputs a logical value "0". The reception quality signal QS of is output to the search control circuit 14.

Therefore, in the search control circuit 14, the reception quality signal QS has the logical value "0", which indicates that the reception quality is poor. Controls _{0 to} CSM _-1 to a logical value "1". Therefore, all AND gates AND _{0 to} AND
_{The M-1} is opened, the system clock signal CK is supplied to all the bit unit filter units MF _{0 to} MF _M-1 of the matched filter 6, the low power consumption mode is released, and the low-pass filter 2 outputs the signal. Of the spread spectrum received code sequence x _{t, 0 to} x _{t, M-1} is restored to the state where the correlation output can be obtained, and the correlation peak detection circuit 7
At, a new correlation peak value is detected. In accordance with this, synchronization tracking is performed, the generation timing of the replica spreading code is controlled according to the correlation peak value, and the correlator 3 performs despreading processing based on the replica spreading code, and the demodulation processing circuit 4 The number of error codes corrected by the error correction circuit 5 is reduced by performing the demodulation processing in.

As described above, according to the above embodiment, when the reception quality is good, the correlation peak value larger than the current correlation peak value of the spread spectrum reception code sequence x _{t, 0 to} x _{t, M-1.} Only the high-order bit side bit unit filter units MF _{k + 1 to} MF _M-1 are activated, and the remaining low-order bit side bit unit filter units MF _{0 to} MF.
_Since a low power consumption mode in which _k is in an operation stop state is set and this state is continued while maintaining a good reception quality, the power consumption of the matched filter 6 can be reduced to a necessary minimum. Power consumption can be reduced significantly compared to the example.

Moreover, the reception quality is determined by despreading the spread spectrum received code sequence by the correlator 3 and then by the demodulation processing circuit 4.
The bit error rate BER calculated based on the demodulated data signal before the error correction and the demodulated data signal after the error correction circuit 5 performs the error correction is compared with a preset bit error rate threshold BER _TH. Since it is performed by doing so, it is possible to accurately determine the reception quality.

In the above embodiment, the bit unit filter sections MF _{0 to} MF for filtering the spread spectrum received code sequence x _{t, 0 to} x _{t, M-1} output from the low-pass filter 2 in 1-bit units. _The case where the matched filter 6 is configured by _M-1 and the adder AD has been described, but the present invention is not limited to this, and the spread spectrum reception code sequence x _{t, 0 to} x _{t, M-1} in multiple bit units. It is also possible to provide a bit-by-bit filter unit for performing the filter processing by and add these outputs by an adder.

In the above embodiment, the case where the reception quality is determined based on the bit error rate BER has been described, but the present invention is not limited to this, and the correlation peak value output from the correlator is used. Then, it may be determined whether the reception quality is good or bad by determining whether or not this is a predetermined threshold value or more.
Similarly, R indicating the received signal strength detected by the wireless reception unit
The quality of the reception quality may be determined by using an SSI (Receiver Signal Strength Indicator) signal and determining whether or not this is a predetermined threshold or more.

[0037]

As described above, according to the invention of claim 1 or 5, the spread spectrum received signal is filtered by the matched filter in a unit of a predetermined bit, and the output of each filter is added to obtain the correlation detection value. The minimum required bit unit filter unit that can output a signal and judge the reception quality based on the spread spectrum received signal, and when the result of this judgment is that the reception quality is good, a correlation peak stronger than the current correlation peak can be detected. Is selected as the operating state, and this state is maintained while maintaining a good reception quality, so that the power consumption of the matched filter with large power consumption in the spread spectrum communication device can be reduced to the necessary minimum.
The effect that the power consumption can be significantly reduced as compared with the conventional example is obtained. In addition, by configuring the matched filter with a bit-by-bit filter unit for each 1-bit unit of the spread spectrum received signal, it is possible to finely set the operating state and the operating stop state.

According to the second aspect of the present invention, when the bit unit filter section sets the despread code length for shifting the input bit unit of the spread spectrum received signal each time the system clock signal is input, the despread code length is N. N-1 shift registers, N exclusive OR circuits for calculating the exclusive OR of the input bits, the output bits of each shift register, and the N-bit despreading code of the matched filter, and each exclusive OR circuit. Since it is composed of an adder that adds the output of the logical sum circuit, it is possible to set the operation state and the operation stop state for each bit unit filter unit depending on whether or not the system clock signal is supplied to the shift register. The effect that it can be obtained.

Further, according to the invention of claim 3 or 6, the reception quality judgment means receives the demodulated signal of the spread spectrum received signal and the demodulated signal after error correction of the demodulated signal based on the bit error rate. Since the quality is determined, it is possible to obtain the effect that the reception quality can be accurately determined. Still further, according to the invention of claim 4, the filter section selection operation control means has a gate circuit for controlling the supply of the system clock signal to the bit unit filter section. The effect that the state can be easily selected is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of the matched filter of FIG.

FIG. 3 is a graph showing an example of correlation output of a matched filter.

[Explanation of symbols]

RT CDMA receiver 1 A / D converter 3 Correlator 4 Demodulation processing circuit 5 Error correction circuit 6 Matched filter MF _{0 to} MF _M-1 bit unit filter unit AD adder SR _{1 to} SRN _-1 shift register EO ₀ ~ EO _M-1 exclusive OR circuit AD _OM adder MU _{0 to} MU _{M-1 multiplier} AD _OA adder 7 correlation peak detection circuit 8 synchronization tracking circuit 9 replica spread code generator 11 filter section selection operation control circuit 12 bits Error number counter 13 Reception quality judgment circuit 14 Search control circuit AND _{0 to} AND _M-1 AND gate

Claims (6)

[Claims] 1. A spread spectrum communication type correlation detection device, wherein a spread spectrum received signal of a predetermined bit is filtered by a matched filter to obtain a correlation output with a despread code sequence, wherein the matched filter is a spectrum filter. The spread spectrum received signal is configured to include a bit unit filter unit for filtering in a predetermined bit unit and an adder for adding a filter output of the bit unit filter unit to output a correlation peak detection value. A reception quality judging means for judging the reception quality based on the received quality judging means, and a minimum necessary bit unit filter capable of detecting a correlation peak stronger than the current correlation peak when the judgment result of the reception quality judging means shows that the reception quality is good. And a filter section selection operation control means for selecting a section to be in an operating state. A spread spectrum communication type correlation detector. 2. The bit unit filter section, when the despread code length for shifting the input bit unit of the spread spectrum received signal is N each time a system clock signal is input, is N−1 shift registers, N exclusive OR circuits that calculate the exclusive OR of the input bits and the output bits of each shift register and the N-bit despreading code of the matched filter, and the addition that adds the outputs of the exclusive OR circuits. 2. The container according to claim 1, wherein
A spread spectrum communication type correlation detector described. 3. The reception quality judging means has a bit error number counter for counting the number of bit errors between the demodulated signal of the spread spectrum received signal and the demodulated signal after error correction of the demodulated signal, and the bit error counter. 3. The spread spectrum communication system according to claim 1, wherein the reception quality is determined to be good when the bit error rate based on the count value of is less than or equal to the bit error rate threshold value. Correlation detector. 4. The spread spectrum communication according to claim 1, wherein the filter section selection operation control means has a gate circuit for controlling supply of a system clock signal to the bit unit filter section. Method correlation detector. 5. A spread spectrum reception signal in a correlation detection method of a spread spectrum communication system, wherein a predetermined M bit spread spectrum received signal is filtered by a matched filter to obtain a correlation detection output with a despread code sequence. Is processed in a predetermined bit unit by a matched filter, the output of each filter is added to output a correlation detection value, a reception quality determination step of determining reception quality based on the spread spectrum received signal, and the reception quality When the determination result of the determination step is that the reception quality is good, a step of selecting a minimum necessary bit unit filter unit capable of detecting a correlation peak stronger than the current correlation peak and setting it in an operating state is provided. A spread spectrum communication method for detecting correlation. 6. The correlation detection method according to claim 5, wherein the reception quality determination step determines the reception quality based on the bit error rate of the demodulated signal of the spread spectrum received signal.