JP2003283368A - Clock accuracy compensating circuit for cdm demodulator, compensating method, and cdm demodulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To compensate the clock accuracy when an instantaneous break occurs for a few seconds even if a clock generator exhibiting a relatively low accuracy is used for back diffusion process of a CDM demodulator. <P>SOLUTION: When signals are received, switches 18 and 19 are connected to '1' and the result of detection by a clock lag detector 17 is supplied to a clock generator 15 as timing compensation signals and the clock timing is adjusted by the result of propagation analysis (including clock compensation) of the received signals. In the meantime, the clock compensation value except the received signals subjected to the propagation analysis is extracted by a clock compensation value extracting circuit 24. When a break of signal is detected, the switches 18 and 19 are connected to '2' and clock compensation is performed by the output (the clock compensation value at the time of the signal reception) of the clock compensation value extracting circuit 24 as long as the break of signal continues. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a CDM transmission system.
The present invention relates to a circuit technology for compensating for the clock accuracy of a CDM demodulator in the event of an instantaneous interruption in a receiving terminal device used in a mobile communication or broadcasting system adopting a (Code Division Multiple) system.

[0002]

2. Description of the Related Art Conventionally, in a mobile communication or broadcasting system, a CDM method using a spread spectrum technique has been used as one of transmission methods. In the receiving terminal device used in this type of system, the clock (chip rate) used for despreading in the CDM demodulator
Must exactly match that of the sender. When an error occurs in the clock, it appears as a decrease in the level of the CDM demodulated signal.

Normally, when a signal is received, the clock timing is corrected by using a cross correlator or the like so that it is strictly synchronized with the clock on the transmission side. However, when the signal is interrupted, the clock timing is not corrected because there is no information to be synchronized. Therefore,
If the clock is not a highly accurate clock with an error of a few ppm, 1
Even if the signal is interrupted for about a second, clock synchronization will be lost.

On the other hand, in the case of mobile reception, an interleaving method is usually used so that the original signal can be restored by error correction even in the case of instantaneous interruption. However, even if this method is used, if the clock synchronization deviates by a certain amount or more, normal data decoding can no longer be performed.

From the above, it is desirable to use a highly accurate clock with an error of about several ppm for the despreading process of the CDM demodulator, but a clock generator that generates such a highly accurate clock is extremely expensive. However, it is not used in the receiving terminal device which requires cost saving, but the fact is that it is dealt with by a clock generator having an accuracy of about several tens of ppm which is generally popular.

[0006]

As described above, in the conventional CDM demodulator, although it is desirable to use a highly accurate clock generator for the clock used for despreading, it is difficult to adopt it in terms of cost. Therefore, the reality is that an inexpensive clock generator must be used.

The present invention has been made in consideration of the above circumstances. In the despreading process of the CDM demodulator, even a clock with an accuracy of about tens of ppm generated by an inexpensive clock generator is interrupted for a few seconds. An object of the present invention is to provide a clock accuracy compensating circuit for a CDM demodulator capable of compensating for clock synchronization accuracy at the time, a compensating method therefor and a CDM demodulator.

[0008]

To achieve the above object, a clock accuracy compensating circuit of a CDM demodulator according to the present invention is for despreading a baseband signal of a CDM (code division multiplex) system by spread spectrum. A clock generator that generates a clock used as a timing signal, and despreads the baseband signal obtained from the received CDM signal at a timing based on the clock generated by the clock generator, and receives from this despreading. A path detecting means for obtaining transmission line response values of a plurality of paths, a clock deviation detecting means for obtaining a clock deviation from a detection result of the path detecting means, and the clock based on the detection result of the clock deviation detecting means. Control means for controlling the clock generation timing of the generator, and the path detected by the path detection means A clock correction value extraction means for use in a CDM demodulator provided with a decoding means for synthesizing and decoding a despread output and for extracting and storing a clock correction value for correcting a clock error from the detection result of the clock shift detection means; The reception signal detecting means for detecting the presence or absence of the reception of the CDM signal, and the clock generation timing of the clock generator based on the detection result of the clock deviation detecting means during the period in which the reception signal is detected by the reception signal detecting means. The clock generation timing of the clock generator is corrected by the clock correction value stored in the clock correction value extraction means instead of the output of the clock deviation detection means during the period when the reception signal is not detected by the reception signal detection means. It is characterized by comprising a switching means for correcting.

Further, the clock accuracy compensating method for a CDM demodulator according to the present invention is a clock generation for generating a clock used as a timing signal for despreading a baseband signal of a CDM (code division multiplexing) system by spread spectrum. And despreading the baseband signal obtained from the received CDM signal at the timing based on the clock generated by the clock generator, and the transmission line response values of a plurality of paths suitable for reception from this despreading. , A clock deviation detecting means for obtaining a clock deviation from the detection result of the path detecting means, and a control means for controlling the clock generation timing of the clock generator based on the detection result of the clock deviation detecting means. When,
A clock correction value for correcting a clock error is extracted from a detection result of the clock shift detection means, which is used in a CDM demodulator provided with a decoding means for synthesizing and decoding the despread output of the path detected by the path detection means. The clock correction value extraction step of storing and storing, the received signal detection step of detecting the presence or absence of reception of the CDM signal, and the detection result of the clock deviation detection step during the period in which the received signal is detected in the received signal detection step. The clock generation timing of the clock generator is corrected based on the clock correction value stored in the clock correction value extraction step instead of the output of the clock deviation detection step during the period when the reception signal is not detected in the reception signal detection step. And a switching process for correcting the clock generation timing of the clock generator. .

The CDM demodulator according to the present invention receives a clock generator for generating a clock used as a timing signal for despreading a CDM (code division multiplexing) baseband signal by spread spectrum. Path detection means for despreading the baseband signal obtained from the CDM signal at a timing based on a clock generated by the clock generator, and obtaining transmission line response values of a plurality of paths suitable for reception from the despreading. A clock deviation detecting means for obtaining a clock deviation from the detection result of the path detecting means; a control means for controlling the clock generation timing of the clock generator based on the detection result of the clock deviation detecting means; Decoding means for synthesizing and decoding the despread outputs of the paths detected by the means, and the clock Clock correction value extracting means for extracting and storing a clock correction value for correcting a clock error from the detection result of the detection means, reception signal detecting means for detecting the presence or absence of reception of the CDM signal, and reception signal detecting means for receiving During the period when the signal is detected, the clock generation timing of the clock generator is corrected based on the detection result of the clock shift detection means, and during the period when the received signal is not detected by the received signal detection means, the clock shift detection means And a switching unit for correcting the clock generation timing of the clock generator with the clock correction value stored in the clock correction value extraction unit instead of the output.

The present invention utilizes the characteristic that the accuracy of the clock hardly changes in a short time such as several seconds and several minutes. When the signal is received, the clock correction value is extracted and held, and when the signal is cut off, the held clock correction value is used to perform the clock correction. Here, since clock correction (timing change) due to a change in signal propagation is included in addition to clock correction at the time of signal reception, a clock correction value extraction circuit for extracting only a clock correction value due to a clock error by some method is required. As an example, there is a circuit configuration or software configuration for averaging clock deviation detection results for clock timing control during path detection to obtain a clock correction value.However, clock movement due to signal propagation change is random, and propagation delay When the frequency of change is not so high, it is possible to extract only the clock error by using a low-pass filter with a sufficiently long time constant.

[0012]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a CDM type receiving terminal device to which the present invention is applied. In FIG. 1, the radio signal of the CDM communication system by the spread spectrum received by the receiving antenna 11 is channel-detected by the tuner 12 and converted into a baseband CDM signal. The baseband CDM signal is converted into a digital signal by an analog / digital converter (A / D) 13 and then supplied to a matched filter (MF) 14.

The matched filter 14 performs a path search based on the clock generated by the chip rate clock generator 15, and obtains the propagation delay characteristic and the despreading timing of the received digital signal from the spreading code and the cross correlation. . The output of the matched filter 14 is supplied to the maximum value detector 16. This maximum value detector 16 detects the timing of the maximum path that is the main wave from the output of the matched filter 14, and the detection result of this maximum value detector 16 is supplied to the clock shift detector 17, where A clock shift per unit time is detected. The detection result of the clock shift detector 17 is supplied as a timing correction value to the clock generator 15 via the first and second switches (selecting “1” side in the steady state) 18 and 19 to correct the clock shift. Is subjected to a timing correction process including.

The baseband CDM signal output from the analog / digital converter 13 is a RAKE combiner 20.
Is supplied to. This RAKE combiner 20 is an input CDM
The clock generator 15 extracts several paths from the signal.
With the clock generated in step 1 as the despreading timing, despreading is performed for each path using the spreading code and combined output is performed. The output of the RAKE combiner 20 is subjected to error correction processing including deinterleaving and Viterbi decoding in an error correction processing circuit 21, and the decoder 22 decodes and outputs transmission data.

On the other hand, the reception state of the tuner 12 is monitored by the no-signal detector 23. If there is a momentary interruption in the received signal, the no-signal detector 23 detects this and the interruption state is eliminated. The first and second switches 18 and 19 are both connected to the "2" side until the above. At this time, the first switch 1
Since the “2” side of 8 is open, the output of the clock shift detector 17 is not supplied to the clock generator 15, and the clock correction value extraction circuit 24 connected to the “2” side of the second switch 19 Is supplied to the clock generator 15.

The clock correction value extraction circuit 24 includes a feedback loop including an adder 241, a delay device (delay amount Z ^-1 corresponds to a clock deviation detection period) 242, and a multiplier (coefficient γ) 243 and a multiplier ( Coefficient 1−γ) 244. That is, in the state where the first switch 18 is connected to the “1” side, the output of the clock shift detector 17 is fetched and sequentially added with the previous adder 241 to average the clock correction. When the value is extracted and the first and second switches 18 and 19 are connected to the "2" side,
The clock correction signal generated and held by the feedback loop is output from the multiplier 243 and supplied to the clock generator 15 via the second switch 19.

Here, the analog / digital converter 1 is used.
The output of 3 and later constitutes a CDM demodulator, and particularly the matched filter 14, the clock generator 15, the maximum value detector 16,
The clock shift detector 17 constitutes the above-mentioned cross-correlator.

In the above structure, the operation of the characteristic part of the present invention will be described below.

First, while the signal is being received, the switches 18 and 19 are connected to "1", the detection result of the clock shift detector 17 is supplied to the clock generator 15 as a timing correction signal, and the received signal The timing of the clock is adjusted according to the result of the propagation analysis (including the clock correction). In the meantime, the clock correction value extraction circuit 24 extracts the clock correction value excluding the propagation analysis of the received signal.

When the signal loss is detected by the no-signal detector 23, the switches 18 and 19 are connected to "2",
As long as the signal disconnection state continues, clock correction is performed by the output of the clock correction value extraction circuit 24 (clock correction value at the time of signal reception). This utilizes the characteristic that the accuracy of the clock hardly changes in a short time such as a few seconds and a few minutes.

At the time of signal reception, in addition to clock correction, clock correction (timing change) due to changes in signal propagation is also included. Therefore, in the present embodiment, the clock correction value extraction circuit 24 that extracts only the clock correction value due to the clock error is used.

In the above embodiment, the case where the clock correction value extraction circuit 24 has a hardware configuration has been described.
It can also be realized by software. FIG. 2 shows an example of implementation with a software configuration.

In FIG. 2, clock fluctuations are extracted at the start of activation (step S1). The extracted clock fluctuation value is ClkMove. In this state, the no-signal detector 2
From the detection result of No. 3, it is determined whether a signal is currently being received (step S2). If it is being received, the moving average value Ave ClkMove of the clock fluctuation is calculated and stored (step S
3). The moving average value Ave ClkMove is expressed by the following equation. Ave ClkMove = γ · Ave ClkMove + Clkmove The coefficient γ is, for example, 0.9999.

In parallel with the processing of step S3, the clock fluctuation detection value ClkMove is assigned to the clock correction value ClkComp (step S4), and the clock is set to the clock correction value ClkC.
Correction based on omp (step S5), step S1
Return to processing.

On the other hand, when the signal reception is not detected in step S2, the moving average value Ave ClkMove of the clock fluctuation stored in the clock correction value ClkComp is substituted (step S6), and the clock is calculated in step S5. Clock correction is performed based on the correction value ClkComp.

By the above processing, the processing equivalent to the clock correction value extraction circuit 24 having the hardware configuration shown in FIG. 1 can be realized by software.

The effects of the above embodiment will be described below with reference to specific examples. CDM wireless signal transmission rate 25
Taking the case of 6 kbps as an example, when the signal is interrupted and the synchronization shifts to 3.9 μsec or more due to a clock error, the signal cannot be demodulated normally. Here, when the transmission side performs interleaving for 3 seconds, the signal instantaneous interruption resistance is about 1 second. Therefore, at least the synchronization deviation for 1 second must be 3.9 μsec or less. The clock accuracy required when the clock correction is not performed is calculated as 1 (second) × 3.9 (μsec) = 3.9 (ppm). A crystal oscillator of this precision is expensive as mentioned above.

On the other hand, when clock correction is performed, the accuracy of the crystal oscillator is the maximum detection value of the clock deviation of the device or a value determined by the maximum correction value, and the clock correction accuracy is the detection resolution and correction of the clock deviation. Determined by resolution. The specifications of the tested device are: -Maximum detection accuracy of clock shift, maximum correction value 60pp
m ・ Clock deviation detection resolution and correction resolution are 2 ppm. Therefore, even if a general crystal oscillator of 60 ppm is used, it is possible to correct the error to 2 ppm. When the clock correction is realized by software, there is no negative factor in implementing this function, so there is almost no increase in parts and the like, and it is extremely effective in terms of cost.

The present invention is not limited to the above embodiment. For example, when the clock movement due to the signal propagation change is random and the frequency of the propagation delay change is not so frequent, the clock correction value extraction circuit 24 is configured to use a low-pass filter with a sufficiently long time constant. Only the error can be extracted.

Although there are various methods for detecting a signal loss, it is necessary to consider that in a multipath environment of a mobile body, it is not possible to make a judgment only by the received power. In this case, for example, when a UW (unique word) for synchronization is added to the transmission signal, the signal break can be detected by referring to the UW detection rate.

[0032]

As described above, according to the present invention, in the despreading process of the CDM demodulator, even if the clock generated by an inexpensive clock generator has an accuracy of about several tens of ppm, the accuracy of the clock can be improved even if the power is interrupted for a few seconds. CD that can compensate for
A clock accuracy compensation circuit for an M demodulator and its compensation method can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of a CDM receiver as an embodiment of a clock accuracy compensation circuit of a CDM demodulator according to the present invention.

FIG. 2 is a flowchart showing a flow of processing when the clock correction value extraction circuit used in the embodiment of FIG. 1 is realized by a software configuration.

[Explanation of symbols]

11 ... Receiving antenna 12 ... Tuner 13 ... Analog / digital converter (A / D) 14 ... Matched filter (MF) 15 ... Chip rate clock generator 16 ... Maximum value detector 17 ... Clock deviation detector 18 ... First switch Reference numeral 19 ... Second switch 20 ... RAKE combiner 21 ... Error correction processing circuit 22 ... Decoder 23 ... No signal detector 24 ... Clock correction value extraction circuit 241 ... Adder 242 ... Delay device (delay amount Z ⁻¹ ) 243 ... Multiplier (coefficient γ) 244 ... Multiplier (coefficient 1-γ)

Claims (6)

[Claims] 1. A clock generator for generating a clock used as a timing signal for despreading a baseband signal of a CDM (code division multiplexing) system by spread spectrum, and the baseband obtained from a received CDM signal. Path detection means for despreading a signal at a timing based on a clock generated by the clock generator and obtaining transmission path response values of a plurality of paths suitable for reception from the despreading, and a detection result of the path detection means Clock deviation detecting means for obtaining a clock deviation from the clock, control means for controlling the clock generation timing of the clock generator based on the detection result of the clock deviation detecting means, and despreading of the path detected by the path detecting means. Used for a CDM demodulator having a decoding means for synthesizing outputs and decoding Clock correction value extracting means for extracting and storing a clock correction value for correcting a clock error from the detection result of the detection means, reception signal detecting means for detecting the presence or absence of reception of the CDM signal, and reception signal detecting means for receiving During the period when the signal is detected, the clock generation timing of the clock generator is corrected based on the detection result of the clock shift detection means, and during the period when the received signal is not detected by the received signal detection means, the clock shift detection means A clock accuracy compensating circuit for a CDM demodulator, comprising switching means for correcting the clock generation timing of the clock generator with the clock correction value stored in the clock correction value extracting means instead of the output. 2. The clock correction value extraction means generates a clock correction value by sequentially taking in and averaging the detection results of the clock shift detection means during the detection period of the received signal. A clock accuracy compensation circuit of the CDM demodulator according to Item 1. 3. The CDM according to claim 1, wherein the clock correction value extracting means is composed of a low-pass filter having a time constant longer than a fluctuation period of the clock.
Clock accuracy compensation circuit for demodulator. 4. The reception signal detecting means, when a pattern signal for synchronization is added to the CDM signal,
2. The clock accuracy compensating circuit for a CDM demodulator according to claim 1, wherein the pattern signal is detected from the received signal, and the presence or absence of reception is judged based on the detection rate. 5. A clock generator for generating a clock used as a timing signal for despreading a baseband signal of a CDM (code division multiplexing) system by spread spectrum, and the baseband obtained from a received CDM signal. Path detection means for despreading a signal at a timing based on a clock generated by the clock generator and obtaining transmission path response values of a plurality of paths suitable for reception from the despreading, and a detection result of the path detection means Clock deviation detecting means for obtaining a clock deviation from the clock, control means for controlling the clock generation timing of the clock generator based on the detection result of the clock deviation detecting means, and despreading of the path detected by the path detecting means. Used for a CDM demodulator having a decoding means for synthesizing outputs and decoding A clock correction value extracting step of extracting and storing a clock correction value for correcting a clock error from a detection result of the detection means, a reception signal detecting step of detecting the presence or absence of reception of the CDM signal, and a reception signal detecting step of receiving During the period when the signal is detected, the clock generation timing of the clock generator is corrected based on the detection result of the clock shift detection process, and during the period when the received signal is not detected in the received signal detection process, the clock shift detection process is performed. And a switching step of correcting the clock generation timing of the clock generator with the clock correction value stored in the clock correction value extraction step instead of the output. 6. A clock generator for generating a clock used as a timing signal for despreading a baseband signal of a CDM (code division multiplexing) system by spread spectrum, and the baseband obtained from a received CDM signal. Path detection means for despreading a signal at a timing based on a clock generated by the clock generator and obtaining transmission path response values of a plurality of paths suitable for reception from the despreading, and a detection result of the path detection means Clock deviation detecting means for obtaining a clock deviation from the clock, control means for controlling the clock generation timing of the clock generator based on the detection result of the clock deviation detecting means, and despreading of the path detected by the path detecting means. The decoding means for synthesizing and decoding the outputs and the detection result of the clock deviation detection means Clock correction value extracting means for extracting and storing a clock correction value for correcting the error, reception signal detecting means for detecting the presence or absence of reception of the CDM signal, and a period during which the reception signal is detected by the reception signal detecting means. Corrects the clock generation timing of the clock generator based on the detection result of the clock shift detecting means, and the clock correction is performed in place of the output of the clock shift detecting means during the period when the received signal is not detected by the received signal detecting means. A CDM demodulator, comprising: switching means for correcting the clock generation timing of the clock generator with the clock correction value stored in the value extracting means.