JP2003282589A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2003282589A
JP2003282589A JP2002086408A JP2002086408A JP2003282589A JP 2003282589 A JP2003282589 A JP 2003282589A JP 2002086408 A JP2002086408 A JP 2002086408A JP 2002086408 A JP2002086408 A JP 2002086408A JP 2003282589 A JP2003282589 A JP 2003282589A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
impurity diffusion
wafer
forming
diffusion regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002086408A
Other languages
Japanese (ja)
Other versions
JP3580293B2 (en
Inventor
Yutaka Fukuda
豊 福田
Mikimasa Suzuki
幹昌 鈴木
Naohiko Hirano
尚彦 平野
Chikage Noritake
千景 則武
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2002086408A priority Critical patent/JP3580293B2/en
Priority to US10/201,556 priority patent/US7145254B2/en
Priority to KR1020020043963A priority patent/KR100659376B1/en
Priority to DE10234155A priority patent/DE10234155B4/en
Priority to CNB02127066XA priority patent/CN1267990C/en
Publication of JP2003282589A publication Critical patent/JP2003282589A/en
Application granted granted Critical
Publication of JP3580293B2 publication Critical patent/JP3580293B2/en
Priority to KR1020060092571A priority patent/KR20060109390A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/732—Location after the connecting process
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a thin semiconductor device on which a back electrode is disposed via an impurity diffusion region for contact for preventing the strength failure of a wafer-shaped substrate, and obtaining the contact of the back electrode at a lower temperature. <P>SOLUTION: An impurity diffusion region for forming an element is formed on one surface of a water-shaped semiconductor substrate 30, and the substrate 30 is formed with a predetermined thickness being ground from the opposite face, and etched to a predetermined depth so as to be made thin excluding the outer periphery. An impurity doped polysilicon film 31 is formed, and an impurity is diffused from the film 31 to the semiconductor substrate 30 side so that the impurity diffusion region for contact can be formed on the surface. The back electrode 32 is formed so as to be brought into contact with the impurity doped polysilicon film 30, and then diced. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置の製造方
法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method.

【０００２】[0002]

【従来の技術】縦型パワーＭＯＳトランジスタの構成の
一例を述べると、ｎ型シリコン基板における一方の面の
表層部にｐ型ベース領域およびｎ型ソース領域が形成さ
れるとともに、ｎ型シリコン基板における他方の面には
ドレイン電極（裏面電極）が形成される。縦型パワーＭ
ＯＳトランジスタにおいて、基板の厚さを薄くすること
により縦方向に形成される電流経路における基板での抵
抗成分を低くしてオン抵抗を低減することができる。こ
れを実現するためには製造工程においてウエハを薄く加
工することになる。詳しい工程は、ウエハ状シリコン基
板の一方の面においてベース・ソース領域と配線材と保
護膜を形成した後、ウエハ状シリコン基板を薄くする加
工を行い、さらに、裏面電極を形成する。この裏面電極
の形成前におけるウエハ状基板は薄くなっており反りや
歪みの発生が危惧される。2. Description of the Related Art An example of the structure of a vertical power MOS transistor will be described. A p-type base region and an n-type source region are formed on the surface layer of one surface of an n-type silicon substrate, and an n-type silicon substrate is formed. A drain electrode (back surface electrode) is formed on the other surface. Vertical power M
In the OS transistor, by reducing the thickness of the substrate, the on-resistance can be reduced by lowering the resistance component in the substrate in the current path formed in the vertical direction. In order to realize this, the wafer is thinly processed in the manufacturing process. More specifically, after forming the base / source regions, the wiring material, and the protective film on one surface of the wafer-shaped silicon substrate, the wafer-shaped silicon substrate is thinned, and the back electrode is further formed. The wafer-shaped substrate before the formation of the back electrode is thin, and there is a concern that warpage or distortion may occur.

【０００３】一方、前述の構成の縦型パワーＭＯＳトラ
ンジスタにおいて、ｎ型シリコン基板の裏面での表層部
にｎ+領域をコンタクト用不純物拡散領域として形成
し、このコンタクト用不純物拡散領域に接するように裏
面電極を形成することが行われている。この構成とすべ
く、製造工程の一例として以下のようにする。ウエハ状
シリコン基板の一方の面においてベース・ソース領域と
配線材と保護膜（ＳｉＮ膜又はＰＩＱ膜）を形成する。
そして、ウエハ状シリコン基板の裏面側においてコンタ
クト確保のためのｎ+領域を形成する。このとき、
（ｉ）イオン打ち込み法、あるいは、（ｉｉ）熱拡散に
よる不純物導入法を、用いる。（ｉ）のイオン打ち込み
法においては、後工程で５００〜７００℃のアニールを
行う必要があるとともに、より高濃度化すべくドーズ量
を多くする必要があり、さらに、打ち込まれたイオンの
活性化率を１００％近くにすべくアニール温度を高くす
る必要がある。一方、（ｉｉ）の熱拡散法においては、
より高い温度と時間が要求される。On the other hand, in the vertical power MOS transistor having the above-described structure, an n + region is formed as a contact impurity diffusion region in the surface layer portion on the back surface of the n type silicon substrate, and is in contact with the contact impurity diffusion region. Backside electrodes are being formed. In order to have this configuration, the following is an example of the manufacturing process. A base / source region, a wiring material, and a protective film (SiN film or PIQ film) are formed on one surface of a wafer-shaped silicon substrate.
Then, an n + region for securing a contact is formed on the back surface side of the wafer-shaped silicon substrate. At this time,
An ion implantation method (i) or an impurity introduction method by thermal diffusion (ii) is used. In the ion implantation method of (i), it is necessary to perform annealing at 500 to 700 ° C. in a later step, and it is necessary to increase the dose amount in order to increase the concentration, and further, the activation rate of the implanted ions. It is necessary to raise the annealing temperature in order to make the value close to 100%. On the other hand, in the thermal diffusion method of (ii),
Higher temperatures and times are required.

【０００４】ここで、ウエハ状シリコン基板の一方の面
においてベース・ソース領域と配線材を形成した後にお
いて、前述の（ｉ）あるいは（ｉｉ）の手法によりコン
タクト用ｎ+領域を形成する場合には、配線材（例えば
アルミ膜）の軟化温度（４５０℃）以下で行う必要があ
る。When the base / source region and the wiring material are formed on one surface of the wafer-shaped silicon substrate and then the contact n + region is formed by the method (i) or (ii) described above. Need to be performed at a softening temperature (450 ° C.) or lower of the wiring material (for example, an aluminum film).

【０００５】[0005]

【発明が解決しようとする課題】本発明はこのような背
景の下になされたものであり、その目的は、薄型で、か
つ、コンタクト用不純物拡散領域を介して裏面電極を配
した半導体装置において、ウエハ状の基板における強度
的な不具合を回避できるとともに、より低温で裏面電極
のコンタクトをとることができる半導体装置の製造方法
を提供することにある。SUMMARY OF THE INVENTION The present invention has been made under such a background, and an object thereof is to provide a semiconductor device which is thin and has a back surface electrode arranged through a contact impurity diffusion region. An object of the present invention is to provide a method for manufacturing a semiconductor device, which can avoid a strength problem in a wafer-shaped substrate and can make contact with a back electrode at a lower temperature.

【０００６】[0006]

【課題を解決するための手段】請求項１，２，３に記載
の半導体装置の製造方法においては、ウエハ状の半導体
基板における一方の面の表層部に素子形成用不純物拡散
領域を形成する工程と、ウエハ状の半導体基板における
素子形成用不純物拡散領域を形成した面とは反対の面か
ら研削加工して当該基板を所定の厚さにする工程と、ウ
エハ状の半導体基板における素子形成用不純物拡散領域
を形成した面とは反対の面に対し同半導体基板の外周部
を残して所定深さまでエッチングして薄膜化する工程
と、ウエハ状の半導体基板における素子形成用不純物拡
散領域を形成した面とは反対の面に不純物ドープトポリ
シリコン膜を形成するとともに、不純物ドープトポリシ
リコン膜から半導体基板側に不純物を拡散させてウエハ
状の半導体基板における素子形成用不純物拡散領域を形
成した面とは反対の面の表層部にコンタクト用不純物拡
散領域を形成する工程と、不純物ドープトポリシリコン
膜に接するように裏面電極を形成する工程を備えてい
る。よって、ウエハ状の半導体基板の外周部に厚肉部を
残したままその内方の領域を薄膜化でき、反りや歪みの
心配のない状態で裏面に電極を形成することができる。
また、不純物ドープトポリシリコン膜からの不純物の拡
散、つまり、コンタクト用不純物拡散領域の形成は低温
で行うことができ、このコンタクト用不純物拡散領域を
介して裏面電極と低抵抗なるオーミックコンタクト接続
することが可能となる。その結果、ウエハ状の基板にお
ける強度的な不具合を回避できるとともに、より低温で
裏面電極のコンタクトをとることができる。In the method of manufacturing a semiconductor device according to any one of claims 1, 2 and 3, a step of forming an impurity diffusion region for element formation in a surface layer portion of one surface of a wafer-shaped semiconductor substrate. And a step of grinding the surface of the wafer-shaped semiconductor substrate opposite to the surface on which the element-forming impurity diffusion regions are formed to make the substrate have a predetermined thickness, and the element-forming impurities in the wafer-shaped semiconductor substrate. A step of forming a thin film by etching to a predetermined depth while leaving the outer peripheral portion of the semiconductor substrate on the surface opposite to the surface on which the diffusion region is formed, and the surface on which the impurity diffusion region for forming elements in the wafer-shaped semiconductor substrate is formed An impurity-doped polysilicon film is formed on the surface opposite to the surface, and impurities are diffused from the impurity-doped polysilicon film to the semiconductor substrate side to form a wafer-shaped semiconductor substrate. A step of forming a contact impurity diffusion region on the surface layer portion opposite to the surface on which the element forming impurity diffusion region is formed, and a step of forming a back electrode so as to contact the impurity-doped polysilicon film. There is. Therefore, the inner region of the wafer-shaped semiconductor substrate can be thinned while leaving the thick portion on the outer peripheral portion, and the electrode can be formed on the back surface without any fear of warpage or distortion.
Further, the diffusion of impurities from the impurity-doped polysilicon film, that is, the formation of the contact impurity diffusion region can be performed at a low temperature, and ohmic contact connection with low resistance is made to the back electrode through the contact impurity diffusion region. It becomes possible. As a result, it is possible to avoid strength problems in the wafer-shaped substrate and to make contact with the back electrode at a lower temperature.

【０００７】特に、請求項２に記載の発明においては、
ウエハ状の半導体基板を各チップにダイシングする工程
と、チップにおける両面側にヒートシンク材を接合する
とともに当該ヒートシンク材の一部が露出するようにし
て樹脂モールドする工程と、を備えている。よって、両
面放熱モールド構造とすることができる。Particularly, in the invention described in claim 2,
The method includes a step of dicing a wafer-shaped semiconductor substrate into each chip, and a step of bonding a heat sink material to both surface sides of the chip and resin-molding so that a part of the heat sink material is exposed. Therefore, a double-sided heat dissipation mold structure can be obtained.

【０００８】さらに、請求項３に記載の発明において
は、ダイシング前において、ウエハ状の半導体基板にお
ける素子形成用不純物拡散領域を形成した面に、熱的良
導性材料よりなる板材を接合する工程を備えている。よ
って、ダイシングしてチップ状態にしても容易に取り扱
うことができる。Further, in the third aspect of the present invention, before dicing, a step of bonding a plate material made of a thermally conductive material to the surface of the wafer-shaped semiconductor substrate on which the element-forming impurity diffusion regions are formed. Is equipped with. Therefore, it can be easily handled even if it is diced into a chip state.

【０００９】さらには、請求項４に記載の発明において
は、ダイシング前においてウエハ状の半導体基板におけ
る裏面電極を形成した面にも、熱的良導性材料よりなる
板材を接合する。よって、半導体基板における裏面電極
を形成した面において熱的良導性材料よりなる板材を介
してヒートシンク材が配置されるので、チップを中心位
置に配置し易く、放熱性の向上を図ることができる。Further, in the invention according to the fourth aspect, a plate member made of a thermally conductive material is also bonded to the surface of the wafer-shaped semiconductor substrate on which the back electrode is formed before dicing. Therefore, since the heat sink material is arranged on the surface of the semiconductor substrate on which the back electrode is formed via the plate material made of a thermally conductive material, the chip can be easily arranged at the center position and the heat dissipation can be improved. .

【００１０】[0010]

【発明の実施の形態】以下、この発明を具体化した一実
施の形態を図面に従って説明する。図１には、本実施形
態における半導体装置の全体構成を示す。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration of the semiconductor device according to this embodiment.

【００１１】図１において、シリコンチップ１には、図
２に示すように縦型パワーＭＯＳトランジスタが作り込
まれている。図１のチップ１の上面にはハンダ２を介し
て銅板３が接合されている。この銅板３は熱的良導性材
料よりなる板材である。また、チップ１の下面にはハン
ダ４を介してヒートシンク材５が接合されている。チッ
プ１とリードフレーム６とがワイヤー７にてボンディン
グされている。一方、前述の銅板３の上面にはハンダ８
を介してヒートシンク材９が接合されている。これらの
部材１，３，５，９は樹脂１０にてモールドされてい
る。ここで、ヒートシンク材９の上面とヒートシンク材
５の下面とはモールド用樹脂１０から露出している。こ
のように両面放熱モールド構造となっている。In FIG. 1, a silicon chip 1 is provided with a vertical power MOS transistor as shown in FIG. A copper plate 3 is bonded to the upper surface of the chip 1 of FIG. 1 via a solder 2. The copper plate 3 is a plate material made of a thermally conductive material. A heat sink material 5 is bonded to the lower surface of the chip 1 via a solder 4. The chip 1 and the lead frame 6 are bonded by a wire 7. On the other hand, solder 8 is placed on the upper surface of the copper plate 3 described above.
The heat sink material 9 is joined via the. These members 1, 3, 5, 9 are molded with resin 10. Here, the upper surface of the heat sink material 9 and the lower surface of the heat sink material 5 are exposed from the molding resin 10. Thus, it has a double-sided heat dissipation mold structure.

【００１２】図２において、半導体基板としてのｎ型シ
リコン基板２０は主表面（上面）とその反対面の裏面
（下面）を有している。このｎ型シリコン基板２０は厚
さが２５〜１５０μｍ程度であり、薄型パワーデバイス
となっている。このように基板２０の厚さが２５〜１５
０μｍ程度と薄くなっていることにより、縦方向に形成
される電流経路における基板２０での抵抗成分を低くし
てオン抵抗を低減することができる。In FIG. 2, an n-type silicon substrate 20 as a semiconductor substrate has a main surface (upper surface) and a back surface (lower surface) opposite to the main surface. The n-type silicon substrate 20 has a thickness of about 25 to 150 μm and is a thin power device. Thus, the thickness of the substrate 20 is 25 to 15
Since the thickness is as thin as about 0 μm, the resistance component in the substrate 20 in the current path formed in the vertical direction can be lowered to reduce the on-resistance.

【００１３】ｎ型シリコン基板２０の主表面（上面）に
おいて表層部にはｐ型ベース領域２１が形成されるとと
もに、ｐ型ベース領域２１の内部においてｎ+ソース領
域２２が形成されている。本例では、ｐ型ベース領域２
１およびｎ+ソース領域２２が素子形成用不純物拡散領
域である。また、ｎ型シリコン基板２０の主表面（上
面）の上にはゲート酸化膜２３を介してポリシリコンゲ
ート電極２４が形成されている。ポリシリコンゲート電
極２４は酸化膜２５にて覆われている。酸化膜２５の上
を含めたｎ型シリコン基板２０の主表面（上面）の上に
はソース電極２６が形成されている。ソース電極２６は
アルミ材よりなる。さらに、ソース電極２６の上には保
護膜（図示略）が形成されている。On the main surface (upper surface) of the n-type silicon substrate 20, a p-type base region 21 is formed in the surface layer portion, and an n + source region 22 is formed inside the p-type base region 21. In this example, the p-type base region 2
The 1 and n + source regions 22 are element forming impurity diffusion regions. A polysilicon gate electrode 24 is formed on the main surface (upper surface) of n-type silicon substrate 20 with gate oxide film 23 interposed. The polysilicon gate electrode 24 is covered with an oxide film 25. A source electrode 26 is formed on the main surface (upper surface) of the n-type silicon substrate 20 including the oxide film 25. The source electrode 26 is made of an aluminum material. Further, a protective film (not shown) is formed on the source electrode 26.

【００１４】一方、ｎ型シリコン基板２０の裏面（下
面）において表層部には、ｎ+型ドレインコンタクト領
域２７が形成されている。このｎ+型ドレインコンタク
ト領域２７の表面には不純物ドープトポリシリコン膜２
８を介してドレイン電極２９が基板裏面の全面に形成さ
れている。ドレイン電極（裏面電極）２９はチタン（Ｔ
ｉ）とニッケル（Ｎｉ）と金（Ａｕ）の積層体よりな
る。また、ｎ+型ドレインコンタクト領域２７は、不純
物ドープトポリシリコン膜２８からの不純物の拡散によ
り形成したものである。On the other hand, on the back surface (lower surface) of the n-type silicon substrate 20, an n + -type drain contact region 27 is formed in the surface layer portion. On the surface of the n + type drain contact region 27, the impurity-doped polysilicon film 2 is formed.
A drain electrode 29 is formed on the entire back surface of the substrate via the electrode 8. The drain electrode (back surface electrode) 29 is made of titanium (T
i), nickel (Ni), and gold (Au). The n + type drain contact region 27 is formed by diffusing impurities from the impurity-doped polysilicon film 28.

【００１５】このように本トランジスタ（ＤＭＯＳ）
は、シリコン基板２０における素子形成用不純物拡散領
域２１，２２を形成した面とは反対の面に不純物ドープ
トポリシリコン膜２８が形成され、この不純物ドープト
ポリシリコン膜２８に接するシリコン基板２０の表層部
に当該膜２８からの不純物の拡散によるコンタクト用不
純物拡散領域２７が形成されている。また、不純物ドー
プトポリシリコン膜２８に接するように裏面電極２９が
形成されている。さらに、シリコン基板２０における素
子形成用不純物拡散領域２１，２２を形成した面に、図
１に示すごとく熱的良導性材料よりなる板材３を介して
ヒートシンク材９が接合されるとともにシリコン基板２
０における裏面電極２９を形成した面にヒートシンク材
５が接合されている。これらヒートシンク材５，９の一
部が露出するようにして樹脂モールドされている。Thus, the present transistor (DMOS)
The impurity-doped polysilicon film 28 is formed on the surface of the silicon substrate 20 opposite to the surface on which the element-forming impurity diffusion regions 21 and 22 are formed, and the silicon substrate 20 in contact with the impurity-doped polysilicon film 28 is formed. Contact impurity diffusion regions 27 are formed in the surface layer portion by diffusion of impurities from the film 28. A back electrode 29 is formed in contact with the impurity-doped polysilicon film 28. Further, as shown in FIG. 1, the heat sink material 9 is bonded to the surface of the silicon substrate 20 on which the element-forming impurity diffusion regions 21 and 22 are formed, via the plate material 3 made of a thermally conductive material, and the silicon substrate 2
The heat sink material 5 is bonded to the surface of the No. 0 surface on which the back surface electrode 29 is formed. The heat sink materials 5 and 9 are resin-molded so that part of them are exposed.

【００１６】次に、製造方法を説明する。まず、図３
（ａ）に示すように、ウエハ状のｎ型シリコン基板（半
導体基板）３０を用意する。そして、このウエハ状のｎ
型シリコン基板３０に対し図２に示したように主表面側
にゲート酸化膜２３を介してポリシリコンゲート電極２
４を形成する（パターニングする）。そして、ウエハ状
のｎ型シリコン基板３０の主表面の表層部にｐ型ベース
領域２１とｎ+ソース領域２２を形成する。さらに、ポ
リシリコンゲート電極２４の上に酸化膜２５を形成する
とともに酸化膜２５の上を含めたｎ型シリコン基板３０
の主表面（上面）の上にアルミ材よりなるソース電極２
６を形成する。また、ゲート配線等の必要なアルミ配線
材および保護膜を形成する。Next, the manufacturing method will be described. First, FIG.
As shown in (a), a wafer-shaped n-type silicon substrate (semiconductor substrate) 30 is prepared. Then, this wafer-shaped n
As shown in FIG. 2, the polysilicon gate electrode 2 is formed on the main surface side of the type silicon substrate 30 via the gate oxide film 23.
4 is formed (patterned). Then, p-type base region 21 and n + source region 22 are formed in the surface layer portion of the main surface of wafer-shaped n-type silicon substrate 30. Further, an oxide film 25 is formed on the polysilicon gate electrode 24 and the n-type silicon substrate 30 including the oxide film 25 is formed.
Source electrode 2 made of aluminum on the main surface (upper surface) of
6 is formed. Also, necessary aluminum wiring material such as gate wiring and a protective film are formed.

【００１７】このようにして、ウエハ状のシリコン基板
３０における一方の面の表層部に素子形成用不純物拡散
領域２１，２２を形成するとともにソース電極２６や配
線材等を形成する。Thus, the element-forming impurity diffusion regions 21 and 22 are formed in the surface layer portion of one surface of the wafer-shaped silicon substrate 30, and the source electrode 26 and the wiring material are formed.

【００１８】その後、図３（ａ）に示すように、ウエハ
状のシリコン基板３０における素子形成用不純物拡散領
域２１，２２を形成した面とは反対の面（裏面）から研
削加工して当該基板３０を所定の厚さにする。つまり、
ウエハ状シリコン基板３０の裏面を研削加工（ＳＧ：Ｓ
urface Ｇrinding）して２５０μｍ程度まで薄くする。After that, as shown in FIG. 3A, the surface of the wafer-shaped silicon substrate 30 opposite to the surface on which the element-forming impurity diffusion regions 21 and 22 are formed (rear surface) is ground, and the substrate is ground. 30 is set to a predetermined thickness. That is,
The back surface of the wafer-shaped silicon substrate 30 is ground (SG: S
urface Grinding) and thin to about 250 μm.

【００１９】そして、図３（ｂ）に示すように、ウエハ
状のシリコン基板３０における素子形成用不純物拡散領
域２１，２２を形成した面とは反対の面（裏面）に対し
同シリコン基板３０の外周部を残して所定深さまでエッ
チングして薄膜化する（断面形状として凹状の薄型基板
とする）。詳しくは、図４，５に示すポットエッチング
装置を用いて、ウエハ外周部を除いて、２５〜１５０μ
ｍ程度まで薄くする。これにより、ウエハは４〜８イン
チであるが、外周の厚い部分が存在するので反り等が抑
えられる。Then, as shown in FIG. 3B, the surface of the silicon substrate 30 in the wafer shape is opposite to the surface (rear surface) opposite to the surface on which the impurity diffusion regions 21 and 22 for element formation are formed. The thin film is formed by etching to a predetermined depth while leaving the outer peripheral portion (a thin substrate having a concave sectional shape). More specifically, using the pot etching apparatus shown in FIGS.
Thin to about m. As a result, the wafer is 4 to 8 inches, but since there is a thick outer peripheral portion, warpage or the like is suppressed.

【００２０】ポットエッチング（薄肉加工用エッチン
グ）について、詳しく説明する。図４に、エッチングポ
ットＰｅの構成を示すとともに、図５に、薄肉加工用エ
ッチング装置としてのポットエッチング装置の全体構成
を示す。The pot etching (etching for thin wall processing) will be described in detail. FIG. 4 shows the configuration of the etching pot Pe, and FIG. 5 shows the overall configuration of the pot etching apparatus as an etching apparatus for thin wall processing.

【００２１】図４に示すように、エッチングポットＰｅ
は、プレート状のポットベース４０と、筒状のポットリ
ング４１とを具備し、ポットベース４０の上面にはシリ
コンウエハ３０が載置できるとともにその上にポットリ
ング４１が一方の開口部を下にした状態で配置される。
つまり、シリコンウエハ３０が筒状のポットリング４１
の下面開口部を塞ぐように配置される。より詳しくは、
ポットベース４０はその中央部がシリコンウエハ３０を
乗せる台の役割をしている。また、ポットベース４０に
おけるウエハ載置部の外周側には凹部４２が環状に形成
され、この凹部４２にポットリング４１の突部４３が嵌
合する。このように凹部４２は位置合わせの機能を持
つ。さらに、ポットベース４０における凹部４２の外周
側（ウエハ載置部の周囲）には、平坦なシール面Ｓ１が
環状に形成され、シール面Ｓ１には凹部４４が環状に形
成され真空用ポケットとして機能する。As shown in FIG. 4, the etching pot Pe
Comprises a plate-shaped pot base 40 and a cylindrical pot ring 41. The silicon wafer 30 can be placed on the upper surface of the pot base 40, and the pot ring 41 has one opening downward. It will be placed in the state of being.
That is, the silicon wafer 30 is a cylindrical pot ring 41.
Is arranged so as to close the lower surface opening of the. For more details,
The pot base 40 has a central portion which serves as a base on which the silicon wafer 30 is placed. Further, a recess 42 is formed in an annular shape on the outer peripheral side of the wafer mounting portion in the pot base 40, and the projection 43 of the pot ring 41 is fitted into this recess 42. In this way, the concave portion 42 has a function of positioning. Further, a flat seal surface S1 is formed in an annular shape on the outer peripheral side of the recess 42 in the pot base 40 (around the wafer mounting portion), and the recess 44 is formed in an annular shape on the seal surface S1 to function as a vacuum pocket. To do.

【００２２】また、ポットリング４１の下面での内周部
にはウエハ形シールパッキンＰｓが固定され、このパッ
キンＰｓはシリコンウエハ３０の縁部上面をシールすべ
くウエハ形状に形抜きされている。ウエハ形シールパッ
キンＰｓにより、ポットリング４１内に満たされるエッ
チング液に対しシールすることができる。つまり、シー
ルパッキンＰｓは、ポットベース４０にシリコンウエハ
３０を載置した状態でポットリング４１の下面とウエハ
３０の外周部とを液密状態でシールするためのものであ
る。また、ポットリング４１における下面外周部には平
坦なシール面Ｓ２が環状に形成され、このシール面Ｓ２
には凹部４５が環状に形成され真空用ポケットとして機
能する。A wafer-shaped seal packing Ps is fixed to the inner peripheral portion of the lower surface of the pot ring 41, and the packing Ps is cut into a wafer shape so as to seal the upper surface of the edge portion of the silicon wafer 30. The wafer-type seal packing Ps can seal the etching liquid with which the pot ring 41 is filled. That is, the seal packing Ps is for liquid-tightly sealing the lower surface of the pot ring 41 and the outer peripheral portion of the wafer 30 with the silicon wafer 30 placed on the pot base 40. A flat seal surface S2 is formed in an annular shape on the outer peripheral portion of the lower surface of the pot ring 41.
A concave portion 45 is formed in a ring shape in the groove and functions as a vacuum pocket.

【００２３】ポットベース４０のシール面Ｓ１とポット
リング４１のシール面Ｓ２との間には、環状のＸ形パッ
キン４６が配置されている。そして、真空ポンプ等で凹
部（真空用ポケット）４４，４５内の空気を排出するこ
とでＸ形パッキン４６が収縮してポットベース４０とポ
ットリング４１とが引き寄せられ、シールパッキンＰｓ
にてシリコンウエハ３０の外周部をシールした状態で固
定される。このように、Ｘ形パッキン４６が固定部材と
して機能する。An annular X-shaped packing 46 is arranged between the sealing surface S1 of the pot base 40 and the sealing surface S2 of the pot ring 41. Then, by discharging the air in the recesses (vacuum pockets) 44 and 45 with a vacuum pump or the like, the X-shaped packing 46 contracts to draw the pot base 40 and the pot ring 41, and the seal packing Ps.
The silicon wafer 30 is fixed in a sealed state at its outer periphery. Thus, the X-shaped packing 46 functions as a fixing member.

【００２４】このように構成したエッチングポットＰｅ
が図５に示すようにエッチング装置にセットされ、エッ
チングポットＰｅ内にエッチング液Ｌｅが注入される。
この際、ウエハ形シールパッキンＰｓによりシールされ
るとともにエッチング液Ｌｅに対しシリコンウエハ３０
の外周部がマスク（保護）される。The etching pot Pe having the above structure
Is set in the etching apparatus as shown in FIG. 5, and the etching liquid Le is injected into the etching pot Pe.
At this time, the silicon wafer 30 is sealed by the wafer type seal packing Ps, and the silicon wafer 30
The outer peripheral portion of is masked (protected).

【００２５】このようにエッチングポットＰｅの内部に
エッチング液Ｌｅが満たされるとともに、ポットＰｅの
底面部にシリコンウエハ３０が支持され、上向きのシリ
コンウエハ３０の被加工面がエッチング液Ｌｅにて覆わ
れる。In this manner, the etching pot Pe is filled with the etching liquid Le, the silicon wafer 30 is supported on the bottom surface of the pot Pe, and the surface to be processed of the upward facing silicon wafer 30 is covered with the etching liquid Le. .

【００２６】詳しくは、エッチングポットＰｅがポット
載置台４７の上に搭載されるとともに、エッチングポッ
トＰｅの上面開口部がキャップ４８にて塞がれる。キャ
ップ４８には攪拌翼４９がシール材５０にてシールされ
た状態で垂下され、モータ５１の駆動により同攪拌翼４
９が回転してエッチング液Ｌｅを攪拌する。また、キャ
ップ４８にはヒータ５２がシール材５３にてシールされ
た状態で垂下され、同ヒータ５２にてエッチング液Ｌｅ
が加熱される。さらに、キャップ４８には温度センサ５
４がシール材５５にてシールされた状態で垂下され、温
度センサ５４にてエッチング液Ｌｅの温度が検出され
る。そして、エッチング中はエッチング液Ｌｅが攪拌翼
４９により十分攪拌され、温調器５６により温度センサ
５４による液温が所定の温度となるようにヒータ５２が
通電制御される。More specifically, the etching pot Pe is mounted on the pot mounting table 47, and the upper opening of the etching pot Pe is closed by the cap 48. A stirring blade 49 is hung down on the cap 48 while being sealed by a sealing material 50, and the stirring blade 4 is driven by a motor 51.
9 rotates to stir the etching liquid Le. Further, a heater 52 is hung down on the cap 48 in a state of being sealed by a sealing material 53, and the etching liquid Le is dripped by the heater 52.
Is heated. Further, the cap 48 has a temperature sensor 5
4 is hung down while being sealed by the sealing material 55, and the temperature of the etching liquid Le is detected by the temperature sensor 54. Then, during the etching, the etching solution Le is sufficiently stirred by the stirring blade 49, and the heater 52 is energized and controlled by the temperature controller 56 so that the temperature of the solution by the temperature sensor 54 becomes a predetermined temperature.

【００２７】また、キャップ４８には洗浄用純水の通路
５７が形成され、ポットリング４１の内壁に沿って純水
をエッチングポットＰｅ内に注入することができる。ま
た、キャップ４８には排液口５８が形成され、ポットＰ
ｅ内でオーバーフローした液を排出することができる。Further, a passage 57 for pure water for cleaning is formed in the cap 48, and pure water can be injected into the etching pot Pe along the inner wall of the pot ring 41. A drain port 58 is formed in the cap 48, and the pot P
The liquid overflowing in e can be discharged.

【００２８】また、ポットベース４０には厚さセンサ５
９が設けられ、シリコンウエハ３０における凹部の底面
部での厚さ（エッチング量）を測定してエッチングの進
行状況を検出し、エッチング終了時期を検出する。The thickness sensor 5 is attached to the pot base 40.
9 is provided to measure the thickness (etching amount) of the bottom surface of the recess in the silicon wafer 30 to detect the progress of etching, and to detect the etching end time.

【００２９】そして、所定量のエッチングが行われ、シ
リコンウエハ３０における凹部の底面部での厚さが所望
の値になると、エッチングを停止すべく図５の通路５７
を通してエッチングポットＰｅ内に洗浄用純水が注入さ
れてエッチング液を希釈冷却するとともに、オーバーフ
ローした液が排液口５８を通して排水される。その後、
真空ポンプ等による凹部（真空用ポケット）４４，４５
内の真空引きを止めて凹部４４，４５内を大気圧にす
る。そして、キャップ４８およびポットリング４１（シ
ールパッキンＰｓ）を取り外して、エッチング加工後の
シリコンウエハ３０を次工程に送る。When a predetermined amount of etching is performed and the thickness of the bottom surface of the recess in the silicon wafer 30 reaches a desired value, the passage 57 of FIG.
Pure water for cleaning is injected into the etching pot Pe to dilute and cool the etching liquid, and the overflowed liquid is drained through the drain port 58. afterwards,
Recesses (vacuum pockets) 44, 45 by vacuum pump, etc.
The vacuum inside is stopped and the inside of the recesses 44 and 45 is brought to atmospheric pressure. Then, the cap 48 and the pot ring 41 (seal packing Ps) are removed, and the silicon wafer 30 after etching is sent to the next step.

【００３０】図４，５の説明を終え、製造工程の説明に
戻る。引き続き、図３（ｃ）に示すように、ウエハ状の
シリコン基板３０における素子形成用不純物拡散領域２
１，２２を形成した面とは反対の面（裏面）に不純物ド
ープトポリシリコン膜３１を形成（堆積）するととも
に、不純物ドープトポリシリコン膜３１からシリコン基
板３０側に不純物を拡散させて（ドーピングし）ウエハ
状のシリコン基板３０における素子形成用不純物拡散領
域２１，２２を形成した面とは反対の面の表層部にｎ+
コンタクト用不純物拡散領域２７（図２参照）を形成す
る。詳しくは、不純物ドープトポリシリコン膜３１を堆
積するときの温度は４５０℃以下で、例えばＬＰ（減
圧）−ＣＶＤ法あるいは、ＰＶＤ（スパッタ）法を用い
る。これは、ポリシリコンは単結晶に比べ数倍から数十
倍の拡散速度であるとともに、結晶間に多量の不純物を
ドープすることができるためであり、これによりトラン
ジスタセル、アルミによる電極や配線材を形成した後の
工程で、裏面に不純物を高濃度に導入することが可能と
なる。After the description of FIGS. 4 and 5, the description returns to the manufacturing process. Subsequently, as shown in FIG. 3C, the element-forming impurity diffusion regions 2 in the wafer-shaped silicon substrate 30.
Impurity-doped polysilicon film 31 is formed (deposited) on the surface (back surface) opposite to the surface on which 1 and 22 are formed, and impurities are diffused from impurity-doped polysilicon film 31 to the silicon substrate 30 side ( N + is formed on the surface layer portion of the surface of the silicon substrate 30 in the form of a wafer which is opposite to the surface on which the element forming impurity diffusion regions 21 and 22 are formed.
The contact impurity diffusion region 27 (see FIG. 2) is formed. Specifically, the temperature at which the impurity-doped polysilicon film 31 is deposited is 450 ° C. or lower, and for example, LP (decompression) -CVD method or PVD (sputtering) method is used. This is because polysilicon has a diffusion rate that is several to several tens of times that of single crystals, and it is possible to dope a large amount of impurities between crystals, which allows transistor cells, electrodes and wiring materials made of aluminum. It becomes possible to introduce a high concentration of impurities into the back surface in a step after the formation of.

【００３１】その後、図３（ｄ）に示すように、不純物
ドープトポリシリコン膜３１に接するように裏面電極３
２を形成する。つまり、Ｔｉ、Ｎｉ、Ａｕの各膜を順に
形成する。Thereafter, as shown in FIG. 3D, the back electrode 3 is contacted with the impurity-doped polysilicon film 31.
Form 2. That is, Ti, Ni, and Au films are sequentially formed.

【００３２】このようにして、４５０℃以下で不純物ド
ープトポリシリコン膜３１を堆積し、ドーピング（熱処
理）することにより、ｎ+型ドレインコンタクト層２７
が形成され、この高濃度層２７を介して低抵抗なるオー
ミックコンタクト接続することが可能となる。In this way, the impurity-doped polysilicon film 31 is deposited at 450 ° C. or lower and doped (heat-treated), whereby the n + type drain contact layer 27 is formed.
Is formed, and ohmic contact connection with low resistance can be performed through the high concentration layer 27.

【００３３】引き続き、図６に示すように、ウエハ状の
シリコン基板３０における素子形成用不純物拡散領域２
１，２２を形成した面（ソース電極側）に、銅板（熱的
良導性材料よりなる板材）３３を接合し、その後に、ウ
エハ状のシリコン基板３０をダイシング（スクライブ）
して各チップにする。これは、以下の理由による。図３
（ｄ）の状態においてはセル領域は厚みが２５〜１５０
μｍ程度まで薄くしているので、ダイシングしてチップ
状態にすると取り扱いが困難となる。そこで、図６のよ
うにソース側に板材３３をハンダ付けして、ダイシング
にてチップ状態にしても容易に取り扱うことができる。Subsequently, as shown in FIG. 6, the element-forming impurity diffusion regions 2 in the wafer-shaped silicon substrate 30.
A copper plate (a plate material made of a thermally conductive material) 33 is bonded to the surface (source electrode side) on which 1 and 22 are formed, and then the wafer-shaped silicon substrate 30 is diced (scribed).
And make each chip. This is for the following reason. Figure 3
In the state of (d), the cell region has a thickness of 25 to 150.
Since the thickness is reduced to about μm, it becomes difficult to handle when dicing into chips. Therefore, as shown in FIG. 6, the plate member 33 is soldered to the source side and can be easily handled even in a chip state by dicing.

【００３４】図７は、ウエハ状のシリコン基板３０およ
び板材３３の平面図である。図６，７に示すように、ウ
エハ状のシリコン基板３０は円板状をなしている。ま
た、板材（銅板）３３は四角形状をなしている。板材３
３には突起３３ａが形成されている。この突起３３ａ
は、ウエハ状のシリコン基板３０における各チップ形成
予定領域でのソース領域（各チップでのソース電極）に
対応しており、突起３３ａの平面形状は例えば正方形で
ある。板材３３に関して、より具体的には、例えば銅板
にニッケル膜を無電解メッキし、これをプレスにより凹
凸を設けるとよい。また、ウエハ状のシリコン基板３０
と板材３３との接合の際に、板材３３の突起３３ａがウ
エハの各チップでのソース電極に対応するように目合わ
せして接合する。FIG. 7 is a plan view of a wafer-shaped silicon substrate 30 and a plate member 33. As shown in FIGS. 6 and 7, the wafer-shaped silicon substrate 30 has a disk shape. The plate material (copper plate) 33 has a quadrangular shape. Plate material 3
3 has a protrusion 33a formed thereon. This protrusion 33a
Corresponds to the source region (source electrode in each chip) in each chip formation planned region in the wafer-shaped silicon substrate 30, and the projection 33a has a square planar shape, for example. More specifically, with respect to the plate member 33, for example, a nickel film may be electrolessly plated on a copper plate, and the nickel film may be pressed to form irregularities. In addition, a wafer-shaped silicon substrate 30
At the time of bonding the plate material 33 with the plate material 33, the projections 33a of the plate material 33 are aligned and bonded so as to correspond to the source electrodes in each chip of the wafer.

【００３５】図８，９にはダイシング後のチップを示
す。シリコンチップ１が板材３とソース電極部分でハン
ダ付けされている。その後、図１に示すように、チップ
１における両面側にヒートシンク材５，９をハンダ付け
（接合）するとともに当該ヒートシンク材５，９の一部
が露出するようにして樹脂モールド（トランスファモー
ルド）する。8 and 9 show the chip after dicing. The silicon chip 1 is soldered to the plate member 3 and the source electrode portion. After that, as shown in FIG. 1, heat sink materials 5 and 9 are soldered (bonded) to both surface sides of the chip 1 and resin molding (transfer molding) is performed so that a part of the heat sink materials 5 and 9 is exposed. .

【００３６】ヒートシンク材５，９と板材３は、例えば
銅板（Ｃｕ板）で構成し、モールド樹脂１０についても
銅（Ｃｕ）に近い熱膨張係数を持つ材料を選択する。冷
熱サイクルにおける熱応力のバランスを考慮した場合、
異なる熱膨張係数を有するのはシリコンチップ１だけで
ある。よって、シリコンチップ１の厚みをできるだけ薄
くすることが熱応力アンバランスによる素子端面剥離と
か素子、樹脂のクラック防止に効果が大きく、耐冷熱サ
イクル性等の信頼性向上に有効である。The heat sink materials 5 and 9 and the plate material 3 are made of, for example, a copper plate (Cu plate), and the mold resin 10 is selected from materials having a thermal expansion coefficient close to that of copper (Cu). When considering the balance of thermal stress in the thermal cycle,
Only the silicon chip 1 has a different coefficient of thermal expansion. Therefore, it is effective to reduce the thickness of the silicon chip 1 as much as possible in order to prevent element end face peeling due to thermal stress imbalance, cracking of the element and resin, and to improve reliability such as resistance to cold and heat cycles.

【００３７】このようにして、ポットエッチング技術を
用いてウエハ状のシリコン基板３０の外周部に厚肉部を
残したままその内方の領域（アクティブ領域）を薄膜化
でき、反りや歪みの心配のない状態でウエハ裏面にスパ
ッタ等で電極を形成することができる。その結果、ウエ
ハ状シリコン基板３０における強度的な不具合を回避で
きる。また、エピタキシャル形成する必要がなくウエハ
（基板）のコストを低減できる。In this way, by using the pot etching technique, the inner region (active region) can be thinned while leaving the thick portion on the outer peripheral portion of the wafer-shaped silicon substrate 30, and there is a fear of warpage or distortion. The electrode can be formed on the back surface of the wafer without sputtering by sputtering or the like. As a result, it is possible to avoid strength problems in the wafer-shaped silicon substrate 30. Further, the cost of the wafer (substrate) can be reduced because it is not necessary to form it epitaxially.

【００３８】一方、ウエハの主表面側にベース・ソース
領域とアルミによる電極・配線材と保護膜（ＳｉＮ膜又
はＰＩＱ膜）を形成した後に、裏面側コンタクト確保の
ためｎ+高濃度層２７を形成する場合において、高濃度
層を形成する方法としては、イオン打ち込み法と熱拡散
による不純物導入法があり、イオン打ち込み法において
は後工程のアニールで５００〜７００℃でのアニールす
る必要があり、又、高濃度層形成のためにドーズ量を多
くし、打ち込まれたイオンの活性化率を１００％近くに
するには、必然的にアニール温度が高くなってしまう傾
向にある。また、熱拡散においては、より高い温度と時
間が要求される。このようなことから、主表面側にベー
ス・ソース領域とアルミによる電極・配線材を形成した
後の工程なので、特にアルミの軟化温度（４５０℃）以
下での処理が要求される。これに対し本実施形態におい
ては、不純物ドープトポリシリコン膜３１（２８）から
の不純物の拡散、つまり、高濃度層（コンタクト用不純
物拡散領域）２７の形成は低温で行うことができ、この
高濃度層（コンタクト用不純物拡散領域）２７を介して
裏面電極３２（２９）を低抵抗なるオーミックコンタク
ト接続することが可能となる。その結果、薄型で、か
つ、コンタクト用不純物拡散領域２７を介して裏面電極
２９を配した半導体装置において、より低温で裏面電極
のコンタクトをとることができ、高信頼性デバイスとす
ることができる。On the other hand, after forming a base / source region, an electrode / wiring material made of aluminum, and a protective film (SiN film or PIQ film) on the main surface side of the wafer, an n + high-concentration layer 27 is formed to secure a contact on the back surface side. In the case of forming, as a method of forming the high-concentration layer, there are an ion implantation method and an impurity introduction method by thermal diffusion. In the ion implantation method, it is necessary to anneal at a temperature of 500 to 700 ° C. in a subsequent annealing step. Further, the annealing temperature tends to be inevitably increased in order to increase the dose amount for forming the high-concentration layer and make the activation rate of the implanted ions close to 100%. Further, higher temperature and time are required for thermal diffusion. For this reason, since it is a process after the base / source regions and the electrode / wiring material made of aluminum are formed on the main surface side, treatment at a softening temperature of aluminum (450 ° C.) or lower is particularly required. On the other hand, in the present embodiment, diffusion of impurities from the impurity-doped polysilicon film 31 (28), that is, formation of the high-concentration layer (contact impurity diffusion region) 27 can be performed at a low temperature. The back electrode 32 (29) can be ohmic contact-connected with low resistance via the concentration layer (contact impurity diffusion region) 27. As a result, in a thin semiconductor device in which the back surface electrode 29 is disposed via the contact impurity diffusion region 27, the back surface electrode can be contacted at a lower temperature, and a highly reliable device can be obtained.

【００３９】以下、応用例を説明する。図８，９に示し
た構成に対し、図１０，１１に示すように、板材３に代
わる板材（銅板）６０の形状としてソース電極対応部を
広くしてもよい。この形状はプレスで作成できる。この
場合、樹脂にてモールドすると図１２に示すようにな
る。An application example will be described below. In contrast to the configurations shown in FIGS. 8 and 9, as shown in FIGS. 10 and 11, the source electrode corresponding portion may be widened as a shape of a plate material (copper plate) 60 instead of the plate material 3. This shape can be created by pressing. In this case, when molded with resin, it becomes as shown in FIG.

【００４０】また、図６，７に示したものに比べ図１
３，１４に示すようにしてもよい。つまり、図３（ｄ）
のウエハ３０に対し図１３，１４に示すように、ウエハ
状基板３０のソース側に板材（銅板）３３をハンダ付け
するとともにウエハ状基板３０のドレイン側に板材（銅
板）７０をハンダ付けする。このようにしてダイシング
前においてウエハ状のシリコン基板３０における裏面電
極３２を形成した面にも、熱的良導性材料よりなる板材
７０をハンダ付け（接合）する。そして、ダイシング
し、さらに、図１５に示すようにヒートシンク材５，９
の間においてハンダ付けし、樹脂１０にてモールドす
る。図１５においては、板材７０によりシリコンチップ
１をヒートシンク材５から持ち上げて（より離間して）
配置でき、縦方向のパッケージ断面においてシリコンチ
ップ１をちょうどセンターに位置させることができる。
これにより、熱応力のバランスをとり、熱歪がチップ端
面に集中しない。その結果、ヒートサイクルに対する耐
久性が更に向上する。In addition, as compared with those shown in FIGS.
3 and 14 may be shown. That is, FIG. 3 (d)
13 and 14, a plate material (copper plate) 33 is soldered to the source side of the wafer-shaped substrate 30 and the plate material (copper plate) 70 is soldered to the drain side of the wafer-shaped substrate 30 as shown in FIGS. In this way, the plate member 70 made of a thermally conductive material is also soldered (bonded) to the surface of the wafer-shaped silicon substrate 30 on which the back electrode 32 is formed before dicing. Then, dicing is performed, and further, as shown in FIG.
Solder between them and mold with resin 10. In FIG. 15, the silicon chip 1 is lifted from the heat sink material 5 by the plate material 70 (further away from the heat sink material 5).
It can be arranged, and the silicon chip 1 can be positioned exactly in the center in the package cross section in the vertical direction.
This balances the thermal stress and prevents thermal strain from concentrating on the chip end surface. As a result, the durability against heat cycle is further improved.

【００４１】このように、チップ１における裏面電極２
９を形成した面に、熱的良導性材料よりなる板材７０を
介してヒートシンク材５を配置することにより、チップ
１を中心位置に配置し易く、放熱性の向上を図ることが
できる。Thus, the back surface electrode 2 of the chip 1 is
By disposing the heat sink material 5 on the surface on which the chip 9 is formed via the plate material 70 made of a thermally conductive material, it is easy to dispose the chip 1 at the center position and the heat dissipation can be improved.

【００４２】なお、これまでの説明においては半導体装
置として縦型ＭＯＳＦＥＴに適用した場合について説明
してきたが、縦型ＩＧＢＴ（絶縁ゲート型バイポーラト
ランジスタ）に適用してもよい。この場合には裏面電極
はコレクタ電極となる。In the above description, the case where the present invention is applied to the vertical MOSFET as the semiconductor device has been explained, but it may be applied to the vertical IGBT (insulated gate bipolar transistor). In this case, the back electrode becomes the collector electrode.

【図面の簡単な説明】[Brief description of drawings]

【図１】実施の形態における半導体装置の全体構成図。FIG. 1 is an overall configuration diagram of a semiconductor device according to an embodiment.

【図２】シリコンチップの縦断面図。FIG. 2 is a vertical sectional view of a silicon chip.

【図３】製造工程を説明するための断面図。FIG. 3 is a cross-sectional view for explaining the manufacturing process.

【図４】エッチングポットの断面図。FIG. 4 is a sectional view of an etching pot.

【図５】エッチング装置の断面図。FIG. 5 is a sectional view of an etching apparatus.

【図６】製造工程を説明するための断面図。FIG. 6 is a cross-sectional view for explaining the manufacturing process.

【図７】製造工程を説明するための平面図。FIG. 7 is a plan view for explaining the manufacturing process.

【図８】製造工程を説明するための平面図。FIG. 8 is a plan view for explaining the manufacturing process.

【図９】製造工程を説明するための断面図。FIG. 9 is a cross-sectional view for explaining the manufacturing process.

【図１０】別例の製造工程を説明するための平面図。FIG. 10 is a plan view for explaining another manufacturing process.

【図１１】別例の製造工程を説明するための断面図。FIG. 11 is a cross-sectional view for explaining the manufacturing process of another example.

【図１２】別例の半導体装置の全体構成図。FIG. 12 is an overall configuration diagram of a semiconductor device of another example.

【図１３】別例の製造工程を説明するための断面図。FIG. 13 is a cross-sectional view for explaining the manufacturing process of another example.

【図１４】別例の製造工程を説明するための平面図。FIG. 14 is a plan view for explaining another manufacturing process.

【図１５】別例の半導体装置の全体構成図。FIG. 15 is an overall configuration diagram of a semiconductor device of another example.

【符号の説明】[Explanation of symbols]

１…シリコンチップ、３…板材、５…ヒートシンク材、
９…ヒートシンク材、２０…ｎ型シリコン基板、２１…
ｐ型ベース領域、２２…ｎ+ソース領域、２３…ゲート
酸化膜、２４…ゲート電極、２６…ソース電極、２７…
ｎ+コンタクト領域、２８…不純物ドープトポリシリコ
ン膜、２９…ドレイン電極、３０…ウエハ状シリコン基
板、３１…不純物ドープトポリシリコン膜、３２…裏面
電極、３３…板材、７０…板材。1 ... Silicon chip, 3 ... Plate material, 5 ... Heat sink material,
9 ... Heat sink material, 20 ... N type silicon substrate, 21 ...
p-type base region, 22 ... N + source region, 23 ... Gate oxide film, 24 ... Gate electrode, 26 ... Source electrode, 27 ...
n + contact region, 28 ... Impurity-doped polysilicon film, 29 ... Drain electrode, 30 ... Wafer-shaped silicon substrate, 31 ... Impurity-doped polysilicon film, 32 ... Back electrode, 33 ... Plate material, 70 ... Plate material.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 29/78 ６５８Ｆ ６５８Ａ (72)発明者 平野 尚彦 愛知県刈谷市昭和町１丁目１番地 株式会 社デンソー内 (72)発明者 則武 千景 愛知県刈谷市昭和町１丁目１番地 株式会 社デンソー内─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 29/78 658F 658A (72) Inventor Naohiko Hirano 1-1c Showa-cho, Kariya city, Aichi prefecture DENSO CORPORATION (72) Inventor Noritake Chikage 1-1, Showa-cho, Kariya city, Aichi Prefecture DENSO CORPORATION

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 半導体基板（２０）における一方の面の
表層部に素子形成用不純物拡散領域（２１，２２）が形
成されるとともに、前記半導体基板（２０）における他
方の面の表層部にコンタクト用不純物拡散領域（２７）
が形成され、当該コンタクト用不純物拡散領域（２７）
を介して裏面電極（２９）が配置された半導体装置の製
造方法であって、 ウエハ状の半導体基板（３０）における一方の面の表層
部に素子形成用不純物拡散領域（２１，２２）を形成す
る工程と、 前記ウエハ状の半導体基板（３０）における素子形成用
不純物拡散領域（２１，２２）を形成した面とは反対の
面から研削加工して当該基板（３０）を所定の厚さにす
る工程と、 前記ウエハ状の半導体基板（３０）における素子形成用
不純物拡散領域（２１，２２）を形成した面とは反対の
面に対し同半導体基板（３０）の外周部を残して所定深
さまでエッチングして薄膜化する工程と、 前記ウエハ状の半導体基板（３０）における素子形成用
不純物拡散領域（２１，２２）を形成した面とは反対の
面に不純物ドープトポリシリコン膜（３１）を形成する
とともに、不純物ドープトポリシリコン膜（３１）から
半導体基板（３０）側に不純物を拡散させてウエハ状の
半導体基板（３０）における素子形成用不純物拡散領域
（２１，２２）を形成した面とは反対の面の表層部にコ
ンタクト用不純物拡散領域（２７）を形成する工程と、 前記不純物ドープトポリシリコン膜（３１）に接するよ
うに裏面電極（３２）を形成する工程と、を備えたこと
を特徴とする半導体装置の製造方法。1. A semiconductor substrate (20) is provided with element-forming impurity diffusion regions (21, 22) in a surface layer portion of one surface thereof, and contacts the surface layer portion of the other surface of the semiconductor substrate (20). Impurity diffusion region (27)
And the contact impurity diffusion region (27) is formed.
A method of manufacturing a semiconductor device in which a back surface electrode (29) is disposed via a device, comprising: forming element-forming impurity diffusion regions (21, 22) in a surface layer portion of one surface of a wafer-shaped semiconductor substrate (30). And a step of grinding the wafer-shaped semiconductor substrate (30) from the surface opposite to the surface on which the element-forming impurity diffusion regions (21, 22) are formed to bring the substrate (30) to a predetermined thickness. And a predetermined depth with respect to the surface of the wafer-shaped semiconductor substrate (30) opposite to the surface on which the element-forming impurity diffusion regions (21, 22) are formed, leaving the outer peripheral portion of the semiconductor substrate (30). Then, the step of etching to reduce the thickness, and the impurity-doped polysilicon film (31) on the surface of the semiconductor substrate (30) opposite to the surface on which the element-forming impurity diffusion regions (21, 22) are formed. And the impurities were diffused from the impurity-doped polysilicon film (31) to the semiconductor substrate (30) side to form the element-forming impurity diffusion regions (21, 22) in the wafer-shaped semiconductor substrate (30). A step of forming a contact impurity diffusion region (27) on the surface layer opposite to the surface, and a step of forming a back electrode (32) in contact with the impurity-doped polysilicon film (31). A method of manufacturing a semiconductor device, comprising: 【請求項２】 半導体基板（２０）における一方の面の
表層部に素子形成用不純物拡散領域（２１，２２）が形
成されるとともに、前記半導体基板（２０）における他
方の面の表層部にコンタクト用不純物拡散領域（２７）
が形成され、当該コンタクト用不純物拡散領域（２７）
を介して裏面電極（２９）が配置された半導体装置の製
造方法であって、 ウエハ状の半導体基板（３０）における一方の面の表層
部に素子形成用不純物拡散領域（２１，２２）を形成す
る工程と、 前記ウエハ状の半導体基板（３０）における素子形成用
不純物拡散領域（２１，２２）を形成した面とは反対の
面から研削加工して当該基板（３０）を所定の厚さにす
る工程と、 前記ウエハ状の半導体基板（３０）における素子形成用
不純物拡散領域（２１，２２）を形成した面とは反対の
面に対し同半導体基板（３０）の外周部を残して所定深
さまでエッチングして薄膜化する工程と、 前記ウエハ状の半導体基板（３０）における素子形成用
不純物拡散領域（２１，２２）を形成した面とは反対の
面に不純物ドープトポリシリコン膜（３１）を形成する
とともに、不純物ドープトポリシリコン膜（３１）から
半導体基板（３０）側に不純物を拡散させてウエハ状の
半導体基板（３０）における素子形成用不純物拡散領域
（２１，２２）を形成した面とは反対の面の表層部にコ
ンタクト用不純物拡散領域（２７）を形成する工程と、 前記不純物ドープトポリシリコン膜（３１）に接するよ
うに裏面電極（３２）を形成する工程と、 前記ウエハ状の半導体基板（３０）を各チップにダイシ
ングする工程と、 チップにおける両面側にヒートシンク材（５，９）を接
合するとともに当該ヒートシンク材（５，９）の一部が
露出するようにして樹脂モールドする工程と、を備えた
ことを特徴とする半導体装置の製造方法。2. A semiconductor substrate (20) is provided with element-forming impurity diffusion regions (21, 22) in a surface layer portion of one surface thereof, and contacts the surface layer portion of the other surface of the semiconductor substrate (20). Impurity diffusion region (27)
And the contact impurity diffusion region (27) is formed.
A method of manufacturing a semiconductor device in which a back surface electrode (29) is disposed via a device, comprising: forming element-forming impurity diffusion regions (21, 22) in a surface layer portion of one surface of a wafer-shaped semiconductor substrate (30). And a step of grinding the wafer-shaped semiconductor substrate (30) from the surface opposite to the surface on which the element-forming impurity diffusion regions (21, 22) are formed to bring the substrate (30) to a predetermined thickness. And a predetermined depth with respect to the surface of the wafer-shaped semiconductor substrate (30) opposite to the surface on which the element-forming impurity diffusion regions (21, 22) are formed, leaving the outer peripheral portion of the semiconductor substrate (30). Then, the step of etching to reduce the thickness, and the impurity-doped polysilicon film (31) on the surface of the semiconductor substrate (30) opposite to the surface on which the element-forming impurity diffusion regions (21, 22) are formed. And the impurities were diffused from the impurity-doped polysilicon film (31) to the semiconductor substrate (30) side to form the element-forming impurity diffusion regions (21, 22) in the wafer-shaped semiconductor substrate (30). Forming a contact impurity diffusion region (27) on the surface layer opposite to the surface; forming a back electrode (32) in contact with the impurity-doped polysilicon film (31); A step of dicing a wafer-shaped semiconductor substrate (30) into each chip, and joining heat sink materials (5, 9) to both sides of the chip and exposing a part of the heat sink material (5, 9) A method of manufacturing a semiconductor device, comprising: a step of resin molding. 【請求項３】 半導体基板（２０）における一方の面の
表層部に素子形成用不純物拡散領域（２１，２２）が形
成されるとともに、前記半導体基板（２０）における他
方の面の表層部にコンタクト用不純物拡散領域（２７）
が形成され、当該コンタクト用不純物拡散領域（２７）
を介して裏面電極（２９）が配置された半導体装置の製
造方法であって、 ウエハ状の半導体基板（３０）における一方の面の表層
部に素子形成用不純物拡散領域（２１，２２）を形成す
る工程と、 前記ウエハ状の半導体基板（３０）における素子形成用
不純物拡散領域（２１，２２）を形成した面とは反対の
面から研削加工して当該基板（３０）を所定の厚さにす
る工程と、 前記ウエハ状の半導体基板（３０）における素子形成用
不純物拡散領域（２１，２２）を形成した面とは反対の
面に対し同半導体基板（３０）の外周部を残して所定深
さまでエッチングして薄膜化する工程と、 前記ウエハ状の半導体基板（３０）における素子形成用
不純物拡散領域（２１，２２）を形成した面とは反対の
面に不純物ドープトポリシリコン膜（３１）を形成する
とともに、不純物ドープトポリシリコン膜（３１）から
半導体基板（３０）側に不純物を拡散させてウエハ状の
半導体基板（３０）における素子形成用不純物拡散領域
（２１，２２）を形成した面とは反対の面の表層部にコ
ンタクト用不純物拡散領域（２７）を形成する工程と、 前記不純物ドープトポリシリコン膜（３１）に接するよ
うに裏面電極（３２）を形成する工程と、 前記ウエハ状の半導体基板（３０）における素子形成用
不純物拡散領域（２１，２２）を形成した面に、熱的良
導性材料よりなる板材（３３）を接合する工程と、 前記ウエハ状の半導体基板（３０）を各チップにダイシ
ングする工程と、 チップにおける両面側にヒートシンク材（５，９）を接
合するとともに当該ヒートシンク材（５，９）の一部が
露出するようにして樹脂モールドする工程と、を備えた
ことを特徴とする半導体装置の製造方法。3. An element forming impurity diffusion region (21, 22) is formed in a surface layer portion of one surface of a semiconductor substrate (20), and a contact is made with the surface layer portion of the other surface of the semiconductor substrate (20). Impurity diffusion region (27)
And the contact impurity diffusion region (27) is formed.
A method of manufacturing a semiconductor device in which a back surface electrode (29) is disposed via a device, comprising: forming element-forming impurity diffusion regions (21, 22) in a surface layer portion of one surface of a wafer-shaped semiconductor substrate (30). And a step of grinding the wafer-shaped semiconductor substrate (30) from the surface opposite to the surface on which the element-forming impurity diffusion regions (21, 22) are formed to bring the substrate (30) to a predetermined thickness. And a predetermined depth with respect to the surface of the wafer-shaped semiconductor substrate (30) opposite to the surface on which the element-forming impurity diffusion regions (21, 22) are formed, leaving the outer peripheral portion of the semiconductor substrate (30). Then, the step of etching to reduce the thickness, and the impurity-doped polysilicon film (31) on the surface of the semiconductor substrate (30) opposite to the surface on which the element-forming impurity diffusion regions (21, 22) are formed. And the impurities were diffused from the impurity-doped polysilicon film (31) to the semiconductor substrate (30) side to form the element-forming impurity diffusion regions (21, 22) in the wafer-shaped semiconductor substrate (30). Forming a contact impurity diffusion region (27) on the surface layer opposite to the surface; forming a back electrode (32) in contact with the impurity-doped polysilicon film (31); Bonding a plate member (33) made of a thermally conductive material to the surface of the wafer-shaped semiconductor substrate (30) on which the element-forming impurity diffusion regions (21, 22) are formed, and the wafer-shaped semiconductor substrate Step of dicing (30) into each chip, and joining heat sink materials (5, 9) to both sides of the chip and exposing part of the heat sink material (5, 9) And a step of resin molding as described above. 【請求項４】 ダイシング前において前記ウエハ状の半
導体基板（３０）における裏面電極（３２）を形成した
面にも、熱的良導性材料よりなる板材（７０）を接合す
るようにしたことを特徴とする請求項３に記載の半導体
装置の製造方法。4. A plate member (70) made of a thermally conductive material is bonded to the surface of the wafer-shaped semiconductor substrate (30) on which the back electrode (32) is formed before dicing. The method for manufacturing a semiconductor device according to claim 3, wherein the semiconductor device is manufactured. 【請求項５】 半導体基板（２０）に作り込まれるのは
縦型パワーＭＯＳトランジスタであることを特徴とする
請求項１〜４のいずれか１項に記載の半導体装置の製造
方法。5. The method of manufacturing a semiconductor device according to claim 1, wherein a vertical power MOS transistor is built in the semiconductor substrate (20).
JP2002086408A 2001-07-26 2002-03-26 Method for manufacturing semiconductor device Expired - Fee Related JP3580293B2 (en)

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US10/201,556 US7145254B2 (en) 2001-07-26 2002-07-24 Transfer-molded power device and method for manufacturing transfer-molded power device
KR1020020043963A KR100659376B1 (en) 2001-07-26 2002-07-25 Transfer-molded power device and method for manufacturing transfer-molded power device
DE10234155A DE10234155B4 (en) 2001-07-26 2002-07-26 Press-molded power component
CNB02127066XA CN1267990C (en) 2001-07-26 2002-07-26 Pressure cast power device and its making process
KR1020060092571A KR20060109390A (en) 2001-07-26 2006-09-22 Transfer-molded power device and method for manufacturing transfer-molded power device

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US7521757B2 (en) 2006-06-22 2009-04-21 Fuji Electric Device Technology Co., Ltd. Semiconductor device with back surface electrode including a stress relaxation film
CN116598210A (en) * 2023-07-12 2023-08-15 江苏富乐华半导体科技股份有限公司 Method for manufacturing retaining dam for DPC product

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