JP2003281112A - Multiprocessor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow an interrupt arbitrating circuit to arbitrate an interrupt request in a multiprocessor system including a plurality of processor units. <P>SOLUTION: The multiprocessor system includes the plurality of processor units 1<SB>1</SB>-1<SB>n</SB>, a plurality of slave units 2<SB>1</SB>-2<SB>m</SB>and a common memory 3 that are connected via a global bus 4, and the interrupt arbitrating circuit 5 for receiving and detecting the interrupt request from the slave unit and sending the interrupt request to the processor unit. This interrupt arbitrating circuit 5 includes a status monitoring section 18 for collecting status information about the presence or absence of the plurality of mounted processor units 1<SB>1</SB>-1<SB>n</SB>, the presence or absence of trouble or the like, and an interrupt target selecting section 17 for selecting the mounted processor unit without trouble based on the status monitoring section 18 and sending the interrupt request. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention connects a plurality of processor units, a plurality of slave units, and a common memory via a global bus, and arbitrates an interrupt request from a slave unit by an interrupt arbitration circuit, so that the interrupt request from the slave unit is transferred to the global bus. The present invention relates to a multiprocessor system that recognizes connected and sound processor units and performs interrupt processing.

[0002]

2. Description of the Related Art A multiprocessor system includes a plurality of processor units, a plurality of slave units such as input / output devices, and a common memory for storing various data, which are interconnected via a global bus. . Since each processor unit can simultaneously process a plurality of tasks, it is possible to increase the processing capacity as compared with a system configured by a single processor unit. Further, even if a failure occurs in a part of the processor units, another healthy processor unit can substitute and process, so that the reliability of the system can be improved.

Various means for interrupting a processor unit in response to an interrupt request from a slave unit have already been proposed. For example, a means for sending a broadcast notification to a processor unit connected to a global bus is known. In this case, the processor unit that acquires the global bus earliest by the broadcast notification of the interrupt determines the processing type of the interrupt notified via the global bus, and queues the processing task for the interrupt inside the processor unit, Clear the interrupt factor and release the global bus.

Then, when the interrupt is held in the other processor unit by the broadcast notification of the interrupt and the global bus is released, the next processor unit which has acquired this global bus passes through the global bus. The interrupt cause to be notified is determined by the processor unit that acquired the first global bus, but the interrupt factor has already been cleared. The global bus is released and normal processing is resumed without performing any special processing. Similarly, for other processor units, the global bus is acquired and the empty factor is detected.

As described above, in the case of the broadcast notification, the bandwidth of the global bus is consumed by repeatedly performing the global bus acquisition processing, so that the processing capability of the entire system is reduced. Further, in the case of pipeline processing, the time-series continuity is lost, the use efficiency of the cache is deteriorated, and the processing capacity is further deteriorated.

Therefore, an interrupt arbitration circuit is provided between the slave unit and the processor unit, and the interrupt arbitration circuit provides means for notifying only one processor unit or a part of the processor unit groups for notifying the interrupt. Are known. However, it is not easy to select an appropriate processor unit because there are a wide variety of interrupt factors and the corresponding processing contents on the processor unit side, and if an appropriate selection is not made, an imbalance in processing load occurs. As a result, the processing capacity of the system is reduced. In a system that requires redundancy, the number of processor units may increase or decrease due to a failure, but it is not easy to grasp and select the processor units that can be used for interrupt processing. .

Further, an interrupt arbitration circuit (arbitration device) is provided for a plurality of processors, and the rank of the processor is obtained from the available signal for each processor, a signal indicating the rank, and a signal indicating the history of interrupt processing. There is known a multiprocessor system in which a processor whose rank is significantly changed in a predetermined direction is used as an interrupt processor (for example, Japanese Patent Laid-Open No. 4-232).
558).

In addition, a multiprocessor system in which a plurality of processors are divided into a master and a plurality of non-masters, the master or non-master designation information is included in the interrupt request, and the allocation control unit distributes the interrupt request to the processors according to the designation information is provided. Known (for example, Japanese Patent Laid-Open No. 2000-3
05917).

[0009]

In a conventional multiprocessor system, in the case of a configuration in which an interrupt request is broadcasted to a plurality of processors, each processor unit sequentially acquires a global bus and interrupts. The processor unit that first acquires the global bus can perform interrupt processing according to the determination of the interrupt processing type, but the acquisition processing of the global bus by other processor units is useless. However, there is a problem in that the bandwidth consumption of the global bus is increased and the system capacity is reduced. In addition, there is a high possibility that the continuity of time-series processing in the processor unit will be lost, and this will also cause a problem of system performance degradation.

Further, in the case of a configuration in which an interrupt arbitration circuit is provided and a single or a plurality of processor units are selected to issue an interrupt notification, it is difficult to make a selection while achieving load distribution. Further, the means for obtaining the rank of the processor and setting the processor unit that performs the interrupt notification according to the rank is because the state of the processor unit such as mounted, unmounted, sound, and unhealthy is not known. However, there is a problem that it is not possible to flexibly deal with system expansion and reduction. Further, the above-mentioned means for presetting the master and the non-master and designating the master or the non-master for the interrupt request has a high possibility that the interrupt processing is concentrated on the master. Therefore, when a plurality of processor units are provided, There was a problem that the load distribution was not sufficient and that it was not possible to flexibly deal with the increase or decrease of the processor unit.

According to the present invention, the presence or absence of mounting and the presence or absence of a failure due to an increase or decrease in the number of processor units are monitored, and one or a group of healthy processors is selected to issue an interrupt notification to balance load and load. The purpose is to provide a flexible system.

[0012]

A multiprocessor system according to the present invention will be described with reference to FIG. 1. A plurality of processor units 1 ₁ to 1 _n and a plurality of slave units 2 are described.
_A multiprocessor system in which _{1 to} 2 _m and a common memory 3 are connected via a global bus 4 and interrupt processing in the processor unit is performed in accordance with an interrupt request from the slave units 2 ₁ to 2 _m. The interrupt arbitration circuit 5 for receiving the interrupt request of 1 and sending the interrupt request to the processor unit. The interrupt arbitration circuit 5 includes a state monitoring unit 18 that collects state information such as whether or not a plurality of processor units 1 ₁ to 1 _n are mounted and whether there is a fault, and a processor that is mounted by the state monitoring unit 18 and has no fault. An interrupt destination selecting unit 17 for selecting a unit as an interrupt destination for sending an interrupt request from a slave unit.

The interrupt arbitration circuit also includes a status monitoring unit that collects status information of a plurality of processor units 1 ₁ to 1 _n , and a counter that detects and counts up interrupt requests from slave units 2 ₁ to 2 _m. , The counter that counts up the counter is determined by judging that the count value of this counter is selected as the processor unit of the interrupt destination, and that the count value of the counter specifies the processor unit that is not mounted or has a fault in the status monitoring unit. It is also possible to adopt a configuration including a determination device that causes the determination. Further, the interrupt arbitration circuit includes a plurality of processor units 1 ₁ to
A state monitoring unit that collects 1 _n state information, an interrupt destination selection unit that detects an interrupt request from the slave units 2 ₁ to 2 _m and selects an interrupt destination, and an interrupt destination selected by this interrupt destination selection unit A determiner for comparing and comparing the state information of the processor unit and the state information of the processor unit of the state monitoring unit, and an alternative destination generation for specifying the alternative processor unit when the interrupt destination processor unit selected by this determiner is not mounted or has a failure And a part. The interrupt arbitration circuit includes a load state monitoring unit that collects processing load information of a plurality of processor units and an interrupt destination selection unit that detects an interrupt request from a slave unit and selects an interrupt destination. The selection unit may include a configuration in which a processor unit having a low processing load collected by the load state monitoring unit is selected as an interrupt destination.

A multiprocessor system in which a plurality of processor units, a plurality of slave units, and a common memory are connected via a global bus, and interrupt processing is performed in the processor units according to an interrupt request from the slave units. , A plurality of interrupt arbitration circuits for receiving interrupt requests from the slave units and sending the interrupt requests to the processor units, each interrupt arbitration circuit including a status monitoring unit for collecting status information of the processor unit in charge, An interrupt destination selection unit that selects a processor unit in charge, which is mounted by the state monitoring unit and has no fault, as an interrupt destination to which an interrupt request from the slave unit is sent is included.

[0015]

1 is an explanatory view of a first embodiment of the present invention, in which 1 ₁ to 1 _n are processor units, 2
_{1 to} 2 _m are slave units, 2a is an interrupt factor holding unit, 3 is a common memory, 4 is a global bus, 5 is an interrupt arbitration circuit, 11 is an interrupt receiving unit, 12 is a priority encoder unit, and 13 is an interrupt factor latch register unit. , 14 is an interrupt ID holding unit, 15 is an interrupt detection unit, 16 is an interrupt transmission unit, 17 is an interrupt destination selection unit,
Reference numeral 18 indicates a state monitoring unit.

A plurality of processor units 1 ₁ to 1 _n ,
A plurality of slave units 2 _{1 to} 2 _m and a common memory 3 are connected by a global bus 4 to form a multiprocessor system. The slave units 2 ₁ to 2 _m are interrupt factor holding units 2a when an interrupt factor occurs. Set interrupt factor generation to and send an interrupt request. This interrupt request is arbitrated in the interrupt arbitration circuit 5, and a specific one unit or a specific one group in the installed and fault-free processor units is selected and an interrupt is notified. When the number of processor units is large, a large number of processor units are divided into a plurality of groups without specifying a single processor unit to be notified of an interrupt, a group is selected, and the processor units within the group are selected. Interrupt notification.

[0017] The interrupt arbitration circuit 5, an interrupt reception unit 11 for receiving an interrupt request from the slave units 2 ₁ to 2 _m, the priority encoder 12 for encoding according to the priority of the received interrupt request,
Interrupt factor latch register unit 13, interrupt ID holding unit 14 that holds an interrupt ID, interrupt detection unit 15 that detects a newly generated interrupt request, and interrupt transmission unit 1 that sends an interrupt request to a processor unit
6, an interrupt destination selection unit 17, and a state monitoring unit 18 that collects information on the processor unit.

When the interrupt receiving unit 11 receives the interrupt request from the slave unit, the priority encoder unit 12 performs encoding according to the priority order of the interrupt requests, and the interrupt ID is stored in the interrupt factor latch register 13 and the interrupt ID holding unit 14. And enter
The interrupt factor latch register 13 latches the interrupt factor on the global bus 4 according to the interrupt ID, and the interrupt detection unit 15 compares the interrupt ID held in the interrupt ID holding unit 14 with the interrupt ID of this time. If it has changed, it is determined that a new interrupt has occurred, the detection signal is input to the interrupt ID holding unit 14 and the interrupt destination selecting unit 17, and the interrupt ID of this time is stored in the interrupt ID holding unit 14. Hold the interrupt destination selection unit 17
Is notified that a new interrupt has occurred, and the interrupt ID holding unit 14 is notified of the current interrupt ID.

The status monitoring unit 18 collects information on the presence / absence of a processor unit and the presence / absence of a failure, grasps an available processor unit, and notifies the interrupt destination selecting unit 17 of the information. Therefore, the interrupt destination selection unit 17 selects one or a group of sound processor units according to the selection logic such as sequential selection, and the interrupt transmission unit 16 notifies the selected processor unit of an interrupt. The processor unit that receives this interrupt notification receives the interrupt ID from the interrupt factor latch register 13.
Is detected via the global bus 4, processing corresponding to the interrupt request is performed, and a clear instruction of the interrupt factor holding unit 2a is sent to the slave unit that has made the interrupt request. When the interrupt factor holding unit 2a is cleared in accordance with the clear instruction, the interrupt receiving unit 11 performs the next interrupt receiving process.

FIG. 2 is an explanatory diagram of the interrupt arbitration circuit according to the first embodiment of the present invention, and shows an embodiment of the interrupt arbitration circuit when eight processor units are used, which is the same as FIG. The reference numerals indicate the same parts. That is, the processor units 1 ₁ to ₁₈ and the plurality of slave units 2 ₁
And to 2 _m, and a common memory 3 constitute a multi-processor system connected by a global bus 4, the interrupt arbitration circuit 5, in which arbitrates interrupt requests from the slave units 2 ₁ to 2 _m. In the figure, 2
1 is a receiver, 22 is a priority encoder, 2
3, 24 and 25 are latch circuits, 26 and 29 are drivers,
27 is a dual port RAM (random access memory), 28 is a status monitoring unit, G1 to G10 are gate circuits, and G1 to G4 are inverters.

Corresponding to the configuration of FIG. 1, the receiver 21
Corresponds to the function of the interrupt receiving unit 11, the priority encoder 22 corresponds to the function of the priority encoder unit 12, the latch circuits 23, 24 and 25, and the driver 29 include the interrupt factor latch register unit 13 and the interrupt ID holding unit. 14 and the interrupt detection unit 15. The driver 26 corresponds to the function of the interrupt transmitting unit 16, the dual port RAM 27 corresponds to the function of the interrupt destination selecting unit 17, and the state monitoring unit 28 is the state monitoring unit 18.
It corresponds to the function of.

[0022] The slave unit 2 ₁ to 2 _m, when a cause of interrupt processing (interrupt level) 3, and sends an interrupt request signal INTRQ1~INTRQ3 indicating each interrupt level from each slave unit 2 ₁ to 2 _m signal line is connected wired slave unit 2 ₁ to 2 _m may send an interrupt request at any time.

The receiver 21 of the interrupt arbitration circuit 5 causes the interrupt request signal I from the slave units 2 ₁ to 2 _m.
A signal INT that receives NTRQ1 to INTRQ3 and encodes it by the priority encoder 22 and represents the signal line number (interrupt level) at that time by a binary number.
Output as ID0 and INTID1. When the interrupt request signal is "0" (low level "L") indicating that none is present, the signals INTID0 and INTID1 (interrupt I
Both D) are set to "0". Further, in the case of "1" (high level "H") (asserted) indicating that there is an interrupt request by a plurality of interrupt request signal lines, the priority encoder 22 encodes and outputs the one with the highest interrupt level.

The latch circuit 23 includes inverters G2 and G2.
3 and the gate circuits G6 and G7 of the NAND gate,
The latch circuit 25 has a configuration including an inverter G4 and NAND gate gate circuits G9 and G10 each having an inverting input NAND gate gate circuit G8.

When the control terminal G receives the signal "0" from the inverter G1, the latch circuit 24 is in a through state in which the input signal is output as it is. Further, when the signal from the inverter G1 becomes "1", the latch state is maintained in which the output signal up to that point is held. Also, the latch circuit 25 is
When the output signal of the gate circuit G5 becomes "0", the output signal Q becomes "1", and when the interrupt factor read request signal INTRR from the processor unit becomes "1", the output signal Q returns to "0". In the initial state, this output signal Q
Is a state of "0".

Therefore, when any one of the interrupt request signals INTRQ1 to INTRQ3 from the slave unit becomes "1" (even when the interrupt level is the lowest),
Since either of the output signals of the priority encoder 22 becomes "1", the output signal Q of the latch circuit 25 becomes "1", and at that time, the interrupt factor read request signal IN
Since TRR is "0", the output signal of the inverter G1 becomes "1", and the latch circuit 24 transits from the through state to the latch state.

[0027] The status monitoring unit 28 is input with the processor unit ₁ 1 to 1 ₈ Implemented signal INS1~INS8 and fault presence signals ALM1~ALM8 is, the signal indicating the processor unit without failure there implementation IE1 ~ I
Outputs E8. The dual port RAM 27 reads one of the interrupt request signals INT1 to INT8 by using the signals IE1 to IE8 and the latch output signals INTID0 and INTID1 of the latch circuit 24 as an address, and sends it out from the driver 26 to the processor unit. .
That is, at this time, the output signal Q of the latch circuit 25 of "1" is input to the output enable terminal OE of the driver 26.

The dual port RAM 27 has ports A and B, writes data including a state in which an interrupt request can be accepted from the processor unit via the global bus 4, and reads an interrupt request signal from the port A. This dual port RAM 27 can output the signals IE1 to IE8, INTID0, I.
It has a function corresponding to a table for selecting a processor unit using NTID1 as an address.
The internal hardware of the interrupt arbitration circuit 5 can update the contents of the dual port RAM 27. Further, the dual port RAM 27 is provided with signals INS1 to INS8 indicating whether or not the processor unit has been mounted.
It is also possible to include the signals ALM1 to ALM8 indicating the presence or absence of a fault as an address signal, and to make the stored contents including the function of the state monitoring unit 28.

When the output signal Q of the latch circuit 25 applied to the enable terminal OE of the driver 26 becomes "1", the driver 26 is enabled and the interrupt request signal INT1 read from the dual port RAM 27.
~ Any one of INT8 is a processor unit 1 ₁ to 1
₈ is selected, and the processor unit designated by this interrupt request signal acquires the global bus 4 and then sets the interrupt factor read request signal INTRR to "1". This interrupt factor read request signal INTR
Since R is applied to the enable terminal OE of the driver 29, the driver 29 is enabled and the signals INTID0 and INTID latched by the latch circuit 24 are set.
1 is sent to the processor unit via the global bus 4.

The processor unit uses this signal INTI.
Based on D0 and INTID1, the slave unit of the interrupt request source is identified, the interrupt factor is specified, and if necessary, the contents of the dual port RAM 27 are updated to indicate that interrupt processing is in progress, Clear the interrupt factor holding unit 2a (see Fig. 1) of the unit,
Start the actual interrupt processing. Further, the latch circuit 24 transits to the through state in response to the interrupt factor read request signal INTRR of "1" from the processor unit, and when the interrupt factor read request signal INTRR becomes "0", the next interrupt request acceptance wait state is set. Become. At this time, if another interrupt request exists, the latch circuit 24 transits to the through state and the latch contents are once cleared. Therefore, when the interrupt factor read request signal INTRR returns to "0",
The next interrupt request can be accepted immediately.

FIG. 3 is an explanatory diagram of the second embodiment of the present invention. The same reference numerals as those in FIG. 1 denote the same parts, 31 is an interrupt receiving section, 32 is a priority encoder section, and 33.
Is an interrupt factor latch register, 34 is an interrupt ID
A holding unit, 35 is an interrupt detection unit, 36 is an interrupt transmission unit, 37 is a decoder, 38 is a state monitoring unit, 39 is a counter, and 40 is a determiner.

In the interrupt arbitration circuit 5, the interrupt receiving unit 31, the priority encoding unit 32, the interrupt factor latch register unit 33, the interrupt ID holding unit 34, and the interrupt detecting unit 35 are shown in FIG. It has the same function as the function of each unit having the same name, and the duplicate description with FIG. 1 is omitted. In addition, the function of the interrupt destination selection unit 17 in FIG.
The case where it is realized by 0 and 0 is shown.

The counter 39 has an interrupt detector 35.
The count signal is counted up by the detection signal that detects the occurrence of a new interrupt from the and the determination signal from the determination device 40. Further, the state monitoring unit 38 is provided in the processor unit 1 ₁
.About.1 _n are numbered in ascending order to form the processor unit ID, and the ID of this processor unit and the count value of the counter 39 are compared in the determiner 40, and the ID of the processor unit that matches the count value If it exists, the count value at that time is decoded by the decoder 37, the processor unit of the ID having the compared and matched ID is selected as the interrupt destination in the judging device 40, and is transmitted from the interrupt transmitting unit 36.

Further, in the case of comparison disagreement in the judging device 40,
Since the processor unit indicated by the count value of the counter 39 indicates the state of no mounting or the state of failure, the counter 39 is counted up by the determination output signal of the determiner 40. Therefore, it is possible to skip the processor unit that is not mounted or has a fault and select the next processor unit as the interrupt destination.

FIG. 4 is an explanatory diagram of the interrupt arbitration circuit according to the second embodiment of the present invention. The same reference numerals as those in FIGS. 2 and 3 denote the same parts, 41 is a receiver, 42 is a priority encoder, 43, 44 and 45 are latch circuits, 46 is a driver, 47 is a 3to8 decoder, 48 is a state monitor, 49 is a 3-bit counter, 50 is a determiner, 51 is a driver, 52 is a falling differential circuit, and G11 and G12 are gate circuits. Show. Similar to FIG. 2, the case where _eight processor units 1 ₁ to ₁₈ are provided is shown.

The receiver 41, the priority encoder 42, the latch circuits 43, 44 and 45, and the driver 5
1 has the same function as the part with the same name in FIG. 2, and the duplicated description will be omitted. Also, in order to select the processor units 1 ₁ to ₁₈ as interrupt destinations, 3
A bit counter 49 and a 3 to 8 decoder 47 are provided, and in FIG. 3, a case is shown in which the count value of the counter 49 and the ID of the processor unit from the state monitor 48 are input to the determiner 40. In the embodiment, the signals IE1 to IE8 from the state monitoring unit 48 indicating the mounted processor unit and the faultless processor unit, and 3to.
The decoding output signal of the 8-decoder 47 is input to the AND gate that constitutes the determiner 50, and the coincidence signal is input to the gate circuit G11 via the OR gate.

The output signal Q of the latch circuit 45 is "0" in the initial state and becomes "1" when a new interrupt request is generated. The 3-bit counter 49 has terminals G1 and
It counts up when any of the input signals of G2 becomes "1". Further, the falling differentiating circuit 52 is provided when the output signal Q of the latch circuit 45 falls from "1" to "0".
Input "1" to the terminal G1 of 9 to count up. That is, the count is incremented each time an interrupt is detected. When the output signal Q of the latch circuit 45 is "1" and the output signal of the determiner 50 is "0", the output signal of the gate circuit G12 input to the terminal G2 of the counter 49 becomes "1",
Count up. That is, when the output signals INTP1 to INTP8 of the decoder 47 and the output signals IE1 to IE8 of the state monitor 48 are input to the determiner 50 and there is no coincidence signal by the AND gate, the processor units ₁₁ to.
This is the case where a processor unit without mounting or with a fault is selected from 1 _8. Therefore, the counter 49 is counted up and the next processor unit is selected.

Further, the output signal of the judging device 50 becomes "1",
When the output signal Q of the latch circuit 45 becomes "1", the output signal of the gate circuit G11 becomes "1", and the driver 4
Since it is input to the enable terminal OE of the driver 6, the driver 4
6 is enabled, and one of the interrupt request signals INT1 to INT8 corresponding to the output signals INTP1 to INTP8 of the 3to8 decoder 47 is sent out. Therefore, it is possible to sequentially select and send the interrupt requests only to the processor units that are mounted and can accept the interrupts without any trouble.

FIG. 5 is an explanatory view of the third embodiment of the present invention. The same reference numerals as those in FIGS. 1 and 3 denote the same parts, and 6
1 is an interrupt receiving unit, 62 is a priority encoder unit, 63 is an interrupt factor latch register unit, 64 is an interrupt ID holding unit, 65 is an interrupt detecting unit, 66 is an interrupt transmitting unit, 67 is a decoder, 68 is a state monitoring unit, 69 Is an interrupt destination selection unit, 70 is a determiner, 71 is a selector, 7
Reference numeral 2 represents an alternative destination generation unit.

In the interrupt arbitration circuit 5, the interrupt receiving unit 61, the priority encoding unit 62, the interrupt factor latch register unit 63, the interrupt ID holding unit 64, and the interrupt detecting unit 65 are shown in FIGS. The same functions as those of the respective parts having the same names in FIG. Further, the configuration including the decoder 67, the interrupt destination selecting unit 69, the judging unit 70, the selector 71, and the alternative destination generating unit 72 selects the alternative destination when a processor unit having a failure is selected as the interrupt destination. It was made possible.

As described above, the state monitor 68 monitors the presence / absence of a processor unit and the presence / absence of a fault, and determines the ID of the processor unit with and without a fault by the determiner 7.
0 and the alternative destination generation unit 72. Based on the interrupt ID held in the interrupt ID holding unit 64, the interrupt destination selecting unit 69 selects the processor unit ID for sending the interrupt request based on the interrupt detection signal, and the judging unit 7
0 and the selector 71. In the judging device 70, the ID of the processor unit with the mounted and no fault from the state monitoring unit 68 is compared with the ID of the processor unit from the interrupt destination selecting unit 69, and if there is a comparison match, the selector 71 To input the ID of the processor unit from the interrupt destination selection unit 69 to the decoder 67 as the interrupt destination.

In the case of a comparison mismatch in the judging device 70, the selector 71 and the alternative destination generating unit 72 are controlled, and the alternative destination generating unit 72 is provided from the state monitoring unit 68, and the processor unit of the processor unit with no fault is mounted. One of the IDs is selected and input to the decoder 67 via the selector 71. Therefore, when the processor units are sequentially selected by the interrupt destination selection unit 69 and the processor units are not mounted or have a failure, the alternative destination generation unit 72 is determined by the determination of the determination unit 70.
It is possible to input the ID of the alternative processor unit, which is generated in the above, to the decoder 67 via the selector 71. Then, the decoder 67 designates a processor unit that is decoded and sends an interrupt request, and the interrupt transmission unit 66 sends the interrupt request.

Further, the alternative destination generation unit 72 is an ID of the processor unit which is mounted and has no fault from the state monitoring unit 68.
Based on the signal of comparison disagreement from the determination unit 70,
For example, it is possible to adopt a configuration of sequentially selecting and outputting.

FIG. 6 is an explanatory diagram of the interrupt arbitration circuit according to the third embodiment of the present invention. The same reference numerals as those in FIGS. 2 and 5 denote the same parts, 81 is a receiver, 82 is a priority encoder, 83, 84 and 85 are latch circuits, 86 is a driver, 87 is a 3to8 decoder, 88 is a state monitoring unit, 89 is a 3 bit counter, 90 is a determiner, 91 is a selector, 92 is a determiner, 93 is a dual port RAM,
Reference numeral 94 indicates a driver, and G13 to G17 indicate gate circuits.

The receiver 81, the priority encoder 82, the latch circuits 83, 84 and 85, and the driver 9
4 has the same function as the part having the same name in FIG. 2, and the 3 bit counter 89, the 3to8 decoder 87 and the judging device 90 have the same function as the part having the same name in FIG. However, the description will not be repeated.

Unlike the dual port RAM 27 shown in FIG. 2, the dual port RAM 93 does not input the information output by the state monitoring unit 88 as an address, and therefore can output the ID of a processor unit that cannot accept an interrupt. Includes sex. Therefore, IE1 to IE1 corresponding to the ID of the processor unit that has read the interrupt ID from the latch circuit 84 as the read address and the ID of the processor unit that can accept the interrupt from the state monitoring unit 88.
IE8 is input to the determiner 92. The output signal SEL of the determiner 92 is the selector 91 and the gate circuits G13, G.
14 and are input. The selector 91 selects the port A when the signal SEL is "1" and the port B when the signal SEL is "0".
Select.

That is, the ID of the processor unit read from the dual port RAM 93 using the interrupt ID latched by the latch circuit 84 as an address is the state monitoring unit 8
When the interrupt can be accepted by 8, the selector 91 selectively outputs the processor unit ID, and when the interrupt cannot be accepted, the selector 91 selectively outputs one of the decode output signals INTP1 to INTP8 of the 3to8 decoder 87. Further, when the output signal SEL of the determiner 92 is "0" and the output signal Q of the latch circuit 85 becomes "1" due to interrupt detection, the output signal of the gate circuit G14 is also "1".
Then, the falling differential circuit 95 detects the falling of this signal from "1" to "0" and counts up the 3-bit counter 89. Also, the output signal of the determiner 90 is "0".
In this case, when the output signal Q of the above-mentioned latch circuit 85 becomes "1", the output signal of the gate circuit G15 becomes "1",
The 3-bit counter 89 is counted up.

When the output signal Q of the latch circuit 85 becomes "1" and the output signal IQ1 of the gate circuit G13 becomes "1", the driver 86 is enabled via the gate circuit G16 (OR gate). When the output signal IQ2 of the gate circuit G14 becomes "1" and the output signal of the determiner 90 becomes "1", the output signal of the gate circuit G17 (AND gate) becomes "1" and the driver 86 is enabled. Become. Therefore, even if an interrupt request is issued to a processor unit that cannot accept an interrupt, another processor unit that can accept an interrupt can be replaced in order.

FIG. 7 is an explanatory diagram of the fourth embodiment of the present invention, in which the same reference numerals as those in the above-mentioned respective embodiments indicate the same parts, 101 is an interrupt receiving unit, and 102 is an interrupt. A selection unit, 103 is an interrupt reception factor latch register, 104 is a priority encoder unit, 105 is an interrupt ID holding unit, 106 is an interrupt detection unit, and 107 is an interrupt detection unit.
Is an interrupt transmission unit, 108 is a decoder unit, 109 is a counter, 110 is an OR circuit (OR), 111 is a state monitoring unit, and 112 is a processor unit built-in control unit.

The interrupt selecting unit 10 receives the interrupt signal from the slave unit received by the interrupt receiving unit 101.
2, and the interrupt selection unit 102 notifies the priority encoder unit 104 of only the interrupt signal designated by the processor unit. The priority encoder unit 104, the interrupt reception factor latch register unit 103, the interrupt ID holding unit 105, and the interrupt detection unit 106 perform the same operations as the units having the same names in each of the above-described embodiments. is there.

The state monitoring unit 111 has the same function as the state monitoring unit in each of the above-mentioned embodiments, and the processor unit built-in control unit 112 has a processor unit number for constructing a multiprocessor system. And the interrupt destination processor unit designated by the counter 109 based on the signal from the status monitoring unit 111 indicating that the interrupt destination is installed in the system and there is no fault, the decoder 108 decodes the interrupt destination processor unit And the interrupt request is sent from the interrupt transmitter 107. If the interrupt destination processor unit designated by the counter 109 is in a faulty state, the counter 109 is caused to count up the signal from the processor unit built-in control unit 112 via the OR circuit 110, and the next processor unit Will be specified as the interrupt destination. Therefore, it is possible to control so as not to send an interrupt request to a processor unit that is in an unmounted state or has a failure.

FIG. 8 is an explanatory view of the fifth embodiment of the present invention, in which the same reference numerals as those in FIG. 7 denote the same parts, and 5a and 5b.
Indicates an interrupt arbitration circuit. That is, the case where two interrupt arbitration circuits 5 in FIG. 7 are provided is shown. Note that more interrupt arbitration circuits can be provided. Then, with respect to one processor unit, the processor unit built-in control unit 112 and the interrupt selection unit 102 are configured so that the interrupt notification is performed only from one interrupt arbitration circuit.
Set the processor unit number to and. As a result, the interrupt arbitration circuits 5a and 5b can independently perform interrupt arbitration.

The processor unit also includes a processor unit built-in control unit 11 of the interrupt arbitration circuits 5a and 5b.
The number of processor units set to 2 is monitored, and the setting of a new processor unit for the processor unit built-in control unit 112 is adjusted so that the number of processor units in charge of each interrupt arbitration circuit does not change significantly from the initial value. . Further, the load state of the processor unit in charge of each interrupt arbitration circuit is monitored, and when the load of the processor unit in charge of a certain interrupt arbitration circuit is high and the load of the processor unit in charge of another interrupt arbitration circuit is low, Change the processor unit with a low load to the interrupt arbitration circuit that handles the processor unit with a high load. That is, the setting of the processor unit of the processor unit built-in control unit 112 is updated. As a result, the loads of the processor units can be balanced, and the processing performance of the entire system can be improved.

FIG. 9 shows a flow chart of the fifth embodiment of the present invention, in which the processings handled by a plurality of interrupt arbitration circuits are A, B, C, ... And the number of processor units in charge of the interrupt arbitration circuits. NA, NB, NC, ...
And the initial values are NA _TYP , NB _TYP , NC _TYP ,.
・ ・The number of processor units that do not belong to any interrupt arbitration circuit is NS. The load factor of the processor unit group belonging to the interrupt arbitration circuit is set to LFA, L.
FB, LFC. .., LFA _MAX (NA), LFB _MAX (NB), LFC _MAX
(NC), ..., For the number of units in charge of each processor unit group, LFA _MIN (NA)
LFB _MIN (NB), LFC _MIN (NC), ...

In FIG. 9, only the process A is shown, but the same applies to the other processes B, C, ... The processor unit monitors the content of the processor unit built-in control unit 112 (see FIG. 8) and determines whether the number of processor units has decreased from the initial value due to a failure of the processor unit or the like (a1). That is, it is determined whether NA <NA _TYP . If it has not decreased from the initial value NA _TYP, proceed to step (a4). If it has decreased, go to step (a4).
Go to 2).

In step (a2), the number NS of processor units that do not belong to any interrupt arbitration circuit
Is 1 or more, that is, whether or not a processor unit as a spare is present. If it is not 1 or more, the process proceeds to step (a4). If it is 1 or more, the process proceeds to step (a
Go to 3). In this step (a3), N
As shown by A-1 (ALM) → NA, the uninterruptible processor unit is excluded due to a failure or the like, and NA
As shown by +1 (NS) → NA, a spare processor unit is incorporated, and the process proceeds to step (a1).

In step (a4), the LFA
(T) ≧ LFA_MAXProcess A, shown as (NA)
Load factor LFA (t) and maximum load factor LFA_MAX(NA)
If there is enough processing performance,
Judgment on similar load factors for B, C, ...
I do. Judgment result in this step (a4), processing
If there is no more margin in performance, check the load factor of Process B.
LFB (t) ≦ LFB _MIN(NB) is judged
(A5), the load factor of process B is one processor unit
If there is no room due to the decrease, the same procedure is performed.
The load factor of Process C is determined (a10). Also in this case
When there is no room, the load factor of process D
To judge.

In step (a5), if the load factor has a margin, the process B is performed as indicated by NB-1 → NB.
The number of processor units of process A is reduced and the number of processor units of process A is increased as indicated by NA + 1 → NA (a6). Then, it is determined whether or not the load factor has a margin even if the processor unit of the process A decreases (a7). If there is no margin, the timer is started (a9), and after a predetermined time, the step (a7) again. Then, it is determined whether or not the load factor has a margin. By repeating this, when the load factor has a margin, the processor unit of the process A increased in step (a6) is decreased (a8). Then, the process proceeds to step (a1).

In step (a10), if the load factor of the process C has a margin, steps (a6) to (a8).
Steps (a11) to (a13) similar to the above are executed.
When there is no margin in the load factor of the processes B and C, the load factor of the next process D (not shown) is determined.

FIG. 10 is an explanatory view of the sixth embodiment of the present invention, in which 1 ₁ to 1 _n are processor units and 2 ₁ to 2 are shown.
_m is a slave unit, 3 is a common memory, 4 is a global bus, 5 is an interrupt arbitration circuit, 121 is an interrupt receiving unit, 122 is a priority encoder unit, 123 is an interrupt factor latch register unit, 131 is a CPU unit, 13
Reference numeral 2 is a setting register, 133 is a mask timer, and 134 is an interrupt mask.

[0061] CPU section 131 and the set register 132 and the mask timer 133 and interrupt mask 134, showing the configuration of the main part of the processor unit ₁ 1 to 1 _n, also interrupt arbitration circuit 5, an interrupt request from the slave unit The interrupt reception unit 121 receives it, the priority encoder unit 122 encodes it for each priority of interrupts, holds the interrupt ID in the interrupt ID holding unit 124, and sends the interrupt notification to the processor units 1 ₁ to 1 _n.
Broadcast notification to.

By the broadcast notification, the processor unit which acquired the global bus 4 earliest accesses the interrupt factor latch register section 123 to queue the processing task according to the interrupt factor, and clears the interrupt factor on the slave unit side. Then, the global bus 4 is released. In this case, the processor unit that has acquired the second global bus 4 cannot read the interrupt factor, so the process is completed as an empty interrupt process.

Further, the processor unit is controlled by the CPU unit 131 corresponding to the core unit to set the setting register 132.
, The mask time and the interrupt mask are set, and the mask time from the start to the stop of the queued task is set by the mask timer 133 accordingly.
It controls an interrupt mask 134 that masks interrupts with lower levels than the queued tasks. For setting the interrupt mask, either a method of setting the start and end of the mask timing or a method of setting only the start of the mask timing can be applied by software.

FIG. 11 is a diagram for explaining the processing sequence of the above-described sixth embodiment of the present invention, in which the processor unit 1 ₁ executing task A and the processor unit 1 ₂ executing task C are broadcast. If by the interruption reception, respectively start handler performs the acquisition of the global bus 4 for processing the cause register read, the processor unit 1 ₁ to acquire the global bus 4 above, the interrupt from the interrupt factor latch register section 13 The factor is read, the interrupt factor of the slave unit and the interrupt factor latch register unit 13 are cleared, the interrupt factor is queued (task B), and the handler is stopped.

When the task A ends, the processing of the queued task B is started, the mask start is written in the setting register 132, the interrupt mask 134 is set, and the processing of the task B is performed. The one processor unit 1 ₁ is masked by the interrupt mask 134. In contrast, the other processor unit 1 _2, the interrupt is not in a mask to perform the interrupt processing, even if the task D start, start the handler will make a reading of the interrupt source.

Therefore, the processor unit having a lighter load among the plurality of processor units executes the interrupt processing, and the interrupt mask is set during the interrupt processing so that the other processor units can perform the interrupt processing. Will be executed. Therefore, the processing performance of the entire system can be improved.

FIG. 12 is an explanatory diagram of an interrupt arbitration circuit and a processor unit according to the sixth embodiment of the present invention.
1 ₁ to 1 _n are processor units, 2 ₁ to 2 _m are slave units, 3 is a common memory, 4 is a global bus, 5
Is an interrupt arbitration circuit, 141 is a receiver, 142 is a priority encoder, 143 and 144 are latch circuits,
145 and 146 are drivers, 151 is a processor core of a processor unit, 152 is a control register,
153 is a timer, 154 is a comparator, 155 is a mask register, G31 to G38 are gate circuits, and G31 to
G33 is an inverter, G34 and G35 are NAND gates,
G36 and G38 are OR gates, and G37 is an AND gate.

In comparison with the configuration of FIG. 10, the receiver 14
1 is the interrupt receiving unit 121, the driver 146 and the latch circuit 143 are the interrupt factor latch register unit 123,
The priority encoder 142 and the driver 145 are connected to the priority encoder unit 122 by the latch circuit 14.
The function 4 corresponds to the interrupt ID holding unit 124. In addition, the program core 151 of the processor unit is C
In the PU unit 131, the control register 152 is the setting register 132, the timer 153 is the mask timer 133.
In addition, the mask register 155 has a function corresponding to the interrupt mask 134, and the portion excluding the processor core 151 constitutes an interrupt mask circuit.

Further, the receiver 141, the priority encoder 142, the latch circuits 143 and 144, and the driver 14
6, the receiver 21, the priority encoder 22, and the latch circuits 23 and 24 in FIG.
It is similar to the function of the driver 29 and the interrupt request signal INTRQ1~I from the slave unit 2 ₁ to 2 _m
The signals INTID0 and INTI received by the receiver 141 of NTRQ3, encoded by the priority encoder 142, and latched by the latch circuit 144.
D1 is input to the drivers 145 and 146 and the OR gate G36.

At this time, since the output signal of the inverter G33 is "1", the driver 145 is in the enabled state, the output signal of the OR gate G36 and the latch circuit 144.
Request signal INTX, INT depending on the output signal of
Connect C0 and INTC1 to all processor units 1 ₁ to 1 _n
Send to.

The comparators 154 of the processor units 1 ₁ to 1 _n compare the signals input to the input terminals A and B, and output "1" to the output terminals when A> B. When the mask register 155 is cleared, "0" is input to the input terminal of the comparator 154 and the output terminal of the comparator 154 becomes "1". Therefore, the interrupt request signal INTX is transmitted via the AND gate G37,
It is input to the interrupt terminal INT of the processor core 151.

When the processor core 151 acquires the global bus 4 in response to this interrupt request, it sends out the interrupt factor read request signal INTRR. As a result, the interrupt factor of the slave unit that has sent the interrupt request is cleared, and the driver 146 of the interrupt arbitration circuit 5 is cleared.
Is enabled, and INTID0 and INTID1 latched by the latch circuit 144 are sent out and input to the comparator 154 and the mask register 155. The output signal of the inverter G33 of the interrupt arbitration circuit 5 becomes "0", and the transmission of the interrupt request signal from the driver 145 is stopped.

Further, the processor core 151 sets the control data in the control register 152, and the timer 153
Is started, and the mask register 153 receives the signal INTC read by the interrupt factor read request signal INTRR.
0 and INTC1 are set, and the set contents are input to the input terminal of the converter 154. This signal INTC
Since 0 and INTC1 correspond to interrupt levels, interrupt requests below the previous interrupt level are masked until the mask register 153 is cleared. When the timer 153 times out, the clear terminal CL of the mask register 155 is passed through the OR gate G38.
Enter "1" in R to clear. Alternatively, the mask register 155 can be cleared via the control register 152 upon completion of the interrupt processing in the processor core 151.

FIG. 13 is an explanatory diagram of the seventh embodiment of the present invention. The same reference numerals as those in FIGS. 1 and 10 denote the same parts, 161 is an interrupt receiving unit, 162 is a priority encoder unit, and 163 is an interrupt. A factor latch register unit, 164 is an interrupt transmission unit, 165 is an interrupt destination selection unit, 166 is a load state monitoring unit, 171 is a CPU unit, 17
2 is an idle task counter, 173 is a fixed timer, 1
Reference numeral 74 denotes a processing load information notification unit.

[0075] The processor unit ₁ 1 to 1 _n are those each comprising the structure shown in the processor unit 1 _1, C
The idle task counter 172 of the PU unit 171 is cleared by the fixed timer 173 at regular time intervals, and the idle tasks are counted up. Therefore, the count value of the idle task counter 172 at regular time intervals can be used as the processing load information. It is also possible to form the processing load information by other means. This processing load information is
The processing load information notification unit 174 sends the processing load information notification unit 174 to the load information monitoring unit 166 of the interrupt arbitration circuit 5.

The load information monitoring unit 166 is similar to the function of the state monitoring unit in the above-described embodiment, and can collect the processing load information about the processor unit with the installed and without the failure. Then, the collected processing load information of the processor units 1 ₁ to 1 _n is transferred to the interrupt destination selecting unit 165. Further, the operations of the interrupt receiving unit 161, the priority encoder unit 162, and the interrupt factor latch register unit 163 are the same as those in the above-mentioned respective embodiments, and the duplicated description will be omitted. The priority encoder unit 162 performs encoding according to the priority of interrupt factors, and notifies the interrupt destination selection unit 165. The interrupt destination selection unit 165 is the load state monitoring unit 1
Based on the processing load information of the processor units 1 ₁ to 1 _n from 66, a processor unit with a low processing load is selected as an interrupt destination, and the interrupt transmission unit 164 sends an interrupt request to the interrupt destination processor unit. Therefore, it is possible to select a processor unit with a low load factor as well as to be mounted and without a failure to perform an interrupt.

FIG. 14 is an explanatory diagram of an interrupt arbitration circuit according to the seventh embodiment of the present invention. The same reference numerals as those in FIG. 13 described above indicate the same parts, 181 is a receiver, 182 is a priority encoder, and 183, 184. , 185 are latch circuits, 186, 195 are drivers, 187 is a decoder,
188 is a register, 189 is a counter, 190 is a clock generator, 191 is a comparator, 192 is a register,
Reference numeral 193 is a comparator, 194 is a decoder, 201 is a processor core, and 202 is a load index register.

The receiver 181, the priority encoder 182, and the latch circuit 183 of the interrupt arbitration circuit 5.
For the 184, 185 and the driver 186, for example, the receiver 81, the priority encoder 82, the latch circuits 83, 84, 85 and the driver 86 in FIG.
Since it has the same function as, the duplicated description will be omitted.

The load index registers 202 of the processor units 1 ₁ to 1 _n are the processing load information notification units 174 of FIG.
The interrupt arbitration circuit 5 is connected via the load information management bus. Further, the counter 189 counts up the clock signal from the clock generator 190, inputs the count value to the register 188 and the decoder 194, and the decoder 194 sequentially decodes and loads one of the load information request signals LDRR1 to LDRRn. It is sent to the processor unit via the information management bus. The processor unit receives the load information request signals LDRR1 to LDRR.
The processing load information set in the load index register 202 according to RRn is transferred to the comparator 1 via the load information management bus.
93 and register 192. That is, counter 1
By 89, it is possible to sequentially select all the processor units in the system and collect the processing load information.

The comparator 193 inputs the current processing load information into the input terminal A and the processing load information stored in the register 192 into the input terminal B, and outputs an output signal of "1" when the condition of A <B is satisfied. ", The processing load information at that time is stored in the register 193, and the count value of the counter 189 at that time is stored in the register 188. Therefore,
The register 192 stores the smallest processing load information, and the number indicating the processor unit in the state of the smallest processing load is stored in the register 188. The decoder 187 decodes it to specify the interrupt destination. The interrupt request can be sent from the driver 186.

Further, the count value of the counter 189 and the value set in the register 188 are compared by the comparator 191, and if the comparison is coincident, the processing load information at that time is stored in the register 192. That is, the previous minimum processing load information is cleared, new processing load information is stored, and then the processor unit is interrupted by the count value of the counter 189 when processing load information smaller than this processing load information is collected. Selected first. Therefore, the processor units having a small processing load are sequentially selected as the interrupt request destinations, and the processing capacity of the entire system can be improved.

FIG. 15 is an explanatory view of a main part of a processor unit according to the seventh embodiment of the present invention, in which 211 is a processor core, 212 is a down counter, 213 is a register,
Reference numeral 214 is a buffer, and 215 is a timer. The processor core 211 applies a count pulse to the down counter 212 at the start of the idle task. The timer 215 is
The down counter 212 is added to the register 213 at regular time intervals.
The count value of is set and the down counter 212 is cleared. The more idle tasks are activated within a certain time, the smaller the value set in the register 213. That is, the processing load is small. Then, the buffer 214 sends the content of the register 213 as processing load information via the load information management bus in accordance with a request signal from the interrupt arbitration circuit.

The present invention is not limited to the above-mentioned respective embodiments, but various additions and modifications can be made, and the function of each part of the interrupt arbitration circuit can be realized by the processing function of the processor. It is possible.

(Supplementary Note 1) A multiprocessor system in which a plurality of processor units, a plurality of slave units, and a common memory are connected via a global bus, and interrupt processing in the processor units is performed according to an interrupt request from the slave units. In the above, an interrupt arbitration circuit that receives an interrupt request from the slave unit and sends an interrupt request to the processor unit is provided, and the interrupt arbitration circuit collects status information of the plurality of processor units. A multiprocessor system comprising: a processor unit mounted by the state monitoring unit and having no fault as an interrupt destination for transmitting an interrupt request from the slave unit. (Supplementary Note 2) The supplementary destination selecting unit is configured by a memory that reads out the interruption destination using the status monitoring unit and the priority encoder output signal of the interrupt request from the slave unit as an address. Multiprocessor system. (Supplementary Note 3) The interrupt arbitration circuit stores a status monitoring unit that collects status information of the plurality of processor units, a counter that receives and detects an interrupt request from the slave unit and counts up, and a count value of the counter. A decoder that is selected as an interrupt destination processor unit, and a determiner that counts up the counter by determining that the count value of the counter specifies a processor unit that is not mounted or has a failure in the state monitoring unit. The multiprocessor system according to appendix 1, further comprising:

(Supplementary Note 4) The interrupt arbitration circuit includes a status monitoring unit for collecting status information of the plurality of processor units, and an interrupt destination selecting unit for detecting an interrupt request from the slave unit and selecting an interrupt destination. When,
A determination unit that compares and determines the interrupt destination processor unit selected by the interrupt destination selection unit and the state information of the processor unit of the state monitoring unit, and whether the interrupt destination processor unit selected by the determination unit is not mounted or has a failure The multiprocessor system according to appendix 1, further comprising an alternative destination generation unit that specifies an alternative destination processor unit. (Supplementary Note 5) The interrupt arbitration circuit stores a status monitoring unit that collects status information of the plurality of processor units, a counter that detects and counts up an interrupt request from the slave unit, and a count value of the counter. The decoder selected as the processor unit of the interrupt destination, the processor unit built-in control unit for writing the implementation from the processor unit, and the processor unit stored in the processor unit built-in control unit according to the count value of the counter, 5. The multiprocessor system according to appendix 4, further comprising: a configuration in which the counter is incremented in the unmounted state or the faulted state based on the state information collected by the state monitoring unit. (Supplementary Note 6) The interrupt arbitration circuit includes a load state monitoring unit that collects processing load information of the plurality of processor units, and an interrupt destination selection unit that detects an interrupt request from the slave unit and selects an interrupt destination. 2. The multiprocessor system according to appendix 1, wherein the interrupt destination selecting unit has a configuration for selecting a processor unit having a low processing load collected by the load state monitoring unit as an interrupt destination. (Supplementary Note 7) The interrupt arbitration circuit sets a register for setting the lowest processing load information during a cycle of designating the plurality of processor units and a processor unit that has transmitted the processing load information set in the register as an interrupt request destination. 7. The multiprocessor system according to appendix 6, characterized in that the multiprocessor system is selected as

(Supplementary Note 8) A multiprocessor system in which a plurality of processor units, a plurality of slave units, and a common memory are connected via a global bus, and interrupt processing in the processor units is performed according to an interrupt request from the slave units. In the above, a plurality of interrupt arbitration circuits for receiving an interrupt request from the slave unit and sending the interrupt request to the processor unit are provided, and each interrupt arbitration circuit collects status information of the processor unit in charge and monitors the status. Department,
A multiprocessor system comprising: an interrupt destination selecting unit for selecting a processor unit in charge, which is mounted by the state monitoring unit and has no fault, as an interrupt destination for transmitting an interrupt request from the slave unit. (Supplementary note 9) In the interrupt arbitration circuit, when the number of processor units mounted by the state monitoring unit and having no fault decreases from the initial value, it is possible to change the allocation of the processor unit in charge of another interrupt arbitration circuit. 9. The multiprocessor system according to appendix 8, wherein the multiprocessor system is configured to determine whether or not the allocation can be changed, and change the charge for the decreased amount.

(Supplementary Note 10) A multiprocessor system in which a plurality of processor units, a plurality of slave units, and a common memory are connected via a global bus, and interrupt processing in the processor units is performed according to an interrupt request from the slave units. In the above, an interrupt arbitration circuit that receives an interrupt request from the slave unit and sends the interrupt request to the processor unit is provided, and the interrupt arbitration circuit detects an interrupt request from the slave unit and detects all processors. A multiprocessor system having a configuration for sending a broadcast notification to a unit, wherein the processor unit has a configuration for acquiring the global bus according to a notification of an interrupt request and setting an interrupt mask.

[0088]

As described above, according to the present invention, the interrupt arbitration circuit, a plurality of slave units 2 ₁ to 2 _m
The interrupt request from is specified by specifying one or one group of processor units, and at that time, it is possible to select a processor unit with and without a failure. Even if it is changed according to the system scale, it is possible to notify the interrupt to the processor unit that can accept the interrupt. Further, the processor unit during a specific pipeline processing can send the interrupt notification to another processor unit by setting the interrupt unacceptable, so that there is an advantage that the pipeline processing is not interrupted. Further, it is possible to select a processor unit with a low processing load state as an interrupt destination, so that the processing load can be averaged and the processing capacity of the entire system can be improved. When the number of processor units is large, multiple interrupt arbitration circuits are provided and interrupt notification is sent to the processor unit in charge of each, thereby speeding up interrupt processing even in a large-scale multiprocessor system. Can be achieved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an interrupt arbitration circuit according to the first embodiment of this invention.

FIG. 3 is an explanatory diagram of a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of an interrupt arbitration circuit according to a second embodiment of this invention.

FIG. 5 is an explanatory diagram of a third embodiment of the present invention.

FIG. 6 is an explanatory diagram of an interrupt arbitration circuit according to a third embodiment of this invention.

FIG. 7 is an explanatory diagram of a fourth embodiment of the present invention.

FIG. 8 is an explanatory diagram of a fifth embodiment of the present invention.

FIG. 9 is a flow chart of a fifth embodiment of the present invention.

FIG. 10 is an explanatory diagram of the sixth embodiment of the present invention.

FIG. 11 is a sequence explanatory diagram of the sixth embodiment of the present invention.

FIG. 12 is an explanatory diagram of an interrupt arbitration circuit and a processor unit according to a sixth embodiment of this invention.

FIG. 13 is an explanatory diagram of the seventh embodiment of the present invention.

FIG. 14 is an explanatory diagram of an interrupt arbitration circuit according to a seventh embodiment of this invention.

FIG. 15 is an explanatory diagram of a main part of a processor unit according to a seventh embodiment of the present invention.

[Explanation of symbols]

1 ₁ to 1 _n Processor unit 2 ₁ to 2 _m Slave unit 3 Common memory 4 Global bus 5 Interrupt arbitration circuit 11 Interrupt receiving unit 12 Priority encoder unit 13 Interrupt factor latch register unit 14 Interrupt ID holding unit 15 Interrupt detection unit 16 Interrupt transmission Part 17 Interrupt destination selection part 18 Status monitoring part

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5B045 BB28 FF01 FF06 FF11                 5B061 BA02 BB01 CC09 GG13 RR02                       RR05                 5B098 AA10 BB01 BB05 EE01

Claims (5)

[Claims] 1. A multiprocessor system in which a plurality of processor units, a plurality of slave units, and a common memory are connected via a global bus, and interrupt processing in the processor units is performed according to an interrupt request from the slave units. And an interrupt arbitration circuit that receives an interrupt request from the slave unit and sends an interrupt request to the processor unit, wherein the interrupt arbitration circuit includes a state monitoring unit that collects state information of the plurality of processor units, A multiprocessor system comprising: an interrupt destination selecting unit that selects a processor unit that is installed by the state monitoring unit and has no fault as an interrupt destination to which an interrupt request from the slave unit is transmitted. 2. The interrupt arbitration circuit, a status monitoring unit for collecting status information of the plurality of processor units,
A counter for detecting and counting up an interrupt request from the slave unit, a decoder for selecting the count value of the counter as an interrupt destination processor unit, and a counter for which the count value of the counter is not mounted in the state monitoring unit 2. A multiprocessor system according to claim 1, further comprising a judging device which judges that a processor unit having a failure is designated and counts up the counter. 3. The interrupt arbitration circuit, a status monitoring unit for collecting status information of the plurality of processor units,
An interrupt destination selection unit that detects an interrupt request from the slave unit and selects an interrupt destination, and an interrupt destination processor unit selected by the interrupt destination selection unit and status information of the processor unit of the status monitoring unit are compared. The multi-processor according to claim 1, further comprising: a judgment unit for judging, and a substitution destination generation unit for designating a substitution destination processor unit when the interrupt destination processor unit selected by the judgment unit is not mounted or has a failure. Processor system. 4. The interrupt arbitration circuit includes a load state monitoring unit that collects processing load information of the plurality of processor units, and an interrupt destination selection unit that detects an interrupt request from the slave unit and selects an interrupt destination. 2. The multiprocessor system according to claim 1, wherein the interrupt destination selection unit has a configuration for selecting a processor unit having a low processing load collected by the load state monitoring unit as an interrupt destination. 5. A multiprocessor system in which a plurality of processor units, a plurality of slave units, and a common memory are connected via a global bus, and interrupt processing in the processor units is performed according to an interrupt request from the slave units. A plurality of interrupt arbitration circuits that receive interrupt requests from the slave units and send the interrupt requests to the processor units, each interrupt arbitration circuit including a status monitoring unit that collects status information of the processor unit in charge. A multiprocessor system comprising: an interrupt destination selecting unit that selects a processor unit in charge, which is mounted by the state monitoring unit and has no fault, as an interrupt destination to which an interrupt request from the slave unit is transmitted.