JP2003273127A - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device capable of improving a withstand voltage at the periphery of a cell. <P>SOLUTION: An N<SP>-</SP>drift layer 2, a P-type first gate layer 3, and an N<SP>+</SP>source layer 4 are laminated successively on an N<SP>+</SP>SiC substrate 1, and a trench 5 is formed through the source layer 4 and the first gate layer 3 to reach the drift layer 2, and an N-type channel layer 6 is formed on the inner wall of the trench 5, and a P-type second gate layer 7 composed of SiC is formed inside the layer 6. A guard ring structure having the same structures as the trench 5, the channel layer 6, and the second gate layer 7, is formed at the periphery of a cell having the trench 5 formed therein, and members 3a, 3b, 3c, 32 and 42 in the structure corresponding to the first gate layer 3 and the second gate layer 7 are in electrical floating states. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device, and more particularly to a vertical JFET.

[0002]

2. Description of the Related Art A silicon carbide semiconductor device is shown in FIG.
An example of a vertical JFET using a punch structure is shown. In FIG.
And N⁺On top of the SiC SiC substrate 100^-Drift layer 10
1, P ⁺Type first gate layer 102, N⁺Source layer 103
Are sequentially formed, and the source layer 103 and the first gate layer 10 are formed.
Trench 1 having a depth penetrating 2 and reaching the drift layer 101
04 are formed. Also, inside the trench 104
The N-type channel layer 105 and the P-type second gate layer
106 are formed. Cell part formed in this way
A trench 110 is formed in the outer peripheral portion of
The drift layer 101 is exposed by the wrench 110.
The drift layer 101 in the trench 110 has a P-type
The guard ring 111 is formed.

With such a structure, since the channel portion is formed by using the trench 104, the cell can be miniaturized, and electrons can flow linearly from the front surface to the back surface of the wafer to reduce the on-resistance of the transistor. There is an advantage.

However, in FIG. 7 in which a normal guard ring forming technique is applied as a breakdown voltage structure in the outer peripheral portion of the cell portion, there are the following problems. At the boundary (point β in the figure) inside the trench 110 around the chip, the distance L between the first gate layer 102 and the guard ring layer 111.
2 becomes wider than the distance L1 between the first gate layer 102 and the second gate layer 106 in the cell portion (L2>
L1). This causes a problem that the breakdown voltage cannot be secured.

[0005]

SUMMARY OF THE INVENTION The present invention has been made under such a background, and an object thereof is to provide a silicon carbide semiconductor device capable of improving the breakdown voltage at the outer periphery of the cell portion. .

[0006]

According to the invention described in claim 1, each structure of the trench, the first gate layer, the channel layer and the second gate layer in the cell portion is used as it is as a guard ring structure. Therefore, the same breakdown voltage as that of the cell portion can be secured, and the breakdown voltage does not decrease.

According to the second aspect of the invention, the channel layer and the second gate layer in the cell portion are extended and used as a field plate. Therefore, it is possible to form the same impurity concentration as that of the second gate layer of the cell portion and
The total distance of the drift layer and the channel layer when measured from the conductivity type substrate can be made equal (d1 = d in FIG. 1).
2) Therefore, the breakdown voltage does not decrease.

According to the invention of claim 3, claim 1
All the actions and effects of 2 and 3 are obtained, and a higher breakdown voltage can be obtained. According to the invention described in claim 4, the electric field at the end portion of the field plate layer can be relaxed, and the outer peripheral structure having a higher breakdown voltage can be obtained.

According to the fifth aspect of the present invention, breakdown can be caused in the trench portion in the portion between the cell portion and the guard ring structure, which is advantageous in improving surge withstand capability.

According to the sixth aspect of the present invention, the electric field can be relaxed in the side surface of the trench formed in the outer peripheral portion of the cell, which intersects with the upper surface of the drift layer.

According to the invention described in claim 7, since the electric field at the bottom of the trench can be relaxed, a high breakdown voltage can be obtained. According to the method for manufacturing a silicon carbide semiconductor device described in claim 8, the silicon carbide semiconductor device described in claim 1 can be obtained. According to the method for manufacturing a silicon carbide semiconductor device of the ninth aspect, the silicon carbide semiconductor device of the second aspect can be obtained. Furthermore, according to the method for manufacturing a silicon carbide semiconductor device of the tenth aspect, the silicon carbide semiconductor device of the seventh aspect can be obtained. In the method for manufacturing a silicon carbide semiconductor device according to any one of claims 8, 9, and 10, since the outer peripheral structure can be formed at the same time when the cell portion is formed, it is not necessary to add an extra step, so that the cost can be reduced. Can be realized.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a vertical sectional view of a silicon carbide semiconductor device (vertical JFET) according to this embodiment. This device has a first gate (G1) and a second gate (G1) as gates.
2), it is possible to separately apply a voltage to G1 and G2. It also has a trench gate structure.

In FIG. 1, an N ⁻ drift layer 2 made of an epitaxial layer and an S layer are formed on an N ⁺ type SiC substrate 1.
A P ⁺ -type first gate layer 3 made of iC and an N ⁺ -type source layer 4 made of SiC are sequentially stacked. In the present embodiment, the first conductivity type is N type and the second conductivity type is P type.

In the cell portion, a trench 5 penetrating the source layer 4 and the first gate layer 3 and reaching the drift layer 2 is formed. An N-type channel layer 6 made of an epitaxial layer is formed on the inner wall of the trench 5, and a P-type second gate layer 7 made of SiC is provided inside thereof.
Are formed. Since the first gate layer 3 is buried, it is also referred to as a valid gate layer, and the second gate layer 7 is disposed on the top, and therefore is also referred to as a top gate layer.

Further, a nickel film 8 and an aluminum film 9 are formed on the second gate layer 7 as electrode materials.
An oxide film 10 is formed on the source layer 4, and a nickel film 11 and an aluminum film 12 are formed as electrode materials in the openings of the oxide film 10. On the other hand, a part of the source layer 4 is removed to expose the first gate layer 3, and the nickel film 13 and the aluminum film 14 are used as electrode materials in the exposed portion.
And are formed. Further, the drain electrode 15 is formed on the entire back surface (lower surface) of the substrate 1.

By adjusting the voltage between the first gate layer 3 and the second gate layer 7, the spread of the depletion layer in the channel layer 6 can be adjusted to control the current flowing between the source and the drain. it can.

On the other hand, the outer peripheral side of the cell portion in which the trench 5 is formed is a separation portion, a guard ring portion outside thereof, and a field plate portion outside thereof. In the guard ring part, the first guard ring structure on the inner peripheral side (guard ring structure (I) in the figure) and the second guard ring structure on the outer peripheral side (guard ring structure (II) in the figure) Are formed.

First, in the separation part, the source layer 4 and the first
A trench 20 penetrating the gate layer 3 and reaching the drift layer 2. The trench 20 is formed in a ring shape so as to surround the cell portion. An N-type channel layer 21 made of an epitaxial layer is formed on the inner wall of the trench 20, and P made of SiC is formed inside the N-type channel layer 21.
A second gate layer 22 of the mold is formed. Furthermore, a nickel film 23 is formed on the second gate layer 22 as an electrode material.
And an aluminum film 24 are formed.

In the guard ring portion on the outer periphery of the isolation portion, a trench 30 penetrating the source layer 4 and the first gate layer 3 and reaching the drift layer 2 is formed. The trench 30 is formed in a ring shape so as to surround the isolation portion (trench 20). An N-type SiC layer 31 made of an epitaxial layer is formed on the inner wall of the trench 30, and a P-type SiC layer 32 is formed inside the N-type SiC layer 31. Further, on the SiC layer 32, a nickel film 33 and an aluminum film 34 are formed as electrode materials. further,
A trench 40 that penetrates the source layer 4 and the first gate layer 3 and reaches the drift layer 2 is formed on the outer peripheral side of the first guard ring structure. This trench 40
Is formed in a ring shape so as to surround the first guard ring structure (trench 30). An N-type SiC layer 41 made of an epitaxial layer is formed on the inner wall of the trench 40, and a P-type SiC layer 42 is formed inside thereof. Further, on the SiC layer 42, a nickel film 43 and an aluminum film 44 are formed as electrode materials.
In this way, the second guard ring structure is formed.

In the first and second guard ring structures, the P ⁺ layers 3a, 3b and 3c, which are members corresponding to the first gate layer 3 in the cell portion, are in an electrically floating state. There is. In addition, the second gate layer 7 of the cell portion
The P layers 32 and 42 corresponding to the above are also in an electrically floating state.

In the field plate portion (chip end portion), a trench 50 that penetrates the source layer 4 and the first gate layer 3 and reaches the drift layer 2 is formed. The trench 50 is formed in a ring shape over the entire circumference of the chip at the chip end face portion. An N-type SiC layer 51 made of an epitaxial layer is formed on the inner wall of the trench 50, and a P-type SiC layer 52 is formed inside thereof. The stacked body of the SiC layer 51 and the SiC layer 52 extends from the cell portion side along the inner surface of the trench 50 to a part of the bottom surface of the trench. Also, the wiring material 56
The SiC layer 52 is electrically connected to the first gate layer (P ⁺ layer) 3c inside the trench 50. An oxide film 53 is formed in the trench 50 including the SiC layer 52. Further, an aluminum film 55 is formed on the oxide film 53 on the bottom surface of the trench 50,
The aluminum film 55 is electrically connected to the SiC layer 52 via the nickel film 54. The aluminum film 55 is S
The iC layers 51 and 52 are extended to the outer peripheral side. The aluminum film 55 functions as a field plate.

The trenches 5, 20, 30, 40, 50 are formed at the same time, and the N-type SiC layers 6, 21, 3 are formed.
1, 41 and 51 are formed at the same time, and P-type S
The iC layers 7, 22, 32, 42, 52 are formed at the same time.

An N ⁺ region 60 is formed on the end face of the chip, and an aluminum film 62 is formed on the region 60 via a nickel film 61 so as to form an equipotential ring (EQ).
R).

In this way, the vertical JFET of this embodiment is
In the outer peripheral portion of the cell portion in which the trench 5 is formed, a guard ring structure having the same structure as the trench 5, the channel layer 6, and the second gate layer 7 in the cell portion is
One is forming. Further, the members 3a, 3 corresponding to the first gate layer 3 and the second gate layer 7 in this structure.
b, 3c, 32, and 42 are in an electrically floating state. As a result, the structures of the trench (5), the first gate layer (3), the channel layer (6), and the second gate layer (7) in the cell portion are used as they are as the guard ring structure. The same breakdown voltage as that of the cell portion can be secured, and the breakdown voltage does not decrease.

Further, the source electrodes 11 and 12 of the cell portion are set to the ground potential, and the second gate layer 22 is set to the source potential (ground potential) in the separation portion on the outer periphery of the cell portion. Therefore, it becomes easy to cause a breakdown at the corner of the second gate layer 22 (corner of the bottom surface of the trench 20) in the isolation portion. In this way, a structure similar to the trench 5, the channel layer 6, and the second gate layer 7 in the cell portion is formed in the portion between the cell portion and the guard ring structure, and the first structure here is formed. The member 22 corresponding to the second gate layer is set to the ground potential. As a result, breakdown can be caused in the trench portion between the cell portion and the guard ring structure, which is advantageous in improving surge withstand capability.

Further, the first gate layer 3 is electrically separated from the cell portion in the outer peripheral portion of the cell portion where the trench 5 is formed, and the source layer 4 and the first gate layer 3 are formed at the end portion of the chip. A trench 50 penetrating through 3 and reaching the drift layer 2 is formed. Further, from the cell portion side to at least the inner end portion β at the bottom surface of the trench 50,
A field plate having the same structure as the channel layer 6 and the second gate layer 7 and having the member 52 corresponding to the second gate layer at the same potential as the electrically separated first gate layer 3c. The layers 51 and 52 are extended. Thus, it is possible to secure the breakdown voltage at the boundary α1 inside the chip of the trench 50 around the chip of FIG. 1, more specifically, at the upper surface α1 of the drift layer 2 on the side surface of the trench 50.
The channel layer 6 (51) and the second gate layer 7 (52) in the cell portion are extended and used as a field plate. Therefore, the same impurity concentration as that of the SiC layer (second gate layer) 7 in the cell portion can be formed, and the total distance between the N ⁻ drift layer 2 and the channel layer 6 when measured from the N ⁺ drain layer (substrate 1). d can be made equal (d1 = d2), so that the breakdown voltage does not decrease.

Further, these two things are simultaneously performed. That is, a guard ring structure having the same structure as the trench 5, the channel layer 6, and the second gate layer 7 in the cell portion is formed in the outer peripheral portion of the cell portion in which the trench 5 is formed, and the structure is formed. The members 3a, 3b, 3c, 3 corresponding to the first gate layer 3 and the second gate layer 7 in
2, 42 are electrically floating,
A trench 50 that penetrates the source layer 4 and the first gate layer 3 and reaches the drift layer 2 is formed at the end portion of the chip, and at least from the cell portion side to the inner end portion β at the bottom surface of the trench 50. The member 52 having the same structure as the channel layer 6 and the second gate layer 7 and corresponding to the second gate layer has the same potential as the member 3c corresponding to the first gate layer in the guard ring structure. The field plate layers 51 and 52 are extended. Therefore, both actions and effects can be obtained, and a higher breakdown voltage can be achieved.

Further, a field plate wiring material 55 is provided on the insulating film (oxide film) 53 from the outer ends of the field plate layers 51 and 52 to the outer peripheral side. That is, the wiring electrode 55 is extended from the P-type SiC layer 52 to the outer peripheral side of the chip as a second field plate. In this way, the wiring material (electrode) 55 is located above the end portion (point α2 in FIG. 1) of the PN junction between the N-type SiC layer 51 and the P-type SiC layer 52 at the cell outer peripheral portion. By thus forming, the electric field at the end portions of the field plate layers 51 and 52, that is, the end portions (α2 points) of the PN junction portion can be relaxed, and a higher breakdown voltage outer peripheral structure can be obtained.

Next, the manufacturing process will be described with reference to FIGS. First, as shown in FIG. 2, an N ⁻ drift layer 2, a P ⁺ type first gate layer 3 and an N ⁺ source layer 4 are formed on an N ⁺ type SiC substrate 1 by an epitaxial growth method.
And are laminated in order. Then, the LTO film 70 is deposited on the substrate (N ⁺ source layer 4) and the film 70 is patterned. Etching is performed using the patterned LTO film 70 as a mask material to form trenches 5, 20, 3
0, 40, 50 are formed. Each trench 5, 20, 3
0, 40, 50 penetrate the source layer 4 and the first gate layer 3 and reach the drift layer 2.

In this way, the source layer 4 is formed in the cell formation area and the guard ring formation area in the outer peripheral portion thereof.
At the same time, trenches 5, 30 and 40 penetrating the first gate layer 3 and reaching the drift layer 2 are formed. Further, trenches 5, 30, 40, 50 penetrating the source layer 4 and the first gate layer 3 and reaching the drift layer 2 are simultaneously formed in the cell formation planned region, its outer peripheral portion, and the chip end portion.

Further, ions are implanted into the bottom surface of the trench 50 at the end face of the chip to form an N ⁺ region 60 for EQR. Subsequently, after removing the LTO film 70, as shown in FIG. 3, an N layer and a P layer are sequentially formed on the substrate (on the upper surface side of the N ⁺ source layer 4) by an epitaxial growth method, and unnecessary for this epi layer. The part is removed by etching. As a result, the N layers 6, 21, 31,
41 and 51 and P layers 7, 22, 32, 42 and 52 are arranged.

That is, the trenches 5 and 3 in the cell formation area and the guard ring formation area in the outer peripheral portion thereof.
N-type SiC layers 6, 31, consisting of an epitaxial layer that will become a channel layer in the cell formation region on the inner walls of 0, 40,
41 is formed at the same time, and a P-type SiC layer 7, 3 serving as a second gate layer is formed inwardly in the cell formation planned region.
2, 42 are formed at the same time. Further, in the cell formation region, an N-type S formed of an epitaxial layer that becomes a channel layer is formed.
The iC layers 6, 31, 41, 51 and the P-type SiC layers 7, 32, 42, 5 serving as the second gate layer in the cell formation planned region.
2 in the trench 5 in the cell formation planned region,
The trenches 30 and 40 in the outer peripheral portion and the trench 50 at the chip end portion are formed so as to extend from the cell portion side to at least the inner end portion β at the bottom surface of the trench 50.

Then, as shown in FIG. 4, the contact portion in the first gate layer 3 is removed by etching,
Further, the LTO film 10 is formed and a contact hole is opened.

Thereafter, as shown in FIG. 1, the nickel film for ohmic electrodes 8, 11, 13, 23, 33, 43, 5 is formed.
4, 61 and aluminum films 9, 12, 14, 24, 34,
44, 55, 62 are formed (patterned). Further, the first gate layers 3a, 3b, 3c and the P-type SiC layers 32, 42 in the guard ring portion (guard ring formation planned area) are electrically floating and the first gate layers 3a, 3b, 3c in the cell formation planned area The gate layer 3 and the P-type SiC layer 7 to be the second gate layer are provided with wirings to which a predetermined voltage can be applied. In addition, the P-type SiC layer 52 in the trench 50 at the end of the chip is
The wiring material 56 is electrically connected to the electrically isolated first gate layer 3c.

Therefore, by manufacturing in this way, it is difficult to balance the breakdown voltage in the cell portion and the breakdown voltage in the cell outer periphery portion because the cell portion and the cell outer periphery portion have different structures. Alternatively, since the withstand voltage structure is formed in the cell outer peripheral portion, an unnecessary process is required in the cell portion, which causes an increase in the number of processes and it is extremely difficult to obtain process consistency. On the other hand, in the present embodiment, since the outer peripheral structure can be formed at the same time when the cell portion is formed, it is not necessary to add an extra step, so that the cost can be reduced.

(Second Embodiment) Next, the second embodiment will be described focusing on the differences from the first embodiment. FIG. 5 shows a vertical sectional view of a silicon carbide semiconductor device (vertical JFET) according to the present embodiment, which is an alternative to FIG. In this embodiment, the breakdown voltage is improved at points α1 and α3 in FIG. That is, the drift layer 2 on the side surface of the trenches 30, 40, 50 formed in the outer peripheral portion of the cell portion
The withstand voltage is improved at the portions α1 and α3 intersecting with the upper surface of.

In FIG. 5, trenches 30, 40, which penetrate the source layer 4 and the first gate layer 3 and reach the drift layer 2 in the outer peripheral portion of the cell portion where the trench 5 is formed,
50 is formed so that the first gate layer 3 of the cell portion is separated. That is, the trenches 30, 40, 50 are formed in a ring shape as described in the first embodiment. Also, at least these trenches 30, 4
P-type (P ⁻ -type) impurity diffusion regions 80, 81 thinner than the first gate layer 3 in the drift layer 2 at the portions α1, α3 intersecting the upper surface of the drift layer 2 on the side surfaces of 0, 50,
82 is formed. Specifically, the P ⁻ -type impurity diffusion regions 80 and 81 extend over the portions of the drift layer 2 that are in contact with the entire length of the side surfaces and the entire length of the bottom surface of the trenches 30 and 40. In addition, the P ⁻ -type impurity diffusion region 8
No. 2 extends over the entire length of the side surface of the trench 50 in the drift layer 2 and a portion in contact with part of the bottom surface.

The manufacturing method is as follows. First, FIG.
The steps shown in are executed. That is, the N ⁺ type SiC substrate 1
On top of which is an N ⁻ type drift layer 2 made of an epitaxial layer
And a P ⁺ -type first gate layer 3 made of SiC, and Si
The N ⁺ type source layer 4 made of C is sequentially stacked. Further, trenches 5, 20, 30, 40, 50 are formed.
That is, the trench 5 penetrating the source layer 4 and the first gate layer 3 to reach the drift layer 2 in the planned cell formation region, and the source layer 4 and the first gate layer 3 in the cell outer peripheral portion. Then reaches the drift layer 2 and reaches the first cell portion.
The trenches 30 and 40 for separating the gate layer 3 are simultaneously formed.

Then, a mask material 90 is arranged as shown in FIG. Then, ion implantation using the mask materials 70 and 90 is performed to form P ⁻ layers 80, 81 and 82 in predetermined regions in the trenches 30, 40 and 50. That is, the P ⁻ -type impurity diffusion regions 80 and 81 are formed at the exposed portions of the drift layer 2 in the trenches 30 and 40 at the cell outer periphery, and the drift layer 2 is exposed without the mask material 90 in the trench 50. A P ⁻ type impurity diffusion region 82 is formed in the portion.

Subsequently, after removing the mask materials 70 and 90, as described with reference to FIG. 3, the N layer and the P layer are formed on the substrate (the upper surface side of the N ⁺ source layer 4) by the epitaxial growth method.
Layers are sequentially formed and unnecessary portions of the epi layer are removed by etching (N layers 6, 21, 31, 4).
1, 51 and P layers 7, 22, 32, 42, 52 are arranged). Then, as described with reference to FIG. 4, the contact portion in the first gate layer 3 is removed by etching, the LTO film 10 is further formed, and the contact hole is opened.

In this way, the N-type channel layer 6 made of an epitaxial layer is formed on the inner wall of the trench 5 at least in the cell formation region, and the inside of the N-type channel layer 6 is made of SiC which is denser than the impurity diffusion regions 80, 81 and 82. Then, a P-type second gate layer 7 is formed.

After that, each electrode and wiring are formed as shown in FIG. That is, the nickel films 8, 11, 13, 2
3, 33, 43, 54, 61, aluminum film 9, 12, 1
4, 24, 34, 44, 55, 62 and wiring member 56
Are formed (patterned).

[0044] Therefore, in the structure of FIG. 5, P ^- layer 8
By providing 0, 81, and 82, it is possible to relax the electric field at the portions α1 and α3 that intersect the upper surface of the drift layer 2 on the side surfaces of the trenches 30, 40 and 50 formed in the outer peripheral portion of the cell portion. Therefore, high breakdown voltage can be achieved. In particular, since the P ⁻ layers 80 and 81 are extended over the portions of the drift layer 2 that are in contact with the side surfaces and bottom surfaces of the trenches 30 and 40, the electric field at the bottom surfaces of the trenches 30 and 40 can be relaxed, so that a high breakdown voltage is achieved. be able to. Further, in the manufacturing method, since the outer peripheral structure can be formed at the same time when the cell portion is formed, it is not necessary to add an extra step, so that the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a vertical sectional view of a silicon carbide semiconductor device according to a first embodiment.

FIG. 2 is a vertical cross-sectional view of a silicon carbide semiconductor device for explaining the manufacturing process.

FIG. 3 is a vertical cross-sectional view of the silicon carbide semiconductor device for explaining the manufacturing process.

FIG. 4 is a vertical cross-sectional view of the silicon carbide semiconductor device for explaining the manufacturing process.

FIG. 5 is a vertical sectional view of a silicon carbide semiconductor device according to a second embodiment.

FIG. 6 is a vertical cross-sectional view of the silicon carbide semiconductor device for explaining the manufacturing process.

FIG. 7 is a vertical cross-sectional view of a silicon carbide semiconductor device for explaining a conventional technique.

[Explanation of symbols]

1 ... N ⁺ type SiC substrate, 2 ... N ^- drift layer, 3 ... First gate layer, 4 ... N ⁺ source layer, 5 ... Trench, 6 ... N-type channel layer, 7 ... Second gate layer, 20 … Trenches, 2
1 ... N-type channel layer, 22 ... 2nd gate layer, 30 ... Trench, 31 ... N-type SiC layer, 32 ... P-type SiC layer, 4
0 ... Trench, 41 ... N-type SiC layer, 42 ... P-type SiC
Layers, 50 ... Trench, 51 ... N-type SiC layer, 52 ... P-type SiC layer, 53 ... Oxide film, 55 ... Aluminum film.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/808 F term (reference) 5F032 AC04 BA01 CA05 CA09 CA16 5F102 FA01 FA08 GB02 GB05 GC08 GD04 GJ02 GL02 GR07 HC01 HC07

Claims (10)

[Claims] 1. A high-concentration first-conductivity-type SiC substrate (1)
A low-concentration first-conductivity-type drift layer (2) made of an epitaxial layer, a second-conductivity-type first gate layer (3) made of SiC, and a first-conductivity-type source made of SiC. The layer (4) is sequentially laminated, and a trench (5) penetrating the source layer (4) and the first gate layer (3) to reach the drift layer (2) is formed.
A channel layer (6) of the first conductivity type made of an epitaxial layer is formed on the inner wall of the trench (5), and a second gate layer (7) of the second conductivity type made of SiC is formed inside the channel layer (6). In the silicon carbide semiconductor device, the outer peripheral portion of the cell portion in which the trench (5) is formed has the same structure as the trench (5), the channel layer (6) and the second gate layer (7) in the cell portion. The members (3a, 3b, 3c, 32, 42) forming the guard ring structure and corresponding to the first gate layer (3) and the second gate layer (7) in this structure are electrically connected. A silicon carbide semiconductor device characterized in that it is in a floating state. 2. A high-concentration first conductivity type SiC substrate (1)
A low-concentration first-conductivity-type drift layer (2) made of an epitaxial layer, a second-conductivity-type first gate layer (3) made of SiC, and a first-conductivity-type source made of SiC. The layer (4) is sequentially laminated, and a trench (5) penetrating the source layer (4) and the first gate layer (3) to reach the drift layer (2) is formed.
A channel layer (6) of the first conductivity type made of an epitaxial layer is formed on the inner wall of the trench (5), and a second gate layer (7) of the second conductivity type made of SiC is formed inside the channel layer (6). In the silicon carbide semiconductor device, the first gate layer (3) is electrically separated from the cell portion at the outer peripheral portion of the cell portion where the trench (5) is formed, and the source is provided at the end portion of the chip. Forming a trench (50) penetrating the layer (4) and the first gate layer (3) to reach the drift layer (2);
From the cell portion side to at least the inner end portion (β) at the bottom surface of the trench (50), the channel layer (6) and the second layer
Field plate having a structure similar to that of the first gate layer (7) and having the same potential as the electrically isolated first gate layer (3c) of the member (52) corresponding to the second gate layer. A silicon carbide semiconductor device in which layers (51, 52) are extended. 3. A high-concentration first conductivity type SiC substrate (1)
A low-concentration first-conductivity-type drift layer (2) made of an epitaxial layer, a second-conductivity-type first gate layer (3) made of SiC, and a first-conductivity-type source made of SiC. The layer (4) is sequentially laminated, and a trench (5) penetrating the source layer (4) and the first gate layer (3) to reach the drift layer (2) is formed.
A channel layer (6) of the first conductivity type made of an epitaxial layer is formed on the inner wall of the trench (5), and a second gate layer (7) of the second conductivity type made of SiC is formed inside the channel layer (6). In the silicon carbide semiconductor device, the outer peripheral portion of the cell portion in which the trench (5) is formed has the same structure as the trench (5), the channel layer (6) and the second gate layer (7) in the cell portion. The members (3a, 3b, 3c, 32, 42) forming the guard ring structure and corresponding to the first gate layer (3) and the second gate layer (7) in this structure are electrically connected. And a trench (50) penetrating the source layer (4) and the first gate layer (3) to reach the drift layer (2) is formed at the end of the chip.
From the cell portion side to at least the inner end portion (β) at the bottom surface of the trench (50), the channel layer (6) and the second layer
A member (52) having a structure similar to that of the gate layer (7) and corresponding to the second gate layer is the same as the member (3c) corresponding to the first gate layer in the guard ring structure. A silicon carbide semiconductor device, wherein field plate layers (51, 52) having a potential are extended. 4. The field plate layer (51, 5)
The silicon carbide semiconductor device according to claim 2 or 3, wherein a field plate wiring member (55) is provided on the insulating film (53) further outward from the outer end of (2). 5. A structure similar to the trench (5), the channel layer (6), and the second gate layer (7) in the cell portion is formed in a portion between the cell portion and the guard ring structure. The silicon carbide semiconductor device according to any one of claims 1, 3 and 4, wherein the member (22) corresponding to the second gate layer (7) here has a ground potential. . 6. A high-concentration first conductivity type SiC substrate (1)
A low-concentration first-conductivity-type drift layer (2) made of an epitaxial layer, a second-conductivity-type first gate layer (3) made of SiC, and a first-conductivity-type source made of SiC. The layer (4) is sequentially laminated, and a trench (5) penetrating the source layer (4) and the first gate layer (3) to reach the drift layer (2) is formed.
A channel layer (6) of the first conductivity type made of an epitaxial layer is formed on the inner wall of the trench (5), and a second gate layer (7) of the second conductivity type made of SiC is formed inside the channel layer (6). In the silicon carbide semiconductor device, a trench (which penetrates the source layer (4) and the first gate layer (3) to reach the drift layer (2) in the outer peripheral portion of the cell portion where the trench (5) is formed ( 30, 4
0, 50) is formed so that the first gate layer (3) of the cell portion is separated, and at least the upper surface of the drift layer (2) at the side surface of the trench (30, 40, 50). Carbonization characterized by forming a second conductivity type impurity diffusion region (80, 81, 82) thinner than the first gate layer (3) in the drift layer (2) at the intersecting portions (α1, α3). Silicon semiconductor device. 7. The thin second-conductivity-type impurity diffusion region (80, 81) is extended over a portion of the drift layer (2) in contact with a side surface and a bottom surface of the trench (30, 40). The silicon carbide semiconductor device according to claim 6. 8. A high-concentration first conductivity type SiC substrate (1)
A low-concentration first-conductivity-type drift layer (2) made of an epitaxial layer, a second-conductivity-type first gate layer (3) made of SiC, and a first-conductivity-type source made of SiC. A step of laminating the layer (4) in order, and a drift layer penetrating the source layer (4) and the first gate layer (3) in the cell formation planned region and the guard ring formation planned region at the outer periphery thereof. A step of simultaneously forming the trenches (5, 30, 40) reaching (2), and a cell formation plan on the inner walls of the trenches (5, 30, 40) in the cell formation plan region and the guard ring formation plan region in the outer peripheral portion thereof. In the region, a first conductivity type SiC layer (6, 31, 4) made of an epitaxial layer serving as a channel layer
1) is formed at the same time, and a second conductivity type SiC layer (7, 32, 42) serving as a second gate layer is formed in the cell formation planned region at the same time, and the guard ring formation planned region is formed. The first gate layer (3
a, 3b, 3c) and a second conductivity type SiC layer (32,
42) is in an electrically floating state, and the first gate layer (3) in the planned cell formation region and the second conductivity type SiC layer (7) to be the second gate layer are predetermined. And a step of providing a wiring to which the voltage can be applied, the method of manufacturing a silicon carbide semiconductor device. 9. A high-concentration first conductivity type SiC substrate (1)
A low-concentration first-conductivity-type drift layer (2) made of an epitaxial layer, a second-conductivity-type first gate layer (3) made of SiC, and a first-conductivity-type source made of SiC. A step of laminating the layer (4) in order, and a drift layer (2) penetrating the source layer (4) and the first gate layer (3) at the cell formation planned region, its outer peripheral portion and chip end portion. Trench reaching (5, 30, 40,
50) and the first conductivity type SiC layer (6, 31, 41, 5) made of an epitaxial layer which becomes a channel layer in the cell formation planned region.
1) and a second gate layer in the planned cell formation region
A laminated body of conductive type SiC layers (7, 32, 42, 52) is provided in the trench (5) in the cell formation planned region, in the trenches (30, 40) at the outer periphery thereof, and in the chip end portion. Forming a trench (50) extending from the cell portion side to at least the inner end portion (β) at the bottom surface of the trench (50), and the second conductivity type of the second conductivity type in the trench (50) at the chip end portion. And a step of electrically connecting the SiC layer (52) to the electrically isolated first gate layer (3c) inwardly. 10. A low-concentration first layer comprising an epitaxial layer on a high-concentration first-conductivity-type SiC substrate (1).
A step of sequentially stacking a conductivity type drift layer (2), a second conductivity type first gate layer (3) made of SiC, and a first conductivity type source layer (4) made of SiC; A trench (5) penetrating the source layer (4) and the first gate layer (3) to reach the drift layer (2) in a region to be formed and a source layer (4) and a trench (5) in the outer peripheral portion of the cell. A step of simultaneously forming trenches (30, 40) penetrating the first gate layer (3) and reaching the drift layer (2) to separate the first gate layer (3) of the cell part; Of the second conductivity type impurity diffusion regions (80, 81) in the exposed portions of the drift layer (2) in the trenches (30, 40) of the trenches (30, 40), and The inner wall is made of epitaxial layer and is of the first conductivity type. Forming a channel layer (6) and forming a second conductive type second gate layer (7) made of SiC, which is denser than the impurity diffusion regions (80, 81), inside thereof. A method for manufacturing a silicon carbide semiconductor device, comprising: