JP2003264205A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

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Publication number
JP2003264205A
JP2003264205A JP2002063413A JP2002063413A JP2003264205A JP 2003264205 A JP2003264205 A JP 2003264205A JP 2002063413 A JP2002063413 A JP 2002063413A JP 2002063413 A JP2002063413 A JP 2002063413A JP 2003264205 A JP2003264205 A JP 2003264205A
Authority
JP
Japan
Prior art keywords
semiconductor chip
adhesive
semiconductor device
manufacturing
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002063413A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Arai
良之 新井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2002063413A priority Critical patent/JP2003264205A/en
Publication of JP2003264205A publication Critical patent/JP2003264205A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73207Bump and wire connectors
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
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    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
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    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a semiconductor chip cannot be firmly adhered to a base due to insufficient wetting of an adhesive caused by the warp of the base on which the semiconductor chips are mounted to deteriorate reliability in a conventional manufacturing method of a semiconductor device. <P>SOLUTION: The base having the warp is corrected to a proper shape by curing the adhesive and a sealing resin at the same time under pressure for compressing and curing the sealing resin. The insufficient wetting of the adhesive is dissolved to firmly fix the semiconductor chip on the base. Thereby the semiconductor device having excellent reliability can be achieved by a simple process. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

【0002】[0002]

【従来の技術】近年、小形軽量かつ高性能の電子機器を
実現すべく、半導体装置の小型化・高性能化が進み、B
GA(Ball・Grid・Array)やLGA(L
and・Grid・Array)に代表されるような、
外部接続端子が格子状に配置されるタイプの半導体装置
が数を増しつつある。また、半導体装置内部で同種また
は異種の複数の半導体チップを平面的に配置するか、あ
るいは立体的に積層して搭載するタイプも増加しつつあ
る。
2. Description of the Related Art In recent years, semiconductor devices have been made smaller and have higher performance in order to realize electronic devices of small size, light weight and high performance.
GA (Ball, Grid, Array) and LGA (L
and Grid, Array),
The number of semiconductor devices of a type in which external connection terminals are arranged in a grid pattern is increasing. In addition, a type in which a plurality of semiconductor chips of the same type or different types are two-dimensionally arranged inside the semiconductor device or three-dimensionally stacked and mounted is also increasing.

【0003】以下に、従来の半導体装置の例を、図7
(a)〜図8(b)を参照しながら説明する。図7
(a)〜図8(b)は、従来のBGAタイプの半導体装
置における、代表的な内部構造を示す断面図である。
An example of a conventional semiconductor device is shown below in FIG.
A description will be given with reference to FIGS. Figure 7
8A to 8B are cross-sectional views showing a typical internal structure of a conventional BGA type semiconductor device.

【0004】図7(a)に示す半導体装置は、プリント
配線板102と、プリント配線板102上に接着固定さ
れている半導体チップ101と、プリント配線板102
と半導体チップ101とを接着している接着剤104
と、半導体チップ101とプリント配線板102とを電
気的に接続するワイヤ103と、半導体チップ101,
ワイヤ103および接着剤104を樹脂封止する封止樹
脂105と、金属ボール106とから構成されている。
The semiconductor device shown in FIG. 7A has a printed wiring board 102, a semiconductor chip 101 adhered and fixed on the printed wiring board 102, and a printed wiring board 102.
Adhesive 104 for bonding the semiconductor chip 101 to the semiconductor chip 101
A wire 103 for electrically connecting the semiconductor chip 101 and the printed wiring board 102, the semiconductor chip 101,
A sealing resin 105 for sealing the wire 103 and the adhesive 104 with resin, and a metal ball 106.

【0005】そして、プリント配線板102は、絶縁部
材102eと、絶縁部材102eの上に位置する複数の
配線パターン102bおよび内部接続用ランド102a
と、絶縁部材102eの下に位置する複数の外部端子用
ランド102dと、絶縁部材102eを貫通して設けら
れ,配線パターン102bおよび内部接続用ランド10
2aと外部端子用ランド102dとを電気的に接続する
バイアホール102cとから構成されている。なお、プ
リント配線板102はサブストレートまたはインターポ
ーザと称することもある。
The printed wiring board 102 has an insulating member 102e, a plurality of wiring patterns 102b located on the insulating member 102e, and internal connection lands 102a.
And a plurality of external terminal lands 102d located below the insulating member 102e and the insulating member 102e, and the wiring pattern 102b and the internal connecting lands 10d.
2a and via hole 102c for electrically connecting external terminal land 102d. The printed wiring board 102 may be referred to as a substrate or an interposer.

【0006】図7(b)においては、図7(a)に示す
構造に加えて、半導体チップ101の上に、第2接着剤
114によって第2半導体チップ111が接着固定され
ており、第2半導体チップ111とプリント配線板10
2とが第2ワイヤ113によって電気的に接続されてい
る。
In FIG. 7B, in addition to the structure shown in FIG. 7A, a second semiconductor chip 111 is bonded and fixed on the semiconductor chip 101 by a second adhesive 114. Semiconductor chip 111 and printed wiring board 10
2 is electrically connected to the second wire 113.

【0007】図7(c)は、2個の半導体チップを平面
的に配列した場合の構造を示している。
FIG. 7C shows a structure in which two semiconductor chips are arranged in a plane.

【0008】図8(a)は、図7(b)における半導体
チップ101がバンプ108を介してプリント配線板1
02とフリップチップ接続された構造を示している。
In FIG. 8A, the semiconductor chip 101 in FIG. 7B is printed wiring board 1 via bumps 108.
No. 02 and flip-chip connected structure.

【0009】図8(b)においては、図7(b)におけ
る第2半導体チップ111が半導体チップ101にバン
プ118を介してフリップチップ接続された構造を示し
ている。
FIG. 8B shows a structure in which the second semiconductor chip 111 in FIG. 7B is flip-chip connected to the semiconductor chip 101 via bumps 118.

【0010】なお、図7(a)〜図8(b)に示す構造
のうち、図7(a)に示す構造は、特開平9−1210
02号公報に、図7(b),図8(a)に示す構造は、
特開平11−204720号公報に開示されている。
Among the structures shown in FIGS. 7A to 8B, the structure shown in FIG. 7A is disclosed in Japanese Patent Laid-Open No. 9-1210.
In the No. 02 publication, the structures shown in FIGS. 7B and 8A are
It is disclosed in JP-A-11-204720.

【0011】次に、図7(a)の半導体装置の組立工程
について、図9(a)〜図10(c)を参照しながら説
明する。図9(a)〜図10(c)は、図7(a)に示
す半導体装置を製造する工程を示した断面図である。な
お、図9(a)〜(c)をダイボンド工程、図9(d)
をダイボンドキュア工程、図10(a)をワイヤボンド
工程、図10(b)を封止工程、図10(c)をアフタ
ーキュア工程と称する。
Next, a process of assembling the semiconductor device shown in FIG. 7A will be described with reference to FIGS. 9A to 10C. 9A to 10C are cross-sectional views showing the steps of manufacturing the semiconductor device shown in FIG. 7A. 9A to 9C are die-bonding steps, and FIG.
Is called a die bond curing step, FIG. 10A is called a wire bonding step, FIG. 10B is called a sealing step, and FIG. 10C is called an after cure step.

【0012】まず、図9(a)〜(c)のうちのいずれ
かの工程(ダイボンド工程)において、接着剤104を
用いて、プリント配線板102と半導体チップ101と
を接続する。ここで、用いる接着剤104の種類によっ
て、図9(a)〜(c)のうちのいずれかの工程が選択
される。図9(a)においては、常温下で、プリント配
線板102の上にペーストタイプの接着剤104を塗布
した後、半導体チップ101を搭載する。図9(b)に
おいては、プリント配線板102の上にフィルムタイプ
の接着剤104を熱圧着した後、半導体チップ101を
搭載する。図9(c)においては、あらかじめフィルム
タイプの接着材104を貼りつけた半導体チップ101
を、プリント配線板102の上に搭載した後、熱圧着を
行なう。
First, in any step (die bonding step) of FIGS. 9A to 9C, the adhesive 104 is used to connect the printed wiring board 102 and the semiconductor chip 101. Here, one of the steps in FIGS. 9A to 9C is selected depending on the type of the adhesive 104 used. In FIG. 9A, after applying a paste type adhesive agent 104 on the printed wiring board 102 at room temperature, the semiconductor chip 101 is mounted. In FIG. 9B, the semiconductor chip 101 is mounted after the film type adhesive 104 is thermocompression bonded onto the printed wiring board 102. In FIG. 9C, the semiconductor chip 101 to which the film type adhesive material 104 has been attached in advance.
After being mounted on the printed wiring board 102, thermocompression bonding is performed.

【0013】次に、図9(d)に示す工程(ダイボンド
キュア工程)で、半導体チップ101を搭載しているプ
リント配線板102をオーブン109内に入れて加熱す
ることにより接着材104を熱硬化させ、完全に半導体
チップ101をプリント配線板102上に接着固定す
る。
Next, in a step (die bond cure step) shown in FIG. 9D, the printed wiring board 102 on which the semiconductor chip 101 is mounted is placed in an oven 109 and heated to heat cure the adhesive 104. Then, the semiconductor chip 101 is completely bonded and fixed onto the printed wiring board 102.

【0014】次に、図10(a)に示す工程(ワイヤボ
ンド工程)で、ワイヤ103によって、半導体チップ1
01と、プリント配線板102における内部接続用ラン
ド102aとを接続する。
Next, in the step (wire bonding step) shown in FIG. 10A, the semiconductor chip 1 is connected by the wire 103.
01 and the internal connection land 102a in the printed wiring board 102 are connected.

【0015】次に、図10(b)に示す工程(封止工
程)で、上部金型120aと下部金型120bとに挟ま
れた空間にこれまでの工程で組み立てた半導体装置を把
持し、半導体チップ101と、プリント配線板102
と、ワイヤ103と、接着剤104とを保護被覆するよ
う封止樹脂105を形成する。
Next, in the step (sealing step) shown in FIG. 10B, the semiconductor device assembled in the above steps is held in the space between the upper die 120a and the lower die 120b, Semiconductor chip 101 and printed wiring board 102
Then, the sealing resin 105 is formed so as to protect and cover the wire 103 and the adhesive 104.

【0016】次に、図10(c)に示す工程(アフター
キュア工程)で、オーブン109に封止済みの半導体装
置を投入し、封止樹脂105の完全な硬化を行なう。図
7(a)に示す金属ボール106の搭載は、図10
(c)に示す工程の後となるが、図示は省略する。
Next, in a step (after-cure step) shown in FIG. 10C, the sealed semiconductor device is put into the oven 109 to completely cure the sealing resin 105. Mounting of the metal balls 106 shown in FIG.
Although it is after the step shown in (c), illustration is omitted.

【0017】次に、図7(b)の半導体装置の組立工程
について、図11(a)〜図14(b)を参照しながら
説明する。図11(a)〜図14(b)は、図7(b)
に示す半導体装置を製造する工程を示した断面図であ
る。なお、図11(a)〜(c)を第1のダイボンド工
程、図11(d)を第1のダイボンドキュア工程、図1
2(a)〜(c)を第2のダイボンド工程、図13
(a)を第2のダイボンドキュア工程、図13(b)を
ワイヤボンド工程、図14(a)を封止工程、図14
(b)をアフターキュア工程と称する。
Next, a process of assembling the semiconductor device of FIG. 7B will be described with reference to FIGS. 11A to 14B. 11 (a) to 14 (b) are shown in FIG. 7 (b).
FIG. 6 is a cross-sectional view showing a step of manufacturing the semiconductor device shown in FIG. 11A to 11C are the first die bond step, FIG. 11D is the first die bond cure step, and FIG.
2 (a) to 2 (c) in the second die bonding step, FIG.
14A is a second die bond curing step, FIG. 13B is a wire bonding step, FIG. 14A is a sealing step, and FIG.
(B) is called an after-cure process.

【0018】まず、図11(a)〜(d)に示す工程に
おいては、図9(a)〜(d)と同様の工程を行なう。
First, in the steps shown in FIGS. 11A to 11D, steps similar to those in FIGS. 9A to 9D are performed.

【0019】次に、図12(a)〜(c)に示す工程
で、半導体チップ101の上に、第2半導体チップ11
1を第2接着剤114によって接着する。図12(a)
〜(c)に示す接着の方法としては、図9(a)〜
(c)に示したのと同様な3つの方法がある。
Next, in a step shown in FIGS. 12A to 12C, the second semiconductor chip 11 is formed on the semiconductor chip 101.
1 is bonded by the second adhesive 114. Figure 12 (a)
9 (a)-
There are three methods similar to those shown in (c).

【0020】次に、図13(a)に示す工程で、オーブ
ン109で、第2接着剤114を熱硬化させることによ
り、第2半導体チップ111と半導体チップ101とを
完全に接着固定する。
Next, in the step shown in FIG. 13A, the second adhesive 114 is thermoset in the oven 109 to completely bond and fix the second semiconductor chip 111 and the semiconductor chip 101.

【0021】次に、図13(b)〜図14(b)に示す
工程においては、図10(a)〜(c)と同様の工程を
行なう。
Next, in the steps shown in FIGS. 13B to 14B, the same steps as those in FIGS. 10A to 10C are performed.

【0022】[0022]

【発明が解決しようとする課題】しかしながら、従来の
製造方法では、接着剤の接着界面に濡れ不足が発生し
た。その濡れ不足は、半導体装置の信頼性を低下せしめ
る原因となる。以下、濡れ不足の発生原因について、図
15(a)〜図16(b)を参照しながら説明する。な
お、図15(a),(b),図16(a),(b)は、
従来の半導体装置の製造方法における不具合を説明する
ための断面図である。
However, in the conventional manufacturing method, insufficient wetting occurs at the adhesive interface of the adhesive. The insufficient wetting causes a decrease in reliability of the semiconductor device. Hereinafter, the cause of insufficient wetting will be described with reference to FIGS. 15 (a) to 16 (b). In addition, FIG. 15 (a), (b), FIG. 16 (a), (b),
FIG. 11 is a cross-sectional view for explaining a defect in the conventional method for manufacturing a semiconductor device.

【0023】濡れ不足の原因には2つある。1つは接着
剤にて半導体チップを接着する下地の反りであり、もう
1つは接着剤の内部に生じるボイドである。
There are two causes of insufficient wetting. One is the warp of the base that adheres the semiconductor chip with an adhesive, and the other is a void generated inside the adhesive.

【0024】図15(a)に示すのはダイボンドキュア
工程における半導体装置である。ここで、半導体チップ
101は反りが生じたプリント配線板102に搭載して
いる。プリント配線102の反りの原因には2つある。
1つはプリント配線板102の製造時に生じる反りであ
り、もう1つはダイボンドキュア時(図15(a))に
生じる反りである。
FIG. 15A shows a semiconductor device in the die bond cure process. Here, the semiconductor chip 101 is mounted on the warped printed wiring board 102. There are two causes of the warp of the printed wiring 102.
One is the warp that occurs when the printed wiring board 102 is manufactured, and the other is the warp that occurs during die bond cure (FIG. 15A).

【0025】反りの第1の原因について説明する。図1
5(a)に示すプリント配線板102は、絶縁部材10
2eを内部接続用ランド102aおよび配線パターン1
02bの層と、外部端子用ランド102dの層ではさん
だ積層体であり、配線パターン102bと外部端子用ラ
ンド102dとは、バイアホール102cによって接続
されている。ここで、3層の積層体であるプリント配線
板(両面プリント配線板)102は、製造時において、
絶縁部材102eの初期応力,絶縁部材102eの上面
と下面とで導体層の面積が異なることに起因する応力,
外形の加工工程やバイアホール102cを形成する工程
における加工歪み等が発生する。そうした要因により、
プリント配線板102は初期的に反りを有している。
The first cause of the warp will be described. Figure 1
The printed wiring board 102 shown in FIG.
2e is an internal connection land 102a and a wiring pattern 1
The layer 02b and the layer for external terminal land 102d sandwich the layer, and the wiring pattern 102b and the external terminal land 102d are connected by a via hole 102c. Here, the printed wiring board (double-sided printed wiring board) 102, which is a laminate of three layers, is
The initial stress of the insulating member 102e, the stress due to the difference in the area of the conductor layer between the upper surface and the lower surface of the insulating member 102e,
Processing distortion and the like occur in the outer shape processing step and the step of forming the via hole 102c. Due to such factors,
The printed wiring board 102 initially has a warp.

【0026】次に、反りの第2の原因について説明す
る。図15(a)に示すダイボンドキュア工程で、半導
体装置をオーブン109内にて加熱すると、接着剤10
4と半導体チップ101とプリント配線板102には、
それぞれの熱膨張による応力と、接着剤104の熱硬化
収縮による応力とが働く。このときの応力分布は、各部
材の物性,サイズ,オーブン109内の温度等に依存す
る。
Next, the second cause of the warp will be described. When the semiconductor device is heated in the oven 109 in the die bond curing step shown in FIG.
4, the semiconductor chip 101 and the printed wiring board 102,
The stress due to each thermal expansion and the stress due to the thermosetting shrinkage of the adhesive 104 work. The stress distribution at this time depends on the physical properties and size of each member, the temperature inside the oven 109, and the like.

【0027】次に、半導体装置をオーブン109から取
り出して常温におくと、この半導体装置はプリント配線
板102と半導体チップ101の熱膨張係数の違いによ
り、全体的に湾曲した形状となる。一般に、プリント配
線板102の絶縁部材102eは有機材料からなり、半
導体チップ101は、有機材料よりも熱膨張係数の小さ
な無機材料からなるため、全体の形状は凸型になること
が多い。ただし、各部材の物性やサイズにより凹型にな
ることもある。
Next, when the semiconductor device is taken out of the oven 109 and kept at room temperature, the semiconductor device has a curved shape due to the difference in thermal expansion coefficient between the printed wiring board 102 and the semiconductor chip 101. In general, the insulating member 102e of the printed wiring board 102 is made of an organic material, and the semiconductor chip 101 is made of an inorganic material having a thermal expansion coefficient smaller than that of the organic material, so that the entire shape is often convex. However, it may be concave depending on the physical properties and size of each member.

【0028】次に、接着剤界面の濡れ不足の2番目の原
因である接着剤内部のボイドについて説明する。
Next, the voids inside the adhesive, which is the second cause of insufficient wetting of the adhesive interface, will be described.

【0029】まず、接着剤104がペーストタイプであ
る場合には、ボイドの発生原因として、接着前の攪拌不
足、塗布時のエアーの巻き込み、接着時の配線パターン
102bと絶縁部材102eとの間の段差の埋め込み不
良、熱硬化時のアウトガスの巻き込みなどが挙げられ
る。
First, when the adhesive 104 is a paste type, the causes of voids are as follows: insufficient agitation before adhesion, air entrapment during application, and a gap between the wiring pattern 102b and the insulating member 102e during adhesion. Examples include defective filling of steps and entrainment of outgas during thermosetting.

【0030】接着剤104がフィルムタイプである場合
には、ペーストタイプに比べて配線パターン102bと
絶縁部材102eとの間の段差の埋め込み性が悪く、ボ
イドが発生しやすくなる。また、フィルムタイプの接着
剤には、ボイドが最初から混入していることもある。そ
れは、フィルムタイプの接着剤を製造する工程は、ベー
スとなる接着剤樹脂をフィラー等と共に溶剤に溶解して
ワニスとして、ワニスをキャリアとなるフィルムに塗布
した後に乾燥させて完成させるというものであるが、そ
の乾燥時において、アウトガス揮発跡やキャリアフィル
ムへのワニスの濡れ不足領域などがボイドの原因となる
からである。また、熱硬化時においても、アウトガスに
よるボイドが発生する。
When the adhesive 104 is of a film type, the step of filling the step between the wiring pattern 102b and the insulating member 102e is poorer than that of the paste type, and voids are likely to occur. In addition, voids may be mixed in the film type adhesive from the beginning. That is, the process of producing a film type adhesive is completed by dissolving a base adhesive resin in a solvent together with a filler and the like as a varnish, applying the varnish to a carrier film and then drying. However, at the time of drying, voids may be caused by the traces of volatilization of outgas, an area where the carrier film is insufficiently wet with varnish, and the like. In addition, voids are generated due to outgas even during heat curing.

【0031】次に、図15(b)に示す構造において
は、凹反りしたプリント配線板102の上に、裏面にフ
ィルムタイプの接着剤104を貼り付けた半導体チップ
101を搭載している。この場合、プリント配線板10
2に接着されるのは半導体チップ101の外縁部のみで
あり、チップ中央部は接着されていないため、チップ中
央部が濡れ不足領域となる。
Next, in the structure shown in FIG. 15B, a semiconductor chip 101 having a back surface to which a film-type adhesive agent 104 is attached is mounted on a warped printed wiring board 102. In this case, the printed wiring board 10
Since only the outer edge of the semiconductor chip 101 is bonded to the second chip 2 and the central part of the chip is not bonded, the central part of the chip becomes an insufficient wetting region.

【0032】図16(a)に示す構造は、プリント配線
板102の上に2個の半導体チップが積層されており、
第2接着剤114にはペーストタイプが用いられてい
る。この場合には、半導体チップ101とプリント配線
板102とが第1のダイボンド工程にて半導体チップ1
01の上面の凸反りを発生させている。このため、第2
半導体置チップ111を半導体チップ101の上面にダ
イボンドすると、図15(a)と同様に、第2接着剤1
14の濡れ不足が生じる。
In the structure shown in FIG. 16A, two semiconductor chips are stacked on the printed wiring board 102,
A paste type is used for the second adhesive 114. In this case, the semiconductor chip 101 and the printed wiring board 102 are not bonded to each other in the first die bonding process.
The convex warp of the upper surface of 01 is generated. Therefore, the second
When the semiconductor mounting chip 111 is die-bonded to the upper surface of the semiconductor chip 101, the second adhesive 1 is formed in the same manner as in FIG.
14 becomes insufficiently wet.

【0033】図16(b)に示す構造においては、プリ
ント配線板102の上に2個の半導体チップが積層され
ており、第2接着剤114にはフイルムタイプが用いら
れている。この場合でも、図16(a)と同様に、半導
体チップ101の上面に凸反りが発生している。第2接
着剤114の接着強度が低いと、第2半導体チップ11
1を半導体チップ101の上面にダイボンドする際、第
2半導体チップ111の一部のみしか下地と接着されな
いため、大きな濡れ不足領域が発生する。
In the structure shown in FIG. 16B, two semiconductor chips are laminated on the printed wiring board 102, and the second adhesive 114 is a film type. Also in this case, as in FIG. 16A, the convex warpage occurs on the upper surface of the semiconductor chip 101. When the adhesive strength of the second adhesive 114 is low, the second semiconductor chip 11
When 1 is die-bonded to the upper surface of the semiconductor chip 101, only a part of the second semiconductor chip 111 is bonded to the base, so that a large area of insufficient wetting occurs.

【0034】以上に説明したように、従来の半導体装置
の製造方法では、ダイボンドキュアが終了した時点で、
半導体チップの下地の反りおよび接着剤のボイドによ
り、接着剤の界面の濡れ不足が生じる。これにより、半
導体チップとその下地となる構造体との密着性が低下す
る。半導体装置内部において空間が生じると、半導体装
置の吸湿量が増加し、リフロー加熱による水分の気化膨
張により、半導体チップ破損、封止樹脂破損、金属ワイ
ヤ破損といった不良が発生しやすくなる。破損に至らぬ
までも、吸湿量の増大により、金属部分の腐食,不純物
抽出による電流リーク、短絡、汚染といった不良が発生
しやすくなる。
As described above, in the conventional semiconductor device manufacturing method, when the die bond cure is completed,
Warpage of the base of the semiconductor chip and voids of the adhesive cause insufficient wetting of the interface of the adhesive. This reduces the adhesion between the semiconductor chip and the underlying structure. When a space is created inside the semiconductor device, the amount of moisture absorbed by the semiconductor device increases, and defects such as semiconductor chip damage, sealing resin damage, and metal wire damage are likely to occur due to vaporization and expansion of water due to reflow heating. Even before damage, defects such as corrosion of metal parts, current leakage due to impurity extraction, short circuit, and contamination are likely to occur due to increase in moisture absorption.

【0035】特に、近年における半導体チップは、その
高性能化への要求から大型化しつつある。それに伴い、
接着しなければならない面積が拡大することから、プリ
ント配線板の反りによる影響が大きくなり接着剤の濡れ
性は低下しやすくなるため、濡れ不足抑制への要望が大
きくなってきている。
In particular, semiconductor chips in recent years are becoming larger due to the demand for higher performance. with this,
Since the area that must be adhered is increased, the influence of the warp of the printed wiring board becomes large, and the wettability of the adhesive agent is likely to decrease, so there is an increasing demand for suppression of insufficient wetting.

【0036】また、半導体チップの大型化は、端子数の
増大につながり、必要な配線数が増大するが、半導体装
置自体は小型化の要求が厳しいため、従来の両面プリン
ト配線板に換わり、多層プリント配線板やビルトアップ
プリント配線板が数を増しつつある。
Further, an increase in the size of the semiconductor chip leads to an increase in the number of terminals and an increase in the required number of wirings. However, since the semiconductor device itself is required to be small in size, it replaces the conventional double-sided printed wiring board and has a multilayer structure. The number of printed wiring boards and built-up printed wiring boards is increasing.

【0037】多層のプリント配線板を作製するために
は、複数の両面プリント配線板を高温かつ高圧力下で積
層成形する工程や、積層したプリント配線板同士の間を
接続するバイアホールを形成する工程が必要となり、熱
履歴や加工履歴が複雑化する。そのため、多層のプリン
ト配線板の反りは、両面プリント配線板よりも悪化す
る。さらに、ビルドアッププリント配線板では、多層プ
リント配線板の表面に導体パターンを積層形成してお
り、プリント配線板の反りの悪化の問題は、さらに重要
になってきている。
In order to produce a multilayer printed wiring board, a step of laminating and molding a plurality of double-sided printed wiring boards at high temperature and high pressure and forming via holes for connecting the laminated printed wiring boards to each other. A process is required, and heat history and processing history are complicated. Therefore, the warp of the multilayer printed wiring board is worse than that of the double-sided printed wiring board. Further, in the build-up printed wiring board, the conductor pattern is laminated on the surface of the multilayer printed wiring board, and the problem of deterioration of the warp of the printed wiring board has become more important.

【0038】また、半導体装置の高性能化と高密度実装
化の要求より、図7(b)、図8(a),(b)に示す
ような複数の半導体チップを積層した半導体装置の需要
が増しているが、このような半導体装置を製造するため
に必要な工程数は多くなり、生産性が低くなるという課
題がある。
Due to the demand for higher performance and higher density packaging of semiconductor devices, there is a demand for semiconductor devices in which a plurality of semiconductor chips are stacked as shown in FIGS. 7 (b), 8 (a) and 8 (b). However, there is a problem in that the number of steps required to manufacture such a semiconductor device increases and the productivity decreases.

【0039】本発明は、接着剤の硬化方法を講ずること
により、従来より信頼性が高い半導体装置の製造方法を
提供することを目的とする。同時に、製造方法を簡略化
し、生産性の高い半導体装置の製造方法を提供すること
も目的とする。
An object of the present invention is to provide a method of manufacturing a semiconductor device which is more reliable than conventional ones by taking a method of hardening an adhesive. At the same time, another object is to provide a method for manufacturing a semiconductor device with high productivity by simplifying the manufacturing method.

【0040】[0040]

【課題を解決するための手段】本発明の第1の半導体装
置の製造方法は、上記半導体チップを搭載する支持体
と、上記半導体チップと上記支持体とを接着する接着剤
とが、封止樹脂によって封止されている半導体装置の製
造方法であって、上記支持体と上記半導体チップと上記
接着剤とを封止金型内で上記封止樹脂で封止する工程
で、上記封止樹脂には圧力を印加して、上記接着剤の硬
化の少なくとも一部と上記封止樹脂の硬化の少なくとも
一部とを行なう工程(a)を備える。
According to a first method of manufacturing a semiconductor device of the present invention, a supporting body on which the semiconductor chip is mounted and an adhesive for adhering the semiconductor chip to the supporting body are sealed. A method of manufacturing a semiconductor device sealed with a resin, comprising the step of sealing the support, the semiconductor chip, and the adhesive with the sealing resin in a sealing mold, wherein the sealing resin Includes a step (a) of applying pressure to perform at least a part of the curing of the adhesive and at least a part of the sealing resin.

【0041】これにより、樹脂封止の圧力が半導体チッ
プと支持体とを押しつける静水圧として作用するため、
支持体の反りを矯正することができ、また、接着剤内部
におけるボイドの発生を抑制することができる。従っ
て、支持体と半導体チップとの密着性を高めることがで
きる。また、封止樹脂の硬化と同時に接着剤の硬化を行
なうので、工程の簡略化を図ることも可能となる。
As a result, the resin sealing pressure acts as a hydrostatic pressure for pressing the semiconductor chip and the support,
The warp of the support can be corrected, and the generation of voids inside the adhesive can be suppressed. Therefore, the adhesion between the support and the semiconductor chip can be improved. Further, since the adhesive is cured at the same time as the sealing resin is cured, it is possible to simplify the process.

【0042】上記半導体チップはフェイスダウン方式で
上記支持体に搭載され、上記半導体チップと上記支持体
との電気的接続をバンプによって行なってもよい。
The semiconductor chip may be mounted on the support in a face-down manner, and the semiconductor chip may be electrically connected to the support by bumps.

【0043】上記半導体チップの上に、第2接着剤を挟
んで第2半導体チップを搭載し、上記工程(a)では、
上記第2接着剤の硬化の少なくとも一部をも行なっても
よい。
A second semiconductor chip is mounted on the semiconductor chip with a second adhesive interposed therebetween, and in the step (a),
You may also perform at least one copy of the hardening of the said 2nd adhesive agent.

【0044】これにより、上記工程(a)で、第2接着
剤と封止樹脂とを硬化させることにより、樹脂封止の圧
力が半導体チップ,第2半導体チップおよび支持体を押
しつける静水圧として作用するため、支持体の反りを矯
正することができ、また、第2接着剤内部におけるボイ
ドの発生を抑制することができる。従って、半導体チッ
プと第2半導体チップとの密着性を高めることができ
る。また、工程の簡略化を図ることも可能となる。
Thus, in the step (a), the second adhesive and the sealing resin are hardened so that the resin sealing pressure acts as a hydrostatic pressure for pressing the semiconductor chip, the second semiconductor chip and the support. Therefore, the warp of the support can be corrected, and the generation of voids inside the second adhesive can be suppressed. Therefore, the adhesion between the semiconductor chip and the second semiconductor chip can be improved. It is also possible to simplify the process.

【0045】上記第2半導体チップはフェイスダウン方
式で上記半導体チップに搭載され、上記第2半導体チッ
プと上記半導体チップとの電気的接続をバンプによって
行なってもよい。
The second semiconductor chip may be mounted on the semiconductor chip in a face-down manner, and the bumps may be used to electrically connect the second semiconductor chip and the semiconductor chip.

【0046】上記半導体チップは複数が平面的に配置さ
れていてもよい。
A plurality of the semiconductor chips may be arranged in a plane.

【0047】上記工程(a)では、上記接着剤および上
記封止樹脂の上記硬化を完了させることにより、その後
に必要なアフターキュア工程を省略することができるた
め、工程の簡略化が可能となる。
In the step (a), after the curing of the adhesive and the sealing resin is completed, the after-curing step required thereafter can be omitted, so that the step can be simplified. .

【0048】本発明の第2の半導体装置の製造方法は、
半導体チップと、上記半導体チップの上に搭載される第
2半導体チップと、上記半導体チップと上記第2半導体
チップとを接着する第2接着剤とが、封止樹脂によって
封止されている半導体装置の製造方法であって、上記半
導体チップと上記第2半導体チップと上記第2接着剤と
を封止金型内で上記封止樹脂で封止する工程で、上記封
止樹脂には圧力を印加して、上記第2接着剤の硬化の少
なくとも一部と上記封止樹脂の硬化の少なくとも一部と
を行なう工程(a)を備える。
A second semiconductor device manufacturing method of the present invention is
A semiconductor device in which a semiconductor chip, a second semiconductor chip mounted on the semiconductor chip, and a second adhesive for bonding the semiconductor chip and the second semiconductor chip are sealed with a sealing resin. In the step of sealing the semiconductor chip, the second semiconductor chip, and the second adhesive with the sealing resin in a sealing mold, a pressure is applied to the sealing resin. Then, there is provided a step (a) of performing at least a part of the curing of the second adhesive and at least a part of the curing of the sealing resin.

【0049】これにより、上記工程(a)を開始する時
点において、接着剤の硬化が終了している場合であって
も、上記工程(a)で、第2接着剤と封止樹脂とを硬化
させることにより、樹脂封止の圧力が半導体チップ,第
2半導体チップおよび支持体を押しつける静水圧として
作用するため、支持体の反りを矯正することができ、ま
た、第2接着剤内部におけるボイドの発生を抑制するこ
とができる。従って、半導体チップと第2半導体チップ
との密着性を高めることができる。
As a result, even when the curing of the adhesive is completed at the time of starting the step (a), the second adhesive and the sealing resin are cured in the step (a). By doing so, the resin sealing pressure acts as a hydrostatic pressure that presses the semiconductor chip, the second semiconductor chip and the support, so that the warp of the support can be corrected, and the voids inside the second adhesive can be corrected. Occurrence can be suppressed. Therefore, the adhesion between the semiconductor chip and the second semiconductor chip can be improved.

【0050】上記第2半導体チップはフェイスダウン方
式で上記半導体チップに搭載され、上記第2半導体チッ
プと上記半導体チップとの電気的接続をバンプによって
行なってもよい。
The second semiconductor chip may be mounted on the semiconductor chip in a face-down manner, and the bumps may be used to electrically connect the second semiconductor chip and the semiconductor chip.

【0051】上記工程(a)では、上記第2接着剤およ
び上記封止樹脂の硬化を完了させることにより、その後
に必要なアフターキュア工程を省略することができるた
め、工程の簡略化が可能となる。
In the step (a), after the curing of the second adhesive and the sealing resin is completed, the after-curing step required thereafter can be omitted, so that the step can be simplified. Become.

【0052】[0052]

【発明の実施の形態】(第1の実施形態)まず、本実施
形態の製造方法を適用する半導体装置の構造について、
図2(c)を参照しながら説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) First, regarding the structure of a semiconductor device to which the manufacturing method of this embodiment is applied,
This will be described with reference to FIG.

【0053】図2(c)に示すように、本実施形態の半
導体装置は、プリント配線板2と、プリント配線板2上
に接着固定されている半導体チップ1と、プリント配線
板2と半導体チップ1とを接着している接着剤4と、ワ
イヤ3と、封止樹脂5とから構成されている。
As shown in FIG. 2C, the semiconductor device according to the present embodiment has a printed wiring board 2, a semiconductor chip 1 bonded and fixed onto the printed wiring board 2, the printed wiring board 2 and the semiconductor chip. It is composed of an adhesive 4 for bonding 1 to each other, a wire 3 and a sealing resin 5.

【0054】そして、プリント配線板2は、絶縁部材2
eと、絶縁部材2eの上に位置する複数の配線パターン
2bおよび内部接続用ランド2aと、絶縁部材2eの下
に位置する複数の外部端子用ランド2dと、絶縁部材2
eを貫通して設けられ,配線パターン2bおよび内部接
続用ランド2aと外部端子用ランド2dとを電気的に接
続するバイアホール2cとから構成されている。
The printed wiring board 2 has the insulating member 2
e, a plurality of wiring patterns 2b and internal connection lands 2a located above the insulating member 2e, a plurality of external terminal lands 2d located below the insulating member 2e, and an insulating member 2
The via hole 2c is formed so as to penetrate through e and electrically connects the wiring pattern 2b, the internal connection land 2a, and the external terminal land 2d.

【0055】ワイヤ3は、プリント配線板2と半導体チ
ップ1とを電気的に接続している。外部端子用ランド2
dには金属ボール(図示せず)を搭載し、これが半導体
装置を搭載する外部のプリント配線板(図示せず)に接
続される。封止樹脂5は、プリント配線板2の上に形成
された半導体チップ1,ワイヤ3および接着剤4を、外
部環境から保護するためにそれらを被覆して形成され
る。
The wire 3 electrically connects the printed wiring board 2 and the semiconductor chip 1. Land for external terminal 2
A metal ball (not shown) is mounted on d, and this is connected to an external printed wiring board (not shown) on which the semiconductor device is mounted. The sealing resin 5 is formed by covering the semiconductor chip 1, the wire 3 and the adhesive 4 formed on the printed wiring board 2 in order to protect them from the external environment.

【0056】次に、本実施形態の半導体装置の製造方法
について、図1(a)〜(c),図2(a)〜(c)を
参照しながら説明する。図1(a)〜(c),図2
(a)〜(c)は、第1の実施形態における半導体装置
の製造工程を示す断面図である。
Next, a method of manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 1 (a) to 1 (c) and 2 (a) to 2 (c). 1 (a) to (c) and FIG.
(A)-(c) is sectional drawing which shows the manufacturing process of the semiconductor device in 1st Embodiment.

【0057】まず、図1(a)〜(c)のうちのいずれ
かの工程(ダイボンド工程)において、接着剤4を用い
てプリント配線板2と半導体チップ1とを接着する。こ
こで、用いる接着剤4の種類によって、図1(a)〜
(c)のうちのいずれかの工程が選択される。
First, in any step (die bonding step) of FIGS. 1A to 1C, the printed wiring board 2 and the semiconductor chip 1 are bonded to each other using the adhesive 4. Here, depending on the type of the adhesive 4 used, FIG.
Either step of (c) is selected.

【0058】図1(a)に示す工程においては、常温下
で、プリント配線板2の上にペーストタイプの接着剤4
を塗布した後、半導体チップ1を搭載する。その後、1
00〜250℃で数十秒〜数分のインラインキュアを行
なって接着剤4を仮硬化させて、プリント配線板2と半
導体チップ1とを仮止め接着する。ここで、接着剤4の
仮硬化とは、硬化反応が初期段階で止まっている状態で
あり、仮止め接着とは、接着剤4が仮硬化することによ
り接着されている状態をいう。
In the step shown in FIG. 1A, the paste type adhesive 4 is applied on the printed wiring board 2 at room temperature.
After applying, the semiconductor chip 1 is mounted. Then 1
The adhesive 4 is temporarily cured by performing in-line curing for several tens of seconds to several minutes at 00 to 250 ° C., and the printed wiring board 2 and the semiconductor chip 1 are temporarily fixed and bonded. Here, the temporary curing of the adhesive 4 is a state in which the curing reaction is stopped at the initial stage, and the temporary fixing adhesion is a state in which the adhesive 4 is adhered by being temporarily cured.

【0059】図1(b)に示す工程においては、プリン
ト配線板2の上にフィルムタイプの接着剤4を、50〜
150℃で数秒間保持して熱圧着する。そして、半導体
チップ1を搭載して、100〜200℃で数秒間保持す
ることにより、接着剤4を仮硬化させ、プリント配線板
2と半導体チップ1とを仮止め接着する。
In the step shown in FIG. 1B, the film type adhesive 4 is applied to the printed wiring board 2 in an amount of 50 to 50%.
Hold at 150 ° C. for several seconds and perform thermocompression bonding. Then, the semiconductor chip 1 is mounted and held at 100 to 200 [deg.] C. for several seconds to temporarily cure the adhesive 4 and temporarily bond the printed wiring board 2 and the semiconductor chip 1 together.

【0060】図1(c)に示す工程においては、あらか
じめフィルムタイプの接着材4が貼りついている半導体
チップ1をプリント配線板2の上に搭載した後、100
〜200℃で数秒間保持することにより、プリント配線
板2と半導体チップ1とを仮止め接着する。
In the step shown in FIG. 1C, after mounting the semiconductor chip 1 to which the film type adhesive material 4 is attached in advance on the printed wiring board 2, 100
The printed wiring board 2 and the semiconductor chip 1 are temporarily fixed to each other by holding at a temperature of up to 200 ° C. for several seconds.

【0061】ここで、上記のそれぞれのダイボンド方法
の技術的な意義について説明する。
Here, the technical significance of each of the above die-bonding methods will be described.

【0062】図1(a)において用いたペーストタイプ
の接着剤は、フィルムタイプの接着剤よりコストが大幅
に低いという長所がある。
The paste type adhesive used in FIG. 1 (a) has an advantage that the cost is significantly lower than that of the film type adhesive.

【0063】図1(b),(c)において用いたフィル
ムタイプの接着剤では、ペーストタイプの接着剤とは異
なって、低温で保管して使用時には常温に戻し、攪拌し
て粘度を調整するという作業が不必要である。さらに、
接着面への塗布が必要でないため、エア巻き込みによる
ボイドを根絶できる。
Unlike the paste type adhesive, the film type adhesive used in FIGS. 1 (b) and 1 (c) is stored at a low temperature, returned to room temperature when used, and stirred to adjust the viscosity. Work is unnecessary. further,
Since it is not necessary to apply it to the adhesive surface, voids due to air entrapment can be eliminated.

【0064】また、フィルムタイプの接着剤を用いた場
合には、ダイボンド後において、接着剤が半導体チップ
の外部に延びる濡れ広がりの面積のコントロールが容易
である。特に、あらかじめ接着剤を半導体チップの裏面
に貼り付ける方法(図1(c))では、ウエハに接着剤
を貼り付けた後にウエハ上の半導体チップを切り出すの
で、接着剤のサイズが半導体チップのサイズと同一とな
り、濡れ広がりがほとんど発生しない。
Further, when a film type adhesive is used, it is easy to control the area of the wet extension of the adhesive extending outside the semiconductor chip after die bonding. Particularly, in the method of attaching the adhesive to the back surface of the semiconductor chip in advance (FIG. 1C), since the semiconductor chip on the wafer is cut out after the adhesive is attached to the wafer, the size of the adhesive is the size of the semiconductor chip. Is almost the same, and almost no wetting and spreading occurs.

【0065】このように、多種のダイボンド方法がある
が、どのタイプの接着剤を選択し、どの貼り付け方法を
選択するかは、要求されている品質やコストにより決定
される。尚、接着剤4の材料としてはエポキシ系樹脂が
挙げられる。
As described above, although there are various die bonding methods, which type of adhesive is selected and which bonding method is selected depend on the required quality and cost. An epoxy resin can be used as the material of the adhesive 4.

【0066】次に、図2(a)に示す工程(ワイヤボン
ド工程)で、ワイヤ3によって、半導体チップ1と、プ
リント配線板2における内部接続用ランド2aとを接続
する。ここで、ワイヤ3の接合方法としては、被着体を
加熱して、加圧と超音波振動とを併用して接合する方法
が一般的である。
Next, in a step (wire bonding step) shown in FIG. 2A, the semiconductor chip 1 and the internal connection land 2a in the printed wiring board 2 are connected by the wire 3. Here, as a method of joining the wires 3, a method of heating an adherend and jointly using pressure and ultrasonic vibration is generally used.

【0067】次に、図2(b)に示す工程(封止工程)
で、160〜190℃に加熱した上部金型20aと下部
金型20bとの間に、これまで組み立てた半導体装置を
把持して、封止樹脂5をトランスファ注入する。注入終
了後、160〜190℃で30秒から2分の間保持して
熱処理を行なうことにより、封止樹脂5を所定の程度ま
で硬化させる。この硬化は、金型から封止済みの半導体
装置を取り出す際に、封止樹脂5の硬化不足により破損
しない程度まで硬化させる。このとき、仮硬化状態にあ
った接着剤4も所定の程度まで硬化する。
Next, the step shown in FIG. 2B (sealing step)
Then, the semiconductor device assembled so far is held between the upper mold 20a and the lower mold 20b heated to 160 to 190 ° C., and the sealing resin 5 is transfer-injected. After the completion of the injection, the sealing resin 5 is cured to a predetermined degree by performing a heat treatment by holding at 160 to 190 ° C. for 30 seconds to 2 minutes. This curing is performed to such an extent that the sealing resin 5 is not sufficiently cured when the semiconductor device that has been sealed is taken out from the mold, so that the sealing resin 5 is not damaged. At this time, the adhesive 4 that was in the temporarily cured state is also cured to a predetermined degree.

【0068】この熱処理の時に、樹脂の注入時に混入し
たエアーを押し潰すために、50kgf/cm2 から2
50kgf/cm2 程度の圧力を封止樹脂5にかける。
この圧力は、半導体チップ1及びプリント配線板2を下
部金型20bに押しつける静水圧としても作用するた
め、半導体チップ1およびプリント配線板2の反りは平
らな状態に矯正され、同時に接着剤4の界面の濡れ不足
領域や接着剤4内部に発生しているボイドは潰し込まれ
る。この状態で封止樹脂5と接着剤4とを硬化させるた
め、均一でかつ濡れ不足領域のない強固な接着界面を得
ることができる。
At the time of this heat treatment, 50 kgf / cm 2 to 2 kg is used to crush the air mixed in at the time of injecting the resin.
A pressure of about 50 kgf / cm 2 is applied to the sealing resin 5.
This pressure also acts as a hydrostatic pressure that presses the semiconductor chip 1 and the printed wiring board 2 against the lower mold 20b, so that the warpage of the semiconductor chip 1 and the printed wiring board 2 is corrected to a flat state, and at the same time, the adhesive 4 Voids occurring in the interface underwetting region and inside the adhesive 4 are crushed. Since the sealing resin 5 and the adhesive 4 are cured in this state, it is possible to obtain a uniform and strong adhesive interface without an insufficient wetting region.

【0069】次に、図2(c)に示す工程(アフターキ
ュア工程)で、半導体装置をオーブン9に投入して16
0〜190℃で3〜8時間保持して熱処理を行なうこと
により、封止樹脂5と接着剤4とを完全硬化させる。接
着剤4の完全硬化のためには、一般に150〜180℃
で30分から1時間の熱処理を行なうことが好ましく、
接着剤4もアフターキュア工程において完全に硬化され
る。以上の工程によって、本実施形態における半導体装
置の製造が完了する。ここで、金属ボールを取り付ける
工程は省いている。
Next, in the step (after-cure step) shown in FIG.
The sealing resin 5 and the adhesive 4 are completely cured by holding them at 0 to 190 ° C. for 3 to 8 hours for heat treatment. For complete curing of the adhesive 4, generally 150 to 180 ° C
It is preferable to perform heat treatment for 30 minutes to 1 hour at
The adhesive 4 is also completely cured in the after-curing process. Through the above steps, the manufacturing of the semiconductor device in this embodiment is completed. Here, the step of attaching the metal balls is omitted.

【0070】本実施形態によって得られる効果を確認す
るため、樹脂封止後の半導体装置を断面研磨して、接着
剤4の状態を観察した。その結果、従来のダイボンドキ
ュア工程を含む製造方法では濡れ不足領域やボイドが多
数発生していたが、本実施形態による製造方法ではそれ
らが消滅し、従来と比較して均一な接着界面が形成され
ていることが分かった。
In order to confirm the effect obtained by this embodiment, the semiconductor device after resin sealing was cross-section polished and the state of the adhesive 4 was observed. As a result, a number of insufficient wetting regions and voids were generated in the conventional manufacturing method including the die bond curing step, but they disappeared in the manufacturing method according to the present embodiment, and a uniform adhesive interface was formed as compared with the conventional method. I found out.

【0071】つまり、本実施形態の製造方法によれば、
半導体チップ1とプリント配線板2との接着強度を従来
の製造方法による場合と比較して高めることができるた
め、半導体装置の信頼性を向上させることができる。
That is, according to the manufacturing method of the present embodiment,
Since the adhesive strength between the semiconductor chip 1 and the printed wiring board 2 can be increased as compared with the case of the conventional manufacturing method, the reliability of the semiconductor device can be improved.

【0072】また、従来の製造方法において必要である
ダイボンドキュア工程を省くことができ、製造工程を簡
略化して生産性の向上を図ることができる。
Further, it is possible to omit the die bond curing step, which is necessary in the conventional manufacturing method, simplify the manufacturing process, and improve the productivity.

【0073】また、接着剤4および封止樹脂5は、図2
(c)に示す工程において完全硬化してもよいし、接着
剤4および封止樹脂5のうちの少なくともいずれかが、
図2(b)に示す工程において完全硬化してもよい。つ
まり、図2(b)の工程を開始する際に、接着剤4が仮
硬化の状態であり、図2(b)の工程が終了する際に、
接着剤4が濡れ不足領域のない状態でほぼ硬化しておれ
ば、密着性の向上を図ることができる。
The adhesive 4 and the sealing resin 5 are the same as those shown in FIG.
It may be completely cured in the step shown in (c), or at least one of the adhesive 4 and the sealing resin 5 is
It may be completely cured in the step shown in FIG. That is, when the step of FIG. 2B is started, the adhesive 4 is in a temporarily cured state, and when the step of FIG.
If the adhesive 4 is almost cured without the insufficient wetting area, the adhesiveness can be improved.

【0074】なお、図1(a)〜図2(c)に示す工程
においては省略されているが、ワイヤボンド工程でのワ
イヤの接合性の向上や、封止樹脂との密着性の向上を目
的として、プラズマクリーニング工程をダイボンド後や
ワイヤボンド後に挿入することは、接着剤4の熱硬化に
直接影響しないため、可能である。
Although omitted in the steps shown in FIGS. 1A to 2C, it is possible to improve the wire bondability in the wire bonding step and the adhesion with the sealing resin. For the purpose, it is possible to insert the plasma cleaning step after die bonding or wire bonding, since it does not directly affect the thermal curing of the adhesive 4.

【0075】(第2の実施形態)図3(a)〜図4
(c)は、第2の実施形態における半導体装置の製造工
程を示す断面図である。図4(c)に示すように、本実
施形態の半導体装置においては、2個の半導体チップが
積層されており、半導体チップとプリント配線板との電
気的接続にワイヤが使用されている。なお、図3(a)
〜(c)に示す工程の前には、図1(a)〜(c)に示
すような工程(ダイボンド工程)によって、半導体チッ
プ1がプリント配線板2の上に仮止め接着されている。
(Second Embodiment) FIGS. 3A to 4
FIG. 6C is a sectional view showing a manufacturing process of the semiconductor device according to the second embodiment. As shown in FIG. 4C, in the semiconductor device of this embodiment, two semiconductor chips are stacked and a wire is used for electrical connection between the semiconductor chip and the printed wiring board. In addition, FIG.
Before the steps shown in FIGS. 1A to 1C, the semiconductor chip 1 is temporarily adhered onto the printed wiring board 2 by the steps shown in FIGS. 1A to 1C (die bonding step).

【0076】まず、図3(a)〜(c)に示す工程で、
半導体チップ1の上に、第2半導体チップ11を第2接
着剤14によって仮接着する。ここで、図3(a)〜
(c)に示す接着の方法としては、図1(a)〜(c)
に示すような3つの方法があり、ここでは説明を省略す
る。ここで、第2接着剤14は仮硬化の状態にし、半導
体チップ1と第2半導体チップ11とは、仮止め接着状
態にしておく。
First, in the steps shown in FIGS.
The second semiconductor chip 11 is temporarily adhered onto the semiconductor chip 1 with the second adhesive 14. Here, FIG.
As the bonding method shown in (c), there are shown in FIGS.
There are three methods as shown in, and the description is omitted here. Here, the second adhesive 14 is in a temporarily cured state, and the semiconductor chip 1 and the second semiconductor chip 11 are in a temporarily bonded state.

【0077】次に、図4(a)に示す工程(ワイヤボン
ド工程)で、ワイヤ3を用いて、半導体チップ1とプリ
ント配線板2における内部接続用ランド2aとを接続す
る。その後、ワイヤ13を用いて、第2半導体チップ1
1と内部接続用ランド2aとを接続する。この接続順序
を逆にすると、半導体チップ1のワイヤボンド時に、ワ
イヤ3を繰り出すツールが第2半導体チップ11のワイ
ヤ3に接触して不良の原因となる可能性がある。またワ
イヤ3とワイヤ13とが接触しないように、ワイヤ3と
ワイヤ13とでは、ループ形状を変えることが好まし
い。
Next, in the step (wire bonding step) shown in FIG. 4A, the wire 3 is used to connect the semiconductor chip 1 to the internal connection land 2a in the printed wiring board 2. Then, using the wire 13, the second semiconductor chip 1
1 and the land 2a for internal connection are connected. If the connection order is reversed, the tool for feeding the wire 3 may come into contact with the wire 3 of the second semiconductor chip 11 during wire bonding of the semiconductor chip 1 and cause a defect. Further, it is preferable that the wire 3 and the wire 13 have different loop shapes so that the wire 3 and the wire 13 do not come into contact with each other.

【0078】次に、図4(b)に示す工程(封止工程)
に移る。160〜190℃に加熱した上部金型20aと
下部金型20bとの間にこれまで組み立てた半導体装置
を把持し、封止樹脂5をトランスファ注入する。注入終
了後、160〜190℃で30秒から2分の間保持して
熱処理を行なうことにより、半導体装置上を覆う封止樹
脂5を所定の程度まで硬化する。この硬化は、金型から
封止済みの半導体装置を取り出す際に、封止樹脂5の硬
化不足により破損しない程度まで硬化させる。このと
き、仮硬化状態にあった接着剤4および第2接着剤14
も所定の程度まで硬化する。
Next, the step shown in FIG. 4B (sealing step)
Move on to. The semiconductor device assembled so far is held between the upper mold 20a and the lower mold 20b heated to 160 to 190 ° C., and the sealing resin 5 is transfer-injected. After the completion of the injection, the sealing resin 5 covering the semiconductor device is cured to a predetermined degree by performing heat treatment by holding at 160 to 190 ° C. for 30 seconds to 2 minutes. This curing is performed to such an extent that the sealing resin 5 is not sufficiently cured when the semiconductor device that has been sealed is taken out from the mold, so that the sealing resin 5 is not damaged. At this time, the adhesive 4 and the second adhesive 14 that were in the temporarily cured state
Also cures to a certain extent.

【0079】この熱処理の時に、樹脂の注入時に混入し
たエアーを押し潰すために、50kgf/cm2 から2
50kgf/cm2 程度の圧力を封止樹脂5にかける。
この圧力は、半導体チップ1,第2半導体チップ11お
よびプリント配線板2を下部金型20bに押しつける静
水圧としても作用するため、半導体チップ1,第2半導
体チップ11およびプリント配線板2の反りは平らな状
態に矯正される。また同時に、接着剤4および第2接着
剤14のそれぞれの界面に発生している濡れ不足領域や
内部のボイドは潰し込まれる。この状態で封止樹脂5,
接着剤4および第2接着剤14とを硬化させるため、均
一で濡れ不足のない強固な接着界面を得ることができ
る。
At the time of this heat treatment, 50 kgf / cm 2 to 2 kg is used in order to crush the air mixed in at the time of injecting the resin.
A pressure of about 50 kgf / cm 2 is applied to the sealing resin 5.
This pressure also acts as hydrostatic pressure that presses the semiconductor chip 1, the second semiconductor chip 11 and the printed wiring board 2 against the lower die 20b, so that the warpage of the semiconductor chip 1, the second semiconductor chip 11 and the printed wiring board 2 is prevented. It is corrected to a flat state. At the same time, the insufficient wetting region and voids inside the adhesive 4 and the second adhesive 14 are collapsed. In this state, the sealing resin 5,
Since the adhesive 4 and the second adhesive 14 are cured, it is possible to obtain a uniform and strong adhesive interface without insufficient wetting.

【0080】次に、図4(c)に示す工程(アフターキ
ュア工程)で、半導体装置をオーブン9に投入して16
0〜190℃で3〜8時間保持して熱処理を行なうこと
により、封止樹脂5,接着剤4および第2接着剤14を
完全硬化させる。接着剤4,第2接着剤14の完全硬化
のためには、一般に、150℃から180℃で30分か
ら1時間の熱処理を行なうことが好ましく、接着剤4お
よび第2接着剤14も、アフターキュア工程において完
全硬化される。以上の工程によって、本実施形態におけ
る半導体装置の製造が完了する。
Next, in the step (after-cure step) shown in FIG.
The sealing resin 5, the adhesive 4, and the second adhesive 14 are completely cured by holding them at 0 to 190 ° C. for 3 to 8 hours for heat treatment. In order to completely cure the adhesive 4 and the second adhesive 14, it is generally preferable to perform heat treatment at 150 ° C. to 180 ° C. for 30 minutes to 1 hour. The adhesive 4 and the second adhesive 14 are also after-cured. It is completely cured in the process. Through the above steps, the manufacturing of the semiconductor device in this embodiment is completed.

【0081】本実施形態においては、半導体チップ1と
プリント配線板2との接着強度および積層した半導体チ
ップ間の接着強度を従来の製造方法に比べて高めること
ができるため、半導体装置の信頼性を向上できる。製造
工程の簡略化においては、接着剤4と第2接着剤14と
のそれぞれに対するダイボンドキュア工程を行わずにす
むので、第1の実施形態と比べて、さらに大きい効果が
得られる。
In the present embodiment, the bonding strength between the semiconductor chip 1 and the printed wiring board 2 and the bonding strength between the stacked semiconductor chips can be increased as compared with the conventional manufacturing method, so that the reliability of the semiconductor device is improved. Can be improved. In the simplification of the manufacturing process, it is not necessary to perform the die bond curing process for each of the adhesive 4 and the second adhesive 14, and therefore, a larger effect can be obtained as compared with the first embodiment.

【0082】なお、本実施形態において、接着剤4と第
2接着剤14とは、作業上同じ種類のものであることが
好ましい。しかし、要求される品質によって、それらが
別種であってもかまわない。
In this embodiment, the adhesive 4 and the second adhesive 14 are preferably of the same type in terms of work. However, they may be different species, depending on the quality required.

【0083】また、本実施形態においては、接着剤4を
ほぼ完全に硬化させる工程を経てから、図4(b),
(c)に示す工程において、第2接着剤14と封止樹脂
5とを硬化させても、プリント配線板2の反りを矯正す
ることができ、第2接着剤14の密着性を高めることが
できる。
Further, in this embodiment, after the step of curing the adhesive 4 almost completely, the process shown in FIG.
In the step shown in (c), even if the second adhesive 14 and the sealing resin 5 are cured, the warp of the printed wiring board 2 can be corrected and the adhesion of the second adhesive 14 can be improved. it can.

【0084】なお、図3(a)〜図4(c)に示す工程
においては省略されているが、ワイヤボンド工程でのワ
イヤの接合性の向上や、封止樹脂との密着性の向上を目
的として、プラズマクリーニング工程をダイボンド後や
ワイヤボンド後に挿入することは、接着剤の硬化に直接
影響しないため、可能である。
Although omitted in the steps shown in FIGS. 3 (a) to 4 (c), it is possible to improve the wire bondability in the wire bonding step and the adhesion with the sealing resin. For the purpose, it is possible to insert the plasma cleaning step after die bonding or wire bonding, since it does not directly affect the curing of the adhesive.

【0085】(第3の実施形態)図5(a)〜図6
(c)は、第3の実施形態における半導体装置の製造工
程を示す断面図である。図6(c)に示すように、本実
施形態の半導体装置においては、2個の半導体チップが
積層されており、半導体チップ同士の電気的接続にバン
プが使用されている。なお、図5(a)〜(c)に示す
工程の前には、図1(a)〜(c)に示すような工程
(ダイボンド工程)によって、半導体チップ1がプリン
ト配線板2の上に仮止め接着されている。
(Third Embodiment) FIGS. 5A to 6
FIG. 7C is a sectional view showing a manufacturing process of the semiconductor device according to the third embodiment. As shown in FIG. 6C, in the semiconductor device of this embodiment, two semiconductor chips are stacked and bumps are used for electrical connection between the semiconductor chips. Before the steps shown in FIGS. 5A to 5C, the semiconductor chip 1 is placed on the printed wiring board 2 by the steps shown in FIGS. 1A to 1C (die bonding step). Temporarily bonded.

【0086】まず、図5(a)〜(c)に示す工程で、
半導体チップ1の上に、第2半導体チップ11を第2接
着剤14によってフェイスダウン方式で仮接着する。こ
こで、図1(a)〜(c)のうちのいずれかの工程が選
択される。
First, in the steps shown in FIGS.
The second semiconductor chip 11 is temporarily bonded onto the semiconductor chip 1 by the second adhesive 14 in a face-down manner. Here, one of the steps in FIGS. 1A to 1C is selected.

【0087】一方の半導体チップ上に形成したバンプ8
を、他方の半導体チップに接続する順番には、第2接着
剤14の載置の前に行う方法と、後に行なう方法とがあ
る。また、バンプ8を形成する半導体チップは、半導体
チップ1の場合と、第2半導体チップ11の場合と、半
導体チップ1と第2半導体チップ11との両方の場合と
がある。ここでは、あらかじめ一方の半導体チップにバ
ンプ8を形成し、それを他の半導体チップに接続する工
程を、第2接着剤14の載置の後に行なう方法を例とし
て述べるが、本発明においては他の方法も適用できる。
Bump 8 formed on one semiconductor chip
The order of connecting to the other semiconductor chip includes a method of performing before the placement of the second adhesive 14 and a method of performing after. The semiconductor chip forming the bump 8 may be the semiconductor chip 1, the second semiconductor chip 11, or both the semiconductor chip 1 and the second semiconductor chip 11. Here, a method of forming the bump 8 on one semiconductor chip in advance and connecting it to another semiconductor chip after the mounting of the second adhesive 14 is described as an example. The method of can also be applied.

【0088】図5(a)に示す工程においては、常温下
で、半導体チップ1の上に、ペーストタイプの第2接着
剤14を塗布した後、あらかじめ第2半導体チップ11
に形成したバンプ8が下を向くよう(フェイスダウン方
式)に第2半導体チップ11を搭載する。このとき、第
2半導体チップ12は、所定の第1半導体チップと向か
いあわせでバンプの位置が整合するようにその搭載位置
をアライメントする。その後、100〜250℃で、数
十秒〜数分程度のインラインキュアを行なって、第2接
着剤14を仮硬化させる。
In the step shown in FIG. 5A, after the paste type second adhesive 14 is applied on the semiconductor chip 1 at room temperature, the second semiconductor chip 11 is preliminarily prepared.
The second semiconductor chip 11 is mounted so that the bumps 8 formed in (1) face downward (face-down method). At this time, the mounting position of the second semiconductor chip 12 is aligned so that the bump positions match with the predetermined first semiconductor chip. After that, in-line curing is performed at 100 to 250 ° C. for several tens of seconds to several minutes to temporarily cure the second adhesive 14.

【0089】図5(b)に示す工程においては、常温下
で、半導体チップ1の上に、ペーストタイプの第2接着
剤14を塗布した後、第2半導体チップ11を下向き
(フェイスダウン方式)に搭載する。ここで、半導体チ
ップ1には、あらかじめバンプ8が形成されており、第
2半導体チップ11が半導体チップ1のバンプの位置と
整合するように第2半導体チップ11の位置をアライメ
ントする。その後、100〜250℃で、数十秒〜数分
程度のインラインキュアを行なって、第2接着剤14を
仮硬化させる。
In the step shown in FIG. 5B, after the paste type second adhesive 14 is applied on the semiconductor chip 1 at room temperature, the second semiconductor chip 11 is faced down (face down method). To be installed on. Here, the bumps 8 are formed in advance on the semiconductor chip 1, and the positions of the second semiconductor chips 11 are aligned so that the second semiconductor chips 11 are aligned with the positions of the bumps of the semiconductor chips 1. After that, in-line curing is performed at 100 to 250 ° C. for several tens of seconds to several minutes to temporarily cure the second adhesive 14.

【0090】図5(c)に示す工程においては、半導体
チップ1の上にフィルムタイプの第2接着剤14を、5
0〜150℃で数秒間保持して熱圧着する。その上に、
第2半導体チップ11を下向き(フェイスダウン方式)
に搭載して、100〜200℃で数秒間保持して熱圧着
する。このとき、第2半導体チップ11にはあらかじめ
バンプ8が形成されており、このバンプ8と半導体チッ
プ1との位置が整合するように第2半導体チップ11の
搭載位置をアライメントする。そして、熱圧着を行なう
ときには、バンプ8が第2接着剤14を貫通して半導体
チップ1と完全なコンタクトが取れる程度の圧力を第2
半導体チップ11に加えて第2接着剤14を仮硬化させ
る。
In the step shown in FIG. 5C, the film type second adhesive 14 is applied on the semiconductor chip 1 by 5
Hold at 0 to 150 ° C. for several seconds and perform thermocompression bonding. in addition,
Second semiconductor chip 11 facing down (face-down method)
And then thermocompression bonded by holding at 100 to 200 ° C. for several seconds. At this time, the bumps 8 are formed in advance on the second semiconductor chip 11, and the mounting position of the second semiconductor chip 11 is aligned so that the bumps 8 and the semiconductor chip 1 are aligned with each other. Then, when thermocompression bonding is performed, the second pressure is set so that the bumps 8 penetrate the second adhesive 14 and complete contact with the semiconductor chip 1 is made.
In addition to the semiconductor chip 11, the second adhesive 14 is temporarily hardened.

【0091】ここで、バンプ8の形成方法としては、印
刷法、マスク蒸着法、ワイヤボンディング法、めっき
法、転写法等がある。バンプ8の材質としては、Ag、
Au、Cu、ハンダ等がある。また、第2接着剤14と
しては、エポキシ系樹脂によるペーストもしくはフィル
ムの他に、エポキシ系樹脂の内部に導電粒子を分散させ
た異方性導電ペーストもしくは異方性導電フィルムを使
用することができる。
Here, as the method of forming the bumps 8, there are a printing method, a mask vapor deposition method, a wire bonding method, a plating method, a transfer method and the like. The material of the bump 8 is Ag,
There are Au, Cu, solder and the like. Further, as the second adhesive 14, in addition to a paste or film made of an epoxy resin, an anisotropic conductive paste or an anisotropic conductive film in which conductive particles are dispersed in an epoxy resin can be used. .

【0092】次に、図6(a)に示す工程(ワイヤボン
ド工程)で、半導体チップ1と、プリント配線板2の内
部接続用ランド2aとを、ワイヤ3によって電気的に接
続する。
Next, in the step (wire bonding step) shown in FIG. 6A, the semiconductor chip 1 and the internal connection lands 2a of the printed wiring board 2 are electrically connected by the wires 3.

【0093】次に、図6(b)に示す工程(封止工程)
で、160〜190℃に熱した上部金型20aと下部金
型20bとの間にこれまで組み立てた(ワイヤボンド後
の)半導体装置を把持し、その所定の空間に、封止樹脂
5をトランスファ注入する。注入終了後、160〜19
0℃で30秒から2分の間保持して熱処理を行なうこと
により、封止樹脂5を所定の程度まで硬化する。この硬
化は、金型から封止済みの半導体装置を取り出す際に、
封止樹脂5の硬化不足により破損しない程度まで硬化さ
せる。このとき、仮硬化状態にあった接着剤4および第
2接着剤14も所定の程度まで硬化する。
Next, the step (sealing step) shown in FIG. 6B.
Then, the semiconductor device assembled up to now (after wire bonding) is held between the upper mold 20a and the lower mold 20b heated to 160 to 190 ° C., and the sealing resin 5 is transferred to the predetermined space. inject. 160 ~ 19 after injection
The encapsulating resin 5 is cured to a predetermined degree by performing a heat treatment by holding it at 0 ° C. for 30 seconds to 2 minutes. This curing is performed when taking out the sealed semiconductor device from the mold.
The sealing resin 5 is cured to such an extent that it is not damaged due to insufficient curing. At this time, the adhesive 4 and the second adhesive 14 that were in the temporarily cured state are also cured to a predetermined degree.

【0094】この熱処理の時に、樹脂の注入時に混入し
たエアーを押し潰すために、50kgf/cm2 から2
50kgf/cm2 程度の圧力を封止樹脂5にかける。
この圧力は、半導体チップ1,第2半導体チップ11お
よびプリント配線板2を下部金型20bに押しつける静
水圧としても作用するため、半導体チップ1,第2半導
体チップ11およびプリント配線板2の反りは平らな状
態に矯正される。また同時に、接着剤4および第2接着
剤14それぞれの界面に発生している濡れ不足領域や内
部に発生しているボイドは潰し込まれる。この状態で封
止樹脂5,接着剤4および第2接着剤14とを硬化させ
るため、均一でかつ濡れ不足領域のない強固な接着界面
を得ることができる。
At the time of this heat treatment, 50 kgf / cm 2 to 2 kg was used in order to crush the air mixed during the injection of the resin.
A pressure of about 50 kgf / cm 2 is applied to the sealing resin 5.
This pressure also acts as hydrostatic pressure that presses the semiconductor chip 1, the second semiconductor chip 11 and the printed wiring board 2 against the lower die 20b, so that the warpage of the semiconductor chip 1, the second semiconductor chip 11 and the printed wiring board 2 does not occur. It is corrected to a flat state. At the same time, the insufficient wetting region generated at the interface between the adhesive 4 and the second adhesive 14 and the voids generated inside are crushed. In this state, the sealing resin 5, the adhesive 4 and the second adhesive 14 are cured, so that a uniform and strong adhesive interface without an insufficient wetting region can be obtained.

【0095】次に、図6(c)に示す工程(アフターキ
ュア工程)で、封止工程後の半導体装置をオーブン9に
投入して160〜190℃で3〜8時間保持して熱処理
を行うことにより、封止樹脂5,接着剤4および第2接
着剤14を完全硬化させる。以上の工程により、本実施
形態の半導体装置の製造が完了する。
Next, in the step (after-cure step) shown in FIG. 6C, the semiconductor device after the sealing step is put into an oven 9 and held at 160 to 190 ° C. for 3 to 8 hours for heat treatment. Thus, the sealing resin 5, the adhesive 4 and the second adhesive 14 are completely cured. Through the above steps, the manufacture of the semiconductor device of this embodiment is completed.

【0096】本実施形態においては、半導体チップ1と
プリント配線板2との接着強度および半導体チップ1と
第2半導体チップ11との接着強度を、従来の製造方法
に比べて高めることができるため、半導体装置の信頼性
を向上できる。また、工程の簡略化を図ることも可能と
なる。
In this embodiment, the adhesive strength between the semiconductor chip 1 and the printed wiring board 2 and the adhesive strength between the semiconductor chip 1 and the second semiconductor chip 11 can be increased as compared with the conventional manufacturing method. The reliability of the semiconductor device can be improved. It is also possible to simplify the process.

【0097】さらに本実施形態では、第2半導体チップ
11が、バンプ8を挟んで半導体チップ1に押し付けら
れた状態で封止樹脂5および第2接着剤14が硬化する
ため、バンプ8の接合が強固になり、電気的接続の信頼
性を向上させることができる。
Further, in the present embodiment, the sealing resin 5 and the second adhesive 14 are hardened in a state where the second semiconductor chip 11 is pressed against the semiconductor chip 1 with the bumps 8 interposed therebetween, so that the bumps 8 are joined together. It becomes stronger and the reliability of electrical connection can be improved.

【0098】一般的に、接着剤により接着されている領
域にバンプが含まれていると、接着剤の濡れ不足による
下地と半導体チップとの密着性の低下が、半導体チップ
の電気的接続を直接悪化させる。そのため、本発明を適
用して密着性を向上させることは極めて有効である。
Generally, if bumps are included in the region bonded by the adhesive, the adhesiveness between the base and the semiconductor chip is deteriorated due to insufficient wetting of the adhesive, and the electrical connection of the semiconductor chip is directly caused. make worse. Therefore, it is extremely effective to apply the present invention to improve the adhesion.

【0099】なお、本実施形態において、接着剤4と第
2接着剤14とは、作業上同じ種類のものであることが
好ましい。しかし、要求される品質によって、それらが
別種であってもかまわない。
In the present embodiment, the adhesive 4 and the second adhesive 14 are preferably of the same type in terms of work. However, they may be different species, depending on the quality required.

【0100】また、本実施形態においては、接着剤4を
ほぼ完全に硬化させる工程を経てから、図6(b),
(c)に示す工程において、第2接着剤14と封止樹脂
5とを硬化させても、プリント配線板2の反りを矯正す
ることができ、第2接着剤14の接着強度を高めること
ができる。
In addition, in this embodiment, after the step of curing the adhesive 4 almost completely, the process shown in FIG.
In the step shown in (c), even if the second adhesive 14 and the sealing resin 5 are cured, the warp of the printed wiring board 2 can be corrected and the adhesive strength of the second adhesive 14 can be increased. it can.

【0101】なお、図5(a)〜図6(c)に示す工程
においては省略されているが、ワイヤボンド工程でのワ
イヤの接合性の向上や、封止樹脂との密着性の向上を目
的として、プラズマクリーニング工程をダイボンド後や
ワイヤボンド後に挿入することは、接着剤の硬化には直
接影響しないため、可能である。
Although omitted in the steps shown in FIGS. 5A to 6C, it is possible to improve the wire bondability in the wire bonding step and the adhesion with the sealing resin. For the purpose, it is possible to insert the plasma cleaning step after die bonding or wire bonding, since it does not directly affect the curing of the adhesive.

【0102】(その他の実施形態)本発明は、図8
(a)に示すような構造にも適用することができる。図
8(a)に示す構造においては、プリント配線板102
の上に2個の半導体チップが積層されており、プリント
配線板102と半導体チップ101との電気的接続にバ
ンプ108が使用されている。
(Other Embodiments) The present invention is shown in FIG.
It can also be applied to the structure shown in FIG. In the structure shown in FIG. 8A, the printed wiring board 102 is
Two semiconductor chips are stacked on top of each other, and bumps 108 are used for electrical connection between the printed wiring board 102 and the semiconductor chip 101.

【0103】この場合には、プリント配線板102と半
導体チップ101とを接着する接着剤104および半導
体チップ101と第2半導体チップ111とを接着する
第2接着剤114とを完全硬化させる工程として、第3
の実施形態で述べた封止工程およびアフターキュア工程
を用いればよい。すると、プリント配線板101の反り
を矯正して半導体チップ101とプリント配線板102
との接着強度および半導体チップ101と第2半導体チ
ップ111との接着強度の向上を図ることができ、また
工程の簡略化も可能となる。
In this case, as a step of completely curing the adhesive 104 for adhering the printed wiring board 102 and the semiconductor chip 101 and the second adhesive 114 for adhering the semiconductor chip 101 and the second semiconductor chip 111, Third
The sealing process and the after-curing process described in the above embodiment may be used. Then, the warp of the printed wiring board 101 is corrected to correct the semiconductor chip 101 and the printed wiring board 102.
The adhesive strength between the semiconductor chip 101 and the second semiconductor chip 111 can be improved, and the process can be simplified.

【0104】本発明は、図7(a)に示すような構造に
おいて、半導体チップ101をプリント配線板102に
フェイスダウン方式で搭載し、その両者の電気的接続に
バンプを用いる場合にも適用することができる。
The present invention is also applied to the case where the semiconductor chip 101 is mounted on the printed wiring board 102 in a face-down manner in the structure as shown in FIG. 7A, and the bumps are used for electrical connection between the both. be able to.

【0105】本発明は、図7(c)に示すような構造に
も適用することができる。また、図7(c)に示す構造
において、半導体チップ101をプリント配線板102
にフェイスダウン方式で搭載し、その両者の電気的接続
にバンプを用いる場合にも適用することができる。
The present invention can also be applied to the structure shown in FIG. 7 (c). Further, in the structure shown in FIG. 7C, the semiconductor chip 101 is connected to the printed wiring board 102.
It can also be applied to the case where the components are mounted in a face-down manner and the bumps are used for electrical connection between the both.

【0106】上記実施形態で示したプリント配線板に
は、導体を保護するソルダーレジストを示していない
が、本発明の効果は、ソルダーレジストの有無に関係な
く発揮されるため、本発明はソルダーレジストを設けた
プリント配線板に適用することも可能である。
Although the printed wiring board shown in the above embodiment does not show a solder resist for protecting the conductor, the effect of the present invention is exerted regardless of the presence or absence of the solder resist. It is also possible to apply to a printed wiring board provided with.

【0107】また、上記実施形態においては、下地がリ
ジットな有機プリント配線板2である場合について述べ
たが、本発明においては、下地として、例えばセラミッ
ク基板やフレキシブル配線板を用いても同様の効果を得
ることができる。
Further, in the above embodiment, the case where the base is the rigid organic printed wiring board 2 is described, but in the present invention, the same effect can be obtained even if a ceramic substrate or a flexible wiring board is used as the base. Can be obtained.

【0108】[0108]

【発明の効果】本発明の半導体装置の製造方法によれ
ば、接着剤の硬化を、封止工程において、封止樹脂への
圧力の印加のもと、封止樹脂の硬化と同時に行う。これ
により、樹脂封止の圧力が半導体チップと支持体とを押
しつける静水圧として作用するため、支持体の反りを矯
正して接着剤界面の濡れ不足領域の削減、および接着剤
内部のボイドの抑制が可能となる。従って、支持体と半
導体チップとの密着性の向上を図ることができるので、
信頼性の高い半導体装置を得ることができる。また、工
程の簡略化が可能となる。
According to the method of manufacturing a semiconductor device of the present invention, the curing of the adhesive is performed simultaneously with the curing of the sealing resin under the application of pressure to the sealing resin in the sealing step. As a result, the resin sealing pressure acts as a hydrostatic pressure that presses the semiconductor chip and the support, so that the warp of the support is corrected to reduce the insufficient wetting area at the adhesive interface, and to suppress voids inside the adhesive. Is possible. Therefore, since it is possible to improve the adhesion between the support and the semiconductor chip,
A highly reliable semiconductor device can be obtained. Moreover, the process can be simplified.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)〜(c)は、第1の実施形態における半
導体装置の製造工程を示す断面図である。
1A to 1C are cross-sectional views showing a manufacturing process of a semiconductor device according to a first embodiment.

【図2】(a)〜(c)は、第1の実施形態における半
導体装置の製造工程を示す断面図である。
2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment.

【図3】(a)〜(c)は、第2の実施形態における半
導体装置の製造工程を示す断面図である。
3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device according to the second embodiment.

【図4】(a)〜(c)は、第2の実施形態における半
導体装置の製造工程を示す断面図である。
4A to 4C are cross-sectional views showing the manufacturing process of the semiconductor device according to the second embodiment.

【図5】(a)〜(c)は、第3の実施形態における半
導体装置の製造工程を示す断面図である。
5A to 5C are cross-sectional views showing a manufacturing process of a semiconductor device according to a third embodiment.

【図6】(a)〜(c)は、第3の実施形態における半
導体装置の製造工程を示す断面図である。
6A to 6C are cross-sectional views showing the manufacturing process of the semiconductor device according to the third embodiment.

【図7】(a)〜(c)は、従来のBGAの半導体装置
における、代表的な内部構造を示す断面図である。
7A to 7C are cross-sectional views showing a typical internal structure of a conventional BGA semiconductor device.

【図8】(a),(b)は、従来のBGAの半導体装置
における、代表的な内部構造を示す断面図である。
8A and 8B are cross-sectional views showing a typical internal structure of a conventional BGA semiconductor device.

【図9】(a)〜(d)は、図7(a)に示す構造を有
する半導体装置を製造する工程を示した断面図である。
9A to 9D are cross-sectional views showing a process of manufacturing a semiconductor device having the structure shown in FIG. 7A.

【図10】(a)〜(c)は、図7(a)に示す構造を
有する半導体装置を製造する工程を示した断面図であ
る。
10A to 10C are cross-sectional views showing a process of manufacturing a semiconductor device having the structure shown in FIG. 7A.

【図11】(a)〜(d)は、図7(b)に示す構造を
有する半導体装置を製造する工程を示した断面図であ
る。
11A to 11D are cross-sectional views showing a process of manufacturing a semiconductor device having the structure shown in FIG. 7B.

【図12】(a)〜(c)は、図7(b)に示す構造を
有する半導体装置を製造する工程を示した断面図であ
る。
12A to 12C are cross-sectional views showing a process of manufacturing a semiconductor device having the structure shown in FIG. 7B.

【図13】(a),(b)は、図7(b)に示す構造を
有する半導体装置を製造する工程を示した断面図であ
る。
13A and 13B are cross-sectional views showing the steps of manufacturing a semiconductor device having the structure shown in FIG. 7B.

【図14】(a),(b)は、図7(b)に示す構造を
有する半導体装置を製造する工程を示した断面図であ
る。
14A and 14B are cross-sectional views showing a process of manufacturing a semiconductor device having the structure shown in FIG. 7B.

【図15】(a),(b)は、従来の半導体装置の製造
方法における不具合を説明するための断面図である。
15A and 15B are cross-sectional views for explaining a defect in a conventional method for manufacturing a semiconductor device.

【図16】(a),(b)は、従来の半導体装置の製造
方法における不具合を説明するための断面図である。
16 (a) and 16 (b) are cross-sectional views for explaining a defect in the conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体チップ 2 プリント配線板 2a 内部接続用ランド 2b 配線パターン 2c バイアホール 2d 外部端子用ランド 2e 絶縁部材 3 ワイヤ 4 接着剤 5 封止樹脂 6 金属ボール 8 バンプ 9 オーブン 11 第2半導体チップ 13 ワイヤ 14 第2接着剤 20a 上部金型 20b 下部金型 1 semiconductor chip 2 printed wiring board 2a Land for internal connection 2b wiring pattern 2c via hole 2d Land for external terminal 2e Insulation member 3 wires 4 adhesive 5 Sealing resin 6 metal balls 8 bumps 9 oven 11 Second semiconductor chip 13 wires 14 Second adhesive 20a upper mold 20b Lower mold

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 25/18 ─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. 7 Identification Code FI Theme Coat (Reference) H01L 25/18

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップと、上記半導体チップを搭
載する支持体と、上記半導体チップと上記支持体とを接
着する接着剤とが、封止樹脂によって封止されている半
導体装置の製造方法であって、 上記支持体と上記半導体チップと上記接着剤とを封止金
型内で上記封止樹脂で封止する工程で、上記封止樹脂に
は圧力を印加して、上記接着剤の硬化の少なくとも一部
と上記封止樹脂の硬化の少なくとも一部とを行なう工程
(a)を備える半導体装置の製造方法。
1. A method of manufacturing a semiconductor device, wherein a semiconductor chip, a support on which the semiconductor chip is mounted, and an adhesive for adhering the semiconductor chip and the support are sealed with a sealing resin. Then, in the step of sealing the support, the semiconductor chip, and the adhesive with the sealing resin in a sealing mold, pressure is applied to the sealing resin to cure the adhesive. A method for manufacturing a semiconductor device, comprising the step (a) of performing at least a part of the above and at least a part of curing of the sealing resin.
【請求項2】 請求項1に記載の半導体装置の製造方法
において、 上記半導体チップはフェイスダウン方式で上記支持体に
搭載され、上記半導体チップと上記支持体との電気的接
続をバンプによって行なうことを特徴とする半導体装置
の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip is mounted on the support in a face-down manner, and the semiconductor chip and the support are electrically connected by bumps. A method for manufacturing a semiconductor device, comprising:
【請求項3】 請求項1または2に記載の半導体装置の
製造方法において、 上記半導体チップの上に、第2接着剤を挟んで第2半導
体チップを搭載し、 上記工程(a)では、上記第2接着剤の硬化の少なくと
も一部をも行なうことを特徴とする半導体装置の製造方
法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein a second semiconductor chip is mounted on the semiconductor chip with a second adhesive interposed therebetween, and in the step (a), the second semiconductor chip is mounted. A method of manufacturing a semiconductor device, characterized in that at least a part of curing of the second adhesive is also performed.
【請求項4】 請求項3に記載の半導体装置の製造方法
において、 上記第2半導体チップはフェイスダウン方式で上記半導
体チップに搭載され、 上記第2半導体チップと上記半導体チップとの電気的接
続をバンプによって行なうことを特徴とする半導体装置
の製造方法。
4. The method of manufacturing a semiconductor device according to claim 3, wherein the second semiconductor chip is mounted on the semiconductor chip by a face-down method, and the second semiconductor chip and the semiconductor chip are electrically connected. A method for manufacturing a semiconductor device, which is performed by bumps.
【請求項5】 請求項1〜4のいずれかに記載の半導体
装置の製造方法において、 上記半導体チップは複数であり、 上記工程(a)では、上記半導体チップと上記支持体と
を接着する上記接着剤の硬化の少なくとも一部を行うこ
とを特徴とする半導体装置の製造方法。
5. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip is plural, and in the step (a), the semiconductor chip and the support are bonded to each other. A method for manufacturing a semiconductor device, characterized in that at least a part of the curing of the adhesive is performed.
【請求項6】 請求項1〜5のいずれかに記載の半導体
装置の製造方法において、 上記工程(a)では、上記接着剤および上記封止樹脂の
硬化が完了することを特徴とする半導体装置の製造方
法。
6. The method for manufacturing a semiconductor device according to claim 1, wherein in the step (a), the curing of the adhesive and the sealing resin is completed. Manufacturing method.
【請求項7】 半導体チップと、上記半導体チップの上
に搭載される第2半導体チップと、上記半導体チップと
上記第2半導体チップとを接着する第2接着剤とが、封
止樹脂によって封止されている半導体装置の製造方法で
あって、 上記半導体チップと上記第2半導体チップと上記第2接
着剤とを封止金型内で上記封止樹脂で封止する工程で、
上記封止樹脂には圧力を印加して、上記第2接着剤の硬
化の少なくとも一部と上記封止樹脂の硬化の少なくとも
一部とを行なう工程(a)を備える半導体装置の製造方
法。
7. A semiconductor chip, a second semiconductor chip mounted on the semiconductor chip, and a second adhesive for bonding the semiconductor chip and the second semiconductor chip together are sealed with a sealing resin. A method of manufacturing a semiconductor device, wherein the semiconductor chip, the second semiconductor chip, and the second adhesive are sealed with the sealing resin in a sealing mold,
A method of manufacturing a semiconductor device comprising a step (a) of applying a pressure to the sealing resin to perform at least a part of the curing of the second adhesive and at least a part of the curing of the sealing resin.
【請求項8】 請求項7に記載の半導体装置の製造方法
において、 上記第2半導体チップはフェイスダウン方式で上記半導
体チップに搭載され、上記第2半導体チップと上記半導
体チップとの電気的接続をバンプによって行なうことを
特徴とする半導体装置の製造方法。
8. The method of manufacturing a semiconductor device according to claim 7, wherein the second semiconductor chip is mounted on the semiconductor chip by a face-down method, and the second semiconductor chip and the semiconductor chip are electrically connected to each other. A method for manufacturing a semiconductor device, which is performed by bumps.
【請求項9】 請求項7または8に記載の半導体装置の
製造方法において、 上記工程(a)では、上記第2接着剤および上記封止樹
脂の硬化が完了することを特徴とする半導体装置の製造
方法。
9. The method of manufacturing a semiconductor device according to claim 7, wherein in the step (a), curing of the second adhesive and the sealing resin is completed. Production method.
JP2002063413A 2002-03-08 2002-03-08 Manufacturing method of semiconductor device Pending JP2003264205A (en)

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