JP2003208358A - Information processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize memory hot swap for exchanging a main memory in which a fault occurs with a normal memory without turning a power of an information processing apparatus off. <P>SOLUTION: The information processing apparatus is provided with main memories 104 to 106 accessed by a processor, a redundant memory 107 made into redundant separately from the main memories, a fault detection part 102 for detecting occurrence of the fault in the main memories, memory changeover switch parts 108 to 110 for switching the main memory in which the fault occurs detected by the fault detection part to the redundant memory, a switch control part 103 for controlling switching of memories, and hot swap switch parts 111 to 114 for electrically cutting off the main memories and the redundant memory from the information processing apparatus. Then, data of the main memory in which the fault occurs is copied in the redundant memory, the main memory in which the fault occurs is electrically cut off by the hot swap switch parts as alternatively using the redundant memory by switching the access to the redundant memory by the memory change over switch parts, and the memories are switched without turning the power of the information processing apparatus off. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, when a failure occurs in the main memory, the main memory can be replaced without turning off the power of the information processing apparatus while continuing the information processing of the processor. The present invention relates to a technology effectively applied to a memory hot swap technology and the like for performing.

[0002]

2. Description of the Related Art In the field of information processing in recent years, high reliability of an information processing apparatus is required with the 24-hour 365-day operation of the information processing (non-stop operation). As means for improving the reliability of the information processing apparatus, duplication of each part constituting the information processing apparatus and hot swapping in which only the failure part can be replaced without turning off the power of the information processing apparatus are often adopted.

[0003]

However, in the main memory, which is one of the most important parts of the information processing device among the parts constituting the information processing device, when the failure occurrence is detected, the information processing is performed. In many cases, a method of replacing the main memory in which a failure has occurred is adopted after the power of the device is turned off, the processing work is temporarily stopped. For this reason, it is difficult to realize the continuous information processing work 24 hours a day, 365 days a year.

In order to solve such a technical problem,
The memory of the information processing device has a dual structure of a main memory system and a redundant system, and the data stored in the memory is always stored dually in the main memory system and the redundant system, and a copy of the data stored in the main system is made. There is an information processing device that has a redundant system side and uses a means to switch from the main system memory to the redundant system memory when a failure occurs, but the redundant system memory cannot be effectively used for information processing during normal operation. By mounting an expensive memory, the price of the information processing apparatus itself is increased.

An object of the present invention is to replace the power supply of the information processing device itself without turning off the power in the memory replacement at the time of failure of the main memory which is one of the most important parts constituting the information processing device. We provide a hot swap technology for memory, which allows you to replace main memory without stopping others, and also to keep the price of information processing equipment low by minimizing redundant mounting of expensive memory. Especially.

[0006]

An information processing apparatus according to the present invention comprises a redundant memory which partially replaces the main memory in addition to the main memory, and when a failure occurs in the main memory, the failure main memory Only the data is selectively copied to the redundant memory, and while the information processing work is continued with the data copied to the redundant memory, the failure main memory is replaced.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a conceptual diagram showing an example of the configuration of a main memory portion in an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is provided in the information processing apparatus according to the present embodiment. FIG. 3 is a conceptual diagram showing an example of the configuration of the memory control LSI, and FIG. 3 is a flowchart showing an example of the operation of the information processing apparatus according to the present embodiment.

The information processing apparatus according to the present embodiment has a main memory 104 for storing data handled by a processor (not shown),
Main memory 105, main memory 106, and the main memory 10
A redundant memory 107 that is made redundant separately from 4 to 106;
The main memories 104 to 106 and the redundant memory 107
And a system bus to which a processor (not shown) is connected,
A memory control LSI 101 is provided between the peripheral device and a PCI bus to which peripheral devices (not shown) are connected.

The memory control LSI 101 includes a failure detection unit 102 for detecting a failure occurrence in each of the main memories 104 to 106, a failure occurrence main memory detected by the failure detection unit 102, and the redundant memory 107. A memory changeover switch unit 108, a memory changeover switch unit 109, a memory changeover switch unit 110,
A switch control unit 103 for controlling the memory changeover switch units 108 to 110 is provided.

Further, between the memory control LSI 101 and the main memories 104 to 106 and the redundant memory 107, each of the main memories 104 to 106 and the redundant memory 107 is provided from the information processing device under the control of the switch control unit 103. A hot swap switch unit 111, a hot swap switch unit 112, a hot swap switch unit 113, and a hot swap switch unit 114, which are selectively electrically disconnected, are provided.

In the case of the present embodiment, as an example, each of the plurality of main memories 104 to 106 is composed of a semiconductor memory board or the like that can be individually mounted (removed) in an information processing device via a slot or the like not shown. ing. The storage capacity of the redundant memory 107 is composed of a semiconductor memory board or the like having a storage capacity capable of substituting one of the main memories 104 to 106.

Further, as illustrated in FIG. 2, inside the memory control LSI 101, a main memory 1 as described later is provided.
04 to 106 and a memory copy buffer 201 used for data copy between the redundant memories 107.

Hereinafter, an example of the operation of the memory hot swap in the information processing apparatus of this embodiment will be described with reference to the flowchart of FIG.

In the information processing apparatus of the present embodiment having the above-mentioned configuration, for example, when a memory error fault that can be corrected by ECC or parity occurs in the main memory 104, the fault detection unit 102 detects the fault. And record. Then, if the frequency of detecting the same error-correctable fault in the main memory 104 exceeds a predetermined value, the main memory 104 is specified as the fault-occurring main memory to be replaced due to the fault (step 301).

Then, the failure detection unit 102 is connected to the main memory 10
4 stores the data stored in the memory copy buffer 20.
It is read to 1 (step 302). After that, the switch control unit 103 switches the memory changeover switch unit 108 to the side of the redundant memory 107 (step 303) and sets the data stored in the memory copy buffer 201 to the redundant memory 1 side.
It is written in 07 (step 304). The above process is repeated until all the data stored in the main memory 104 where the failure has occurred is stored in the redundant memory 107 (step 305). As a result, the access from the processor side to the main memory 104 to be replaced is not interrupted, and the main memory 104 to the redundant memory 10 are interrupted between the accesses.
Data copy to 7 can be performed.

When the data storage in the redundant memory 107 is completed, the memory changeover switch unit 108 is kept switched to the redundant memory 107 side, and the use of the data in the redundant memory 107 instead of the main memory 104 is started ( In step 306), the switch control unit 103 turns off only the hot swap switch unit 111, and electrically disconnects the main memory 104 from the information processing device (step 307). This process causes the main memory 104 to fail.
This can be removed without turning off the information processing device (step 308).

During this time, the switch control section 103 keeps the memory changeover switch section 108 switched to the redundant memory 107 side, and the redundant memory 107 is kept in the main memory 104.
Instead of, processing continues.

Furthermore, when the main memory 104 removed as described above is replaced with a normal memory, the hot swap switch unit 111 is turned on by the switch control unit 103, and the main memory 104 is transferred to the information processing device. (Step 309). Furthermore, the failure detection unit 10
2 reads the data stored in the redundant memory 107 to the memory copy buffer 201 (step 310). Thereafter, the switch control unit 103 switches the memory changeover switch unit 108 to the normal main memory 104 side (step 311) and writes the data stored in the memory copy buffer 201 to the normal main memory 104 (step 31).
2). The above process is repeated until all the data stored in the redundant memory 107 is stored in the normal main memory 104 (step 313).

Thereafter, the switch control unit 103 keeps the memory changeover switch unit 108 switched to the main memory 104 side and continues (restarts) the process using the replaced main memory 104 (step 314).

In the above description, the main memory 1 of the failure is
04 After the replacement, the use of the replaced main memory is resumed, but the redundant memory 107 used as a substitute at the time of replacement is regarded as a normal main memory and continued to be used as it is, and the other main memory or the redundant memory concerned When a failure occurs, the previously replaced main memory may be regarded as redundant memory and memory hot swap may be performed. In this case, there is an advantage that it is possible to omit the processing (steps 309 to 314, etc.) of returning the data copied to the redundant memory to the main memory of the substitution source.

As described above, in the case of the present embodiment, the redundant memory 107 having a capacity for substituting a part of the plurality of main memories 104 to 106 is provided, and a failure occurs in any of the main memories 104 to 106. When the replacement is required, the data of the main memory to be replaced is selectively copied to the redundant memory 107, and the redundant memory 107 is used to accept the access from the processor to continue the operation. Since the main memory to be replaced is electrically separated from the information processing apparatus and removed and replaced without turning off the information processing apparatus, hot swapping of the main memory can be realized without stopping the information processing apparatus. .

Further, since the capacity of the redundant memory 107 is about the capacity of a part of the main memory to be replaced (unit), the information processing apparatus can be compared with the case where the entire main memories 104 to 106 are made redundant. Manufacturing cost reduction, main memory 104
It is possible to improve availability of hardware resources such as ~ 106 and redundant memory 107 and to prevent performance deterioration due to constant double writing of data in the redundant memory.

Further, since the data copy from the main memory to be exchanged to the redundant memory 107 is executed via the memory copy buffer 201 between the accesses from the processor side, the main memory hot swap operation is in progress. It is also possible to prevent a decrease in access performance from the processor to the main memory in.

The present invention is not limited to the above embodiment, and for example, instead of the redundant memory 107, a hard disk mounted in the information processing device can be used.

Further, in the above-described present embodiment, the fault detection unit 102 for detecting the fault occurrence in the main memory, the memory changeover switch unit for switching between the fault main memory detected by the fault detection unit and the redundant memory. 108,
Although the memory control LSI 101 includes the switch control unit 103 for controlling the changeover switch unit 109 and 110, the memory changeover switch for switching between the fault main memory detected by the fault detection unit and the redundant memory. The units 108, 109, 110 and the switch control unit 103 for controlling the changeover switch unit can be provided outside the memory control LSI 101. This allows general-purpose memory control L such as a bus bridge.
It is also possible to realize a hot swap method of memory by using SI.

The invention described in the claims of the present application can be expressed in a different way as follows.

(1) A main memory that stores data handled by a processor, a redundant memory that is made redundant in addition to the main memory, a failure detection unit that detects a failure occurrence in the main memory, and the failure detection unit A memory changeover switch unit for switching between the main memory and the redundant memory in which a failure is detected, a switch control unit for controlling the changeover switch unit, and a hot swap switch for electrically disconnecting the main memory and the redundant memory from the information processing device. And a memory hot-swap method.

(2) A memory hot-swap system characterized in that data stored in the main memory is copied to the redundant memory, and data stored in the redundant memory is copied to the main memory.

(3) A memory hot-swap system characterized in that the main memory can be replaced without turning off the power of the information processing apparatus after copying the data stored in the main memory to the redundant memory.

(4) The data stored in the main memory is copied to the redundant memory only when a failure is detected, and after the failure main memory is replaced, the data copied to the redundant memory is returned to the main memory. Memory hot swap method.

(5) A memory hot-swap system characterized in that the information processing of the processor can be continued by the redundant memory even when the main memory in which the failure has occurred is replaced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

[0034]

The main memory in which a failure has occurred can be replaced without turning off the power of the information processing apparatus, continuous operation of the information processing apparatus can be realized 24 hours a day, 365 days a year, and reliability can be improved.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing an example of a configuration of a main memory part in an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing an example of a configuration of a memory control LSI provided in the information processing apparatus according to the embodiment of the present invention.

FIG. 3 is a flowchart showing an example of an operation of the information processing apparatus according to the exemplary embodiment of the present invention.

[Explanation of symbols]

101 ... Memory control LSI 102 ... Fault detection unit 103 ... Switch control units 104, 105, 106 ... Main memory 107 ... Redundant memories 108, 109, 110 ... Memory changeover switch units 111, 112, 113, 114 ... Hot swap switch unit 201 … Memory copy buffer

Continued front page    (72) Inventor Yoshiaki Hisada             810 Shimo-Imaizumi Stock Exchange, Ebina City, Kanagawa Prefecture             Hitachi Platform Platform             Home Office (72) Inventor Hiroyuki Jinno             810 Shimo-Imaizumi Stock Exchange, Ebina City, Kanagawa Prefecture             Hitachi Platform Platform             Home Office F term (reference) 5B018 GA06 KA03 KA13 MA01 MA24

Claims (3)

[Claims] 1. A main memory that stores data handled by a processor, a redundant memory that is redundant to the main memory, a failure detection unit that detects a failure occurrence in the main memory, and a failure detection unit. A memory changeover switch unit that switches between the main memory and the redundant memory in which a failure has been detected, a switch control unit that controls the memory changeover switch unit, and a hot that electrically disconnects the main memory and the redundant memory from the information processing device. An information processing device comprising a swap switch unit. 2. The information processing apparatus according to claim 1,
Data stored in the main memory in which a failure has been detected is selectively copied to the redundant memory, and operation is continued using the redundant memory in place of the main memory, and a failure has been detected. After replacing the main memory, after returning the data of the redundant memory to the replaced main memory, use of the main memory is resumed. 3. The information processing apparatus according to claim 2,
The information processing apparatus, wherein the copying of the data between the main memory and the redundant memory is performed via a copy buffer between the accesses from the processor to the main memory.