JP2003208352A - Flash memory enabling restriction of writing frequency and ware levelling - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flash memory for restricting writing frequencies and enabling ware levelling. <P>SOLUTION: The flash memory is provided with a plurality of pages having data areas and management areas corresponding to the data areas and further has a plurality of the pages and a plurality of memory blocks of deletion unit. Then the flash memory is further provided with page ID areas in which page IDs specifying the pages are written when data is written in the management areas of the respective pages and a first positional flag area in which information for specifying a page to be written among a plurality of the pages with the same page ID in the latest data writing position is written when the data is updated and written. Thus, writing operation to a page at an update origin becomes unnecessary to be performed in the case of update and write. Writing operations are successively performed to deleted unused pages and when unused pages to be written are deleted, garbage collection is performed. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory which is one of semiconductor non-volatile memories, and more particularly to a flash memory which limits the number of times of writing and enables wear leveling.

[0002]

2. Description of the Related Art Semiconductor non-volatile memory is widely used as a device that can retain stored data even when the power is off, is smaller than a hard disk, and can be read at high speed. In particular, the flash memory has a relatively large erase unit to suppress the disadvantage of the semiconductor nonvolatile memory that the erase time is long.

A semiconductor non-volatile memory has a cell transistor having a structure in which a floating gate is embedded in a gate oxide film between a gate electrode of a MOS transistor and a channel region. In the flash memory, these cell transistors are connected in cascade, and the segments connected in cascade are connected to the bit line through the select transistor.
Type memory. Because of its large capacity, this NAND flash memory is widely used as a memory for digital still cameras and mobile phones.

It is known that a characteristic feature of such a NAND type flash memory is that when the number of write (program) operations for accumulating charges in the floating gate of a cell transistor increases, a write error is likely to occur. It is better to limit the number of times of writing from one erase operation to the next. On the other hand, in the erase operation,
Electric charges are once injected into the floating gates of all the cell transistors in the block of the erase unit, and then an erase pulse is applied all at once to remove the charges in the floating gates. Therefore, as compared with the read operation and the write operation, the erase operation requires a long time, for example, 1 second. Therefore, it is preferable to reduce the frequency of the erase operation as much as possible.

Further, as a feature of the flash memory, if the number of write (program) operations or erase operations increases, the tunnel oxide film under the floating gate may deteriorate, and an over-program phenomenon due to the program operation may occur. Therefore, it is desirable to reduce the number of erasures as much as possible to minimize such a problem. One solution to this is the idea of wear leveling, and it has been proposed to perform the erase operation as evenly as possible in the memory cell array in the chip.

FIG. 1 is a block diagram of one conventional flash memory proposed in Japanese Patent Laid-Open No. 9-97218. In this example, erase block EB, which is the erase unit
It has a plurality of pages in LK, and has an array of cell transistors (not shown) in each page PAGE. Each of the erase blocks EBLK has an erase count counter 10, and every time an erase block is erased, the erase count counter 10 in the block is incremented. As a result, it is possible to grasp the erase counts of all erase blocks, and in the garbage collection process, erase blocks with a small erase count can be preferentially selected as the rearrangement target blocks to disperse the erase operation.

Each page comprises a data area 20 for storing data and a management area. In the management area, a page number 12, a busy flag 14 indicating whether the page is effectively used, a used flag 16 indicating that the usage of the page is finished, and an error collection code 18
Area is provided.

According to this conventional example, in the new write operation, a predetermined number is written in the page number 12 and TRUE is written in the in-use flag 14 for an unused page, and write data is written in the data area. . In addition, in the update write operation, that is, the operation of rewriting the data with respect to the specific page that has been written, the update data is written in the unused page without erasing the page,
The busy flag 14 is set to TRUE, and the used flag 16 is set to TRUE for the page in which the original data is written. As a result, among the plurality of pages having the same page number, it can be determined that the data of the page whose used flag 16 is FALSE is the latest valid data. When deleting page data, set the used flag
It should be set to TRUE.

As the update write operation is repeated and the page delete operation is repeated as described above, unused pages disappear. Therefore, new write operation and update write operation cannot be performed. In such cases, garbage collection is performed. In this garbage collection, the data of all the used pages in a specific erase block is written in the unused page, and the erase operation is performed on the erase block to make it the unused page. The erase block to be adjusted is selected on the basis of the small number of erase counters in each block.

[0010]

In the above-mentioned conventional example, in response to a write command, data is written in the data area 20, and further information necessary for the page number 12, the busy flag 14, the ECC 18, etc. in the management area. Write. Furthermore,
When an update write command is issued, it is necessary to write TRUE to the used flag 16 for the update source page. Further, if there is a delete command after writing, it is necessary to write TRUE in the used flag 16 as well. Moreover, when the erase operation is completed, the write operation to the erase number counter 10 is also performed.

Therefore, in one erase block, between the erase operation and the next erase operation, (1) writing to the erase count counter, (2) writing to the data area, and (3) writing to the management area. , (4) Writing to the used flag and a large number of writing operations are repeated. Such increase in the number of write operations causes an error, especially in a NAND flash memory, which is not preferable.

Further, an erase count counter is provided for each erase block, the counter value is incremented for each erase operation, and when performing garbage collection, the erase count counter is referenced to select the erase block to be adjusted. Is complicated and is not preferable as a wear leveling method.

Therefore, an object of the present invention is to provide a flash memory in which the management of wear leveling is simplified and the number of write operations between erase operations is minimized.

[0014]

In order to achieve the above object, the first aspect of the present invention has a plurality of pages each having a data area and a management area corresponding to the data area. It is a flash memory having a plurality of pages and a plurality of memory blocks in erase units. Then, in the management area of each page, when data is written, a page ID area in which a page ID that identifies the page is written,
There is provided a first position flag area in which, when the data is written, information for specifying the position of the write target page for writing the latest data among a plurality of pages having the same page ID is written.

According to the first aspect described above, at the time of update writing, it is not necessary to write any information to the management area of the update source page, and the page ID and the first ID are stored in the management area of the update destination page. It is sufficient to write the position flag of 1. Therefore, the write operation to the management area of the update source page can be omitted, and the number of write operations during the erase operation can be reduced.

To achieve the above object, the second aspect of the present invention has a plurality of pages having a data area and a management area corresponding to the data area, and further has the plurality of pages. It is a flash memory having a plurality of erase-unit memory blocks. Then, in each page area, a second position flag area is provided in which, when data is written, information for specifying the write target page as a final write position is written. According to the information in the second position flag area, the data write operation is performed on the plurality of pages in serial order.

Further, when the data write operation to the memory blocks other than the transfer memory block is completed, garbage collection is performed, and at that time, the valid data in the rearrangement target memory block having the valid page written earliest is valid. Garbage collection is performed in which data is written to the transfer memory block and the rearrangement target memory block is erased.

In the second aspect described above, it is possible to serially write data to the memory blocks in the erase unit and further perform the erase operation in order. Therefore, it is possible to evenly distribute the erase operation to a plurality of memory blocks without providing an erase counter in each memory block.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. However, the scope of protection of the present invention is not limited to the following embodiments,
The invention extends to the inventions described in the claims and their equivalents.

FIG. 2 is an overall configuration diagram of the flash memory according to the present embodiment. A command CMD from the outside is input to the flash memory, and a controller 30 for controlling internal writing (programming), reading, and erasing, a memory cell array 32 for storing data, and data writing to the memory cell array 32 and It has a page buffer PB for reading. The write data DATA supplied from the outside is temporarily stored in the page buffer PB, and the data is written to the page area corresponding to the address ADD supplied from the outside.

The memory cell array 32 is divided into a plurality of erase unit memory blocks (erase blocks) EBLK, and each memory block EBLK is further divided into a plurality of page areas PAGE. A data area for holding data and a management area for managing the page are provided for each page area.

FIG. 3 is a block diagram of a memory cell array of a NAND type flash memory. In the memory cell array, a plurality of bit lines BL0, BL1, a plurality of segments SG connected to each bit line, a plurality of memory cells MC provided in each segment, and a plurality of word lines connected thereto WL and is provided.

A plurality of segments (16 in the figure) are provided in the segment SG.
Memory cells MC are connected in a column, one of which is the first
Is connected to the bit line BL via the segment gates SGG10, SGG11, SGG12, and the other is the second segment gate SG.
It is connected to the in-cell source voltage ARRVSS via G20, SGG21, SGG22.

Then, in the read operation, for example, the segment selection signals SG10, SG20 are controlled to the H level, the first and second segment gates SGG10, SGG20 are rendered conductive, and 16
A segment SG composed of memory cells is connected between the bit line BL and the source voltage ARRVSS in the cell. 1 of 16 word lines connected to 16 memory cells MC
A high voltage is applied to the five unselected word lines, and an intermediate voltage between the threshold voltages corresponding to the data "0" and "1" is applied to one selected word line. In one example, unselected word lines have a voltage of 4V or lower, and selected word lines have a voltage of 0V.
V.

As a result, of the 16 memory cells in the segment, all 15 non-selected memory cells become conductive, and only one selected memory cell becomes conductive or non-conductive depending on the stored data. Become. Along with that, bit line BL
A state is generated in which current flows or does not flow. The page buffer PB connected to each bit line BL0, BL1 detects the presence or absence of the bit line current and latches the read data.

In addition, during a write (program) operation, the segment SG is similarly divided into the bit line BL and the source line in the cell.
Connected to ARRVSS, the bit line BL and the selected word line are controlled to a high potential. As a result, charges (electrons) are injected into the floating gate from the drain of the selected memory cell by the tunnel phenomenon. Along with this, the threshold voltage of the memory cell becomes a positive voltage.

On the other hand, in the erase operation, after all the memory cells are set to the programmed state, all the segments are connected to the bit line BL and the intra-cell source line ARRVSS, and the bit line BL.
Is controlled to a floating state, all word lines are controlled to a negative voltage, and the in-cell source voltage ARRVSS is controlled to a high voltage. As a result, in all the memory cells, the charge in the floating gate is extracted to the source, and the threshold voltage of all the memory cells becomes a negative voltage.

FIG. 4 is a detailed configuration diagram of the flash memory according to the present embodiment. The memory block EBLK, which is the erase unit, is divided into multiple pages PAGE. Figure 4
In the above example, the memory block EBLK is divided into four pages PAGE for simplicity.

Each page PAGE is provided with a data area 20 for holding data and a management area 11 for managing the page area. The data area 20 is, for example, 256
Has a capacity of bytes. The management area 11 does not necessarily have to be provided physically adjacent to the data area 20,
The data area 20 and the management area 11 of all page areas may be provided physically separated.

A physical address is assigned to each page PAGE so that all pages can be physically distinguished.

The management area 11 of each page area specifies the position where the latest data is written among the plurality of pages having the same page ID and the page identifier PID in which the page ID for specifying the page is written. The latest page write position flag (first position flag) F1 to be used and the final write position flag (second position flag) F2 that specifies the last data write position of all pages are included. This page identifier PID corresponds to the logical address of page PAGE. Furthermore, the management area 11 is the data area 2
EC to write error correction code of data written in 0
It has a C area and a bad block information area DBL that specifies the memory block to which the page belongs as a bad block when an error occurs in the stored data.

A write operation and a garbage collection operation in such a flash memory configuration will be described below.

[Write Operation] FIG. 5 is a flow chart of the write operation to the page. Further, FIG. 6 is a diagram for explaining a write operation to a page. When a data write command is issued, the controller 30 writes (programs) data in the data area 10 of the page to be written (S10). As will be described later, since the page to be written is an erased and unused page, it is possible to write by performing a program operation on the memory cell in the data area 10. As shown in FIG. 6, this is the first write operation for the page.

The program operation includes a program verify, which confirms whether or not the writing is normally completed (S12). When the writing operation is completed normally, next, the page identifier PID in the management area 11, the latest page writing position flag F1, the last writing position flag F2,
And writing to the ECC area is performed (S14). This is,
This is the second write operation for the page.

The page identifier PID is a logical address assigned to a page, and as described later, the same page identifier may be given to a plurality of pages as a result of update writing. The latest page write position flag F1 is, for example, a count value that is sequentially decremented (or sequentially incremented) for a plurality of pages having the same page identifier, and by referring to the position flag F1. It is possible to identify which of a plurality of pages having the same page identifier PID is a valid page in which the latest data is written.

The final write position flag F2 is a count value that is sequentially decremented (or sequentially incremented) every time writing is performed on all pages. Therefore, the position of the last written page can be detected by referring to the position flag F2, and the data write operation can be performed on a plurality of pages in serial order by the position flag F2. You can

The ECC is an error correction code generated from the data written in the data area 10 according to a predetermined error correction algorithm. With this error correction code, it is possible to detect whether or not there is an error in the stored data, and the error can be corrected. And
Normally, once an error occurs, the bad block information DBL of that page is set to TRUE, and then the use of the memory block to which the bad page belongs is prohibited.

If normal writing to the data area 10 is not performed, TRUE is written to the defective block information DBL (S15). This is also the second write operation. Further, even when the writing to the management area 11 is not normally performed (S16), TRUE is written to the bad block information DBL (S18). This corresponds to the third write operation.
Furthermore, even after the writing to the data area and the management area is normally performed, if an error is detected in the subsequent read operation, the defective block information DBL is detected as described above.
TRUE is written to. This also corresponds to the third write operation.

When there is an update write command to update the data written in the data area 10 (S20), the flash memory does not write the update data again to the original page, but to another erased page (not yet written). Write the updated data to the (used page). In the flash memory, it is necessary to erase the original page once in order to rewrite the updated data. However, since the erase operation takes a long time, it is not efficient to erase the original page for each update write. Therefore, the update data is written to the new erased page while keeping the storage state of the original page.

In this case, the update data is written to another erased page, the same page identifier PID is written to the management area 11, and the page latest write position flag F1 is decremented. The count value is written (S22). As a result, the same page identifier P
Although there are a plurality of pages having the ID, it is possible to identify which page stores valid data by referring to the page latest write flag F1. By doing so, the update writing can be performed without performing the writing operation to the management area of the original page.

Furthermore, if there is a delete command for deleting the data of the page (S24), the page latest write position flag F1 in the management area 11 will have a count value indicating deletion, for example, a count value of all 0s. It is written (S26). This corresponds to the third writing. The data area of the corresponding page is not erased in response to the delete command. Also, the delete command is one of the write commands,
In the case of deletion, unlike update writing, a page having the same latest identifier and decremented page latest writing position flag F1 is not added. Therefore, in the case of a delete instruction, it is necessary to write a count value of all 0s to the page latest write position flag F1 for a page with the same page identifier to indicate that the data of that page has become invalid. . Alternatively, only for the page having valid data, the page latest writing position flag F1
A count value of all 0 may be written in.

7 and 8 are diagrams for further explaining the write operation. Here, 4 for each memory block EBLK
One page is included, and there are four memory blocks EBLK0-3 in total. In the initial state, all pages are in the erased state. Further, in FIG. 7, the solid line is
The transition of the write target page is shown, and the broken line shows the transition of the page of the same page identifier PID for the update writing.

FIG. 7 shows a newly written state S30. By the first new write operation, data is written in the highest page of the memory block EBLK0, the page identifier PID = 0, and the page latest write position flag F1 is set to "0".
xFFFE "and" 0xFFFE "are written in the final write position flag F2. In the erased state, the maximum count value “0xFFFF” is written as a default value in these identifiers and flags. Therefore, when a new writing is performed on the page, the count value obtained by decrementing the default value is written in the position flags F1 and F2.

When the next new write operation occurs, the data is written to the page at the next position in the same memory block EBLK, and the page identifier PID = 1 and the page latest write position flag F1 is "0xFFFE", which is the final value. Write position flag F2 with "0xFFF
"D" is written respectively. Since the page identifier PID = 1 is the first write, the page latest write position flag F1 is written with "0xFFFE" decremented from the default maximum count value. On the other hand, since the target page to be written is the second, the decremented "0xFFFD" is written in the final write position flag F2.

Similarly, by the subsequent two new write operations, PID = 2, F1 = 0xFFFE, F2 = 0xFFFC and PID = 3, F1 in the remaining two pages in the memory block EBLK.
= 0xFFFE and F2 = 0xFFFB are written.

In this state, since the final write position flag F2 of the fourth page of the memory block EBLK has the smallest count value, the next write can be performed to the page next to that page. In this way, by sequentially writing the decremented count value as the final write position flag F2, writing to all pages can be performed in a serial order.

Next, FIG. 7 shows a state in which the data has been updated and written.
S31 is shown. From the new writing state S30, the page identifier PI
State S31 after two update writes have occurred for D = 0
Shown in. When the first update writing occurs for the page identifier PID = 0, the updated data is written to the first page of the memory block EBLK1, and PID = 0, F1 = 0xFFFD, F2 = 0xFFFA is written. That is, since there are a plurality of pages having the same page identifier PID = 0, the page latest writing position flag F1 is displayed to indicate that the latest data is written.
At this time, F1 = 0xFFFD decremented from the position flag F1 = 0xFFFE of the update source page is written. Further, in order to indicate the final write position regardless of the page identifier PID, the final write position flag F2 is decremented from the position flag F2 = 0xFFFB of the fourth new write target page F2 = 0xFFFA.
Is written.

Further, when the second update write occurs for the page identifier PID = 0, the updated data is written to the second page of the memory block EBLK, and PID = 0 is written in the management area. , F1 = 0xFFFC, F2 = 0xFFF
9 is written. As with the first time, both position flags F
Both 1 and F2 are decremented.

When update writing occurs in this way, a plurality of pages having the same page identifier PID occur. However, it is possible to determine that the page having the smallest count value of the page latest writing position flag F1 is the valid page holding the latest data, and the page identifier PI
In the read operation for D = 0, it is possible to determine the valid page holding the latest data and read the valid data. Then, as shown in FIG. 7, the two shaded pages become an invalid page state in which invalid data is written.

FIG. 8 shows the state S32 after the deleting operation. From the state S31 after update writing in FIG. 7, the page identifier PID
When an instruction to delete = 0 is issued, the page is identified and PID = 0
Page latest writing position flag F1 of all pages having
, The minimum count value “0x0000” indicating the deleted state is written. As a result, the three pages are in the invalid data holding state (shaded pages), and the three pages are in the valid data holding state. Also, 10 pages are still in the erased state (PAGE in the figure).

As described above, by using the page latest writing position flag F1, it is not necessary to perform any writing operation on the update source page at the time of update writing. Further, the position flag F1 also makes it possible to identify the deleted page.

When a defect occurs, TRUE is written in the defective block information DBL, but thereafter, in the memory block to which the page belongs, the data of the page having valid data is copied to the page in another memory block. To be done. This data copy is the same as the above update write operation. Then, after the valid data is copied, the use of the memory block whose bad block information DBL is TRUE is prohibited.

[Garbage Collection] In this embodiment, each time a new write operation or an update write operation is performed,
Data is newly written to an unused page in the erased state. This data writing is performed in a serial order with respect to unused pages. Then, an invalid page that holds invalid data is generated every update write operation or every delete operation. Eventually, when the number of unused pages in the erased state becomes limited, it is necessary to sort out the invalid pages that hold invalid data and newly secure an unused page in the erased state. This process is garbage collection.

Garbage collection is performed when data writing to all memory blocks other than a predetermined transfer memory block is completed.
In the present embodiment, since writing is performed on unused pages in a serial order, the frequency of garbage collection can be suppressed to a low level.

In the garbage collection, the memory block of the page in which valid data is stored and written earliest becomes the rearrangement target block. The page in which the writing is performed earliest can be found by referring to the final writing position flag F2 in which the writing order is stored. In addition, the valid page that stores valid data can be detected by the first position flag F1. Then, the valid data in the rearrangement target block is copied to the transfer memory block. This copy operation is the same as the update write operation. When the saving of all valid data in the rearrangement target block is completed, the rearrangement target block is erased. When a plurality of blocks to be sorted are erased, the last erased memory block is designated as the subsequent transfer memory block.

FIG. 9 is a flowchart showing the operation of garbage collection. 10 to 13 are diagrams for explaining the garbage collection. Also in this figure, the solid line shows the transition of the write target page,
The broken line shows the transition of data for update writing.

The state before the garbage collection in FIG.
In S60, as a result of appropriately repeating new writing, update writing, and deletion, data writing to all memory blocks except the transfer memory block EBLK3 is completed. The operation of new writing, update writing, and deletion is as described above, and the operation can be understood by referring to the solid line and the broken line in the figure, and the page identifier PID of each page and the position flags F1 and F2. it can. If the erased memory block is the transfer block T-BLK only, garbage collection becomes necessary.

As shown in FIG. 9, a memory block for transfer is designated in advance (S40). In the first state, the memory block EBLK3 is the transfer memory block T
-Designated as BLK. Then, the block to be sorted is specified as the transfer source block (S42). The valid page that was written earliest is the page with page identifier PID = 1, so the memory block to which the page belongs
EBLK0 is the block to be sorted.

Therefore, as in the state S61 of FIG. 10, the valid data of the valid page PID = 1, 2 is copied to the transfer destination block EBLK3. This copy operation is the same as the update write operation, for example, the data of valid page PID = 1 is written to the first page of the transfer destination block EBLK3 (S46),
After that, PID = 1 in the page identifier PID of the management area on the same page
However, "0xFFFD" is written in the page latest writing position flag F1 and "0xFFF2" is written in the final writing position flag F2 (S48). In this state, there are a plurality of pages with the page identifier PID = 1, but it is possible to determine which is the valid page by the position flag F1. In the same way, the data of the page with page identifier PID = 2 is transferred to the transfer block EBL.
Copied to the next page of K3.

Source block EBLK which is an adjustment block
If there are no valid pages in 0, the transfer source block EBL
K0 is erased (S50, S52). This erase operation is performed simultaneously for all pages in the transfer source block. Therefore, even if the erasing time is long, a plurality of pages become erasing target pages, so that erasing efficiency can be improved. Figure 1
The state S62 of 1 is a state in which the erase operation of the rearrangement target block EBLK0 is completed.

Further, the next memory block EBLK1 is designated as the rearrangement target block (transfer source block) (S42).
In this block, page identifiers PID = 3 and 4 exist as valid pages. Therefore, data is copied to the transfer memory block EBLK3 for these pages as well. Data is copied from the valid page that was written first (earliest). Therefore, referring to the final write position flag F2, the page with the page identifier PID = 4 is copied first. The copy operation is as described above. After that, the data of the valid page with the page identifier PID = 3 is copied. As a result, as shown in the state S63 of FIG. 11, all the rearrangement target blocks EBLK1 are invalid pages. Therefore, the rearrangement target block EBLK1 is erased as shown in the state S64 of FIG.

At the time of this state S64, the memory block subject to garbage collection becomes EBLK2. Therefore, this memory block EBLK2 is the block to be adjusted,
That is, it becomes the transfer source block (S56). Then, since there is no erased block in the transfer destination block EBLK3 (S44), the oldest erased memory block EBLK0 is temporarily designated as the transfer destination block (S58).

Then, as shown in the state S65 of FIG. 12, the data of the page of the page identifier PID = 5,6 in the transfer source block EBLK2 is copied to the erased pages of the transfer destination block EBLK0, respectively (S46). , S48). In this state, all pages of the transfer source block EBLK2 are invalid pages, and the memory block EBLK2 is erased as in state S66 of FIG.

Finally, of the erased memory blocks,
Latest erased block (last erased memory block)
Is set as the transfer memory block (S59), and the garbage collection is completed. As a result, memory block EBLK
2 is designated as the transfer block T-BLK.

As described above, the write operation is performed in a serial order from a plurality of erased pages in the memory area regardless of the memory block of the erase unit.
Then, when data is written in all the write target blocks except the transfer block, garbage collection is executed. In garbage collection, the memory block of the oldest written valid page becomes the adjustment target block, and the valid page data in that block is copied to the transfer block. As a result of this copy operation, the original valid page becomes an invalid page. And
The block is erased when all the valid page data in the adjustment target block is copied. When there are no unused pages in the transfer block, the memory block of the copy destination moves to the oldest erase block (first erased block). In this way, the transfer destination blocks are sequentially secured. When the copying of all valid pages is completed and the erasing is completed, the most recently erased memory block is designated as the transfer block and a new write operation is started.

Therefore, even if each memory block does not have an erase count counter, the erase counts can be averaged and wear leveling can be performed. The above garbage collection does not necessarily have to be performed at the time when writing to the erased block other than the transfer block is completed, but may be performed when the erased page reaches a certain level. By controlling the above-mentioned fixed level, the frequency of garbage collection and the time required for each garbage collection can be controlled.

When the memory block EMBL2 in FIG. 13 is erased, the memory is composed of only valid pages and erased pages. After that, as described above, the write operation including the new write and the update write is executed in the serial order on the erased unused pages.

The above embodiments are summarized below.

(Supplementary Note 1) In a flash memory having a plurality of pages having a data area and a management area corresponding to the data area, and having a plurality of memory blocks in erase units, the data writing is This is performed for erased pages, and the management area of each page includes a page ID area in which a page ID that identifies a page is written when data is written and a plurality of page IDs that have the same page ID when the data is written. A first position flag area in which information specifying the write target page at the latest data write position is written.

(Supplementary Note 2) In Supplementary Note 1, in the first position flag area, a predetermined count value is written in the erased state, and each time the page having the same page ID is updated and written, the count value is updated. A flash memory in which a count value obtained by decrementing or incrementing is written.

(Supplementary Note 3) In Supplementary Note 2, when the data in the page having the predetermined page ID is read, the data of the page having the smallest or largest count value in the first position flag area is read as the valid data. Characteristic flash memory.

(Supplementary Note 4) In Supplementary Note 1, when data in a page having a predetermined page ID is deleted, the page ID concerned is deleted.
A flash memory in which information indicating a deletion state is written in the first position flag area of a page having

(Supplementary Note 5) In Supplementary Note 1, further, the management area has a second position flag area in which information for specifying the final write position of the write target page is written when the data is written, The flash memory is characterized in that the write operation is performed on the plurality of erased pages in a serial order.

(Supplementary Note 6) In a flash memory having a plurality of pages having a data area and a management area corresponding to the data area, and having a plurality of memory blocks in erase units, the page of each page is The management area has a second position flag area in which information for specifying the write target page at the final write position is written when data is written, and the data is written according to the information in the second position flag area. The operations are performed on the plurality of erased pages in a serial order, and when the data writing operation to the memory block other than the transfer memory block is completed, the garbage collection is performed, and the garbage collection is most performed. The effective data in the memory block to be pruned that has the effective page written early. Flash memory, characterized in that the data is written into the transfer memory block, then deletes the organizing target memory block, specify the unused memory blocks that were erased last new transfer memory blocks.

(Supplementary Note 7) In Supplementary Note 6, a predetermined count value is written in the second position flag area in the erased state, and the count value obtained by decrementing or incrementing the count value each time new writing is performed. A flash memory that is written with a value.

(Supplementary Note 8) In Supplementary Note 6, the management area includes a page ID area in which a page ID for specifying a page is written when data is written, and a plurality of pages having the same page ID in writing the data. And a first position flag area in which information for specifying the write target page at the latest data write position is written.

(Supplementary note 9) In Supplementary note 8, when the already written data is updated and written, the information different from the first position flag area of the update source page is the first position flag of the update destination page. The flash memory is written in an area, and as a result, the update source page becomes an invalid page and the update destination page becomes a valid page.

(Supplementary Note 10) In Supplementary Note 6, the flash memory is characterized in that the garbage collection is performed for all memory blocks having a page for storing valid data.

(Supplementary Note 11) In a flash memory having a plurality of pages having a data area and a management area corresponding to the data area, and having a plurality of memory blocks in erase units having the plurality of pages, the management area is , (1)
Page I that identifies the page when the data is written
A page ID area in which D is written, and (2) a first position in which, when the data is updated and written, information identifying the write target page among the plurality of pages having the same page ID as the latest data write position is written. And a second position flag area in which information specifying the write target page to the final write position is written when the data is written, and the data writing is performed in the second position flag area. According to the above, the erased pages are sequentially performed, and when the erased page to be written reaches a certain level or less, garbage collection is performed. In the garbage collection, information on the first and second position flag areas is written. According to, the organized memory mem- bers having valid data and having the earliest written page. Flash memory, characterized in that Tsu valid data in the click, the writing to the transfer memory block, and then erases the organizing target memory block.

[0080]

As described above, according to the present invention, the number of times of writing between erase operations can be reduced. Further, wear leveling can be realized without providing an erase count counter.

[Brief description of drawings]

FIG. 1 is a configuration diagram of one conventional flash memory.

FIG. 2 is an overall configuration diagram of a flash memory according to the present embodiment.

FIG. 3 is a configuration diagram of a memory cell array of a NAND flash memory.

FIG. 4 is a detailed configuration diagram of a flash memory according to the present embodiment.

FIG. 5 is a flow chart of a page write operation.

FIG. 6 is a diagram illustrating a page write operation.

FIG. 7 is a diagram for explaining a write operation.

FIG. 8 is a diagram for explaining a write operation.

FIG. 9 is a flowchart showing an operation of garbage collection.

FIG. 10 is a diagram for explaining garbage collection.

FIG. 11 is a diagram for explaining garbage collection.

FIG. 12 is a diagram for explaining garbage collection.

FIG. 13 is a diagram for explaining garbage collection.

[Explanation of symbols]

EBLK Memory block in erase unit T-BLK Transfer memory block PAGE Page PID Page identifier, page ID F1 First position flag, Page latest write position flag F2 Second position flag, Last write position flag ECC Error correction code Area DBL Bad block information 11 Management area 20 Data area

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G11C 17/00 601B (72) Inventor Isamu Nakajima 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu In-house F-term (reference) 5B025 AA01 AD04 AD08 AE01 AE05 5B060 AA10

Claims (5)

[Claims] 1. In a flash memory having a plurality of pages having a data area and a management area corresponding to the data area, and having a plurality of memory blocks in erase units, the data writing has been completed. Page ID area in which a page ID identifying a page is written when data is written, and a plurality of pages having the same page ID when the data is written. Among them, a flash memory having a first position flag area in which information for specifying the write target page at the latest data write position is written. 2. A predetermined count value in an erased state is written in the first position flag area according to claim 1,
A flash memory in which a count value obtained by decrementing or incrementing the count value is written each time update writing is performed on a page having the same page ID. 3. A management area of each page in a flash memory having a plurality of pages each having a data area and a management area corresponding to the data area, and having a plurality of memory blocks in erase units. Has a second position flag area in which information for specifying the write target page at the final write position is written when data is written, and the data write operation is performed according to the information in the second position flag area. , The plurality of erased pages are serially processed, and the garbage collection is performed at the time when the data writing operation to the memory block other than the transfer memory block is completed, and the fastest writing is performed in the garbage collection. The valid data in the memory block to be sorted that has the valid page Writing to the transfer memory block,
After that, the flash memory is characterized in that the memory block to be rearranged is erased, and the last unused unused memory block is designated as a new transfer memory block. 4. In appendix 3, a predetermined count value is written in the second position flag area in an erased state, and a count value obtained by decrementing or incrementing the count value each time new writing is performed. Flash memory characterized by being written. 5. The management area according to claim 3, wherein the management area includes a page ID area in which a page ID specifying a page is written when data is written, and a plurality of pages having the same page ID when the data is written. A flash memory having a first position flag area in which information for specifying the write target page at the latest data write position is written.