JP2003208339A - Processor operation display device and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently perform optimization of a reduced evaluation program regarding a processor operation display device and a recording medium. <P>SOLUTION: The processor operation display device 1 having functions for performing performance evaluation of a processor and for displaying execution results of an evaluation program consisting of a plurality of functions, is provided with a graph display part for displaying the execution results of the evaluation program by making a graph of them in an order of executed steps, a corresponding information display part for comparing function list data in which starting addresses and ending addresses of the respective functions in the evaluation program are described with trace data in which a state of the processor in the case of execution of the evaluation program in order of the executed steps and for displaying in what functions the respective execution steps are executed and an association display part for displaying the graph display part and the corresponding information display part by associating them with the executed steps. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU (Central Processing Unit: Central Processing Unit),
MPU (micro processor unit), DSP
(Digital signal processor), Logic IC
In a data processing device that performs data processing for optimizing a reduced evaluation program that evaluates the performance of various processors such as, the numerical data generated by the tool management means that combines and executes each tool group is used as a basis. Further, the present invention relates to a processor operation display device and a program having a function of visually displaying the numerical data so as to intuitively grasp an optimized portion in a reduction evaluation program.

The present invention provides a standard evaluation program for software simulation for verifying the logic of a processor and performance evaluation in some steps of developing a new processor, for example. It is used to provide an environment for efficiently performing the process of optimizing (reducing) a reduced evaluation program (a program that simplifies each of the evaluation programs) that enables the same characteristics in a short time. Is.

A characteristic of the evaluation program is CPI (Cycle Per Inst) which means cache miss and instruction execution efficiency.
ruction: Average number of clocks per instruction) etc. In other words, it is necessary to optimize (reduce) the functions and variables in the program so that these cache misses and CPI do not change, and the function and variable parts are efficiently extracted from the graph of cache miss data, CPI data, etc. There is a need.

As a result, in software simulation, the evaluation can be performed in a much shorter time than the time required for the evaluation work using the evaluation program, and as a result, the development time of a new processor is shortened. It is something. In recent years, development competition for a wide variety of processors has intensified, and it has been demanded to reduce the development time and development cost.

[0005]

2. Description of the Related Art A conventional example will be described below.

FIG. 17 is an explanatory diagram of a conventional example, and FIG.
FIG. 3 is an explanatory diagram of the PU evaluation method, and FIG. B is an explanatory diagram of the CPU evaluation support device. Conventionally, in the process of developing a processor used in various computers and the like, for example, a CPU, evaluation has been performed for each function of the CPU.

In this case, a simulation program in which the functions of the CPU are realized by a program is used, and an evaluation program is used for this simulation program to evaluate the performance for each function of the CPU. However, this evaluation program is large in scale, and the simulation program generally has a slower operation speed than the CPU, so that the evaluation takes a lot of time. Therefore, create a reduced evaluation program that is a reduction of the evaluation program,
The CPU is evaluated using this reduction evaluation program.

However, when the evaluation is performed using the reduction evaluation program, it is necessary to confirm whether or not the same performance as the evaluation by the evaluation program can be performed. Each function was compared, and optimization was performed so that they would have approximately the same performance.

The architecture of the optimization method of the reduction evaluation program is simple, and its logic has been verified by a calculation formula or the like. However, in recent years, the CPU architecture has become more and more complicated, and it has become necessary to verify logic using a logic simulator and confirm test items using trace data of an evaluation program within a realistic time. . Also, the evaluation program itself has a tendency to increase its execution steps.

By the way, conventionally, when the CPU is evaluated, the CPU evaluation support device as shown in FIG. 17B has been used. This CPU evaluation support device uses an arbitrary computer, and includes a computer main body, a display device, and an input device.
Then, when the CPU is evaluated by the CPU evaluation support device, the operator operates the input device,
By starting a program provided in the computer main body, performing a predetermined evaluation by the program, and displaying the evaluation result data on the display screen of the display device,
The evaluation was done manually.

In this case, for example, in order to optimize the reduction evaluation program for cache miss, trace data, function list data, and cache miss data are generated from the reduction evaluation program, and these data are displayed on the display screen of the display device. To display. Then, the optimization is performed by repeating the process of manually observing the displayed data and correcting the corresponding portion of the reduction evaluation program.

[0012]

SUMMARY OF THE INVENTION The above-mentioned conventional device has the following problems. That is, C
The evaluation of the PU was performed using the CPU evaluation support device, but there was no established method for optimizing (reducing) the evaluation program necessary for developing the CPU.

[0013] Further, there are individual tools that support it, and the optimization process is only subdivided into individual tools. Also, there was no association between numerical data and visual information. Furthermore, optimization of the reduction evaluation program is a manual work. Therefore, C
The PU development time was long and the development cost was high.

The present invention solves such a conventional problem, enables efficient optimization of a reduction evaluation program, and enables efficient development of various processors using the reduction evaluation program. By doing so, the development time of the processor is reduced and the development cost is reduced.

[0015]

In order to achieve the above object, the present invention has the following constitution.

(1): A processor operation display device having a function of evaluating the performance of a processor and displaying the execution result of an evaluation program consisting of a plurality of functions, and graphing the execution result of the evaluation program in the order of execution steps. And a graph display area (graph display area) for displaying, function list data describing start addresses and end addresses of respective functions in the evaluation program, and a trace recording the state of the processor when the evaluation program is executed in the order of execution steps. Correspondence information display area (correspondence information display area) that compares the data and displays which function executed each execution step
And a related display unit for displaying the graph display unit and the correspondence information display unit in association with the execution step.

(2): In the processor operation display device according to (1), the correspondence information display section is not displayed in the same drawing area, but the correspondence information display section is scrolled to display more information. It is characterized in that it is provided with a layout display control means having a function of increasing the list of a large number of functions by making the function of (1) compatible with the graph display section.

(3): In the processor operation display device of (1) above, a line is drawn between an arbitrary point on the graph of the graph display unit and a point indicated by the corresponding information display unit corresponding to the execution step of the arbitrary point. It is characterized in that it is provided with a line drawing means connecting with.

(4): In the processor operation display device of (1) above, when an arbitrary section of the graph display section is selected,
It is characterized in that it has an enlarged display means for enlarging and displaying so that the display of each function of the corresponding information display section corresponding to the range is displayed in more detail.

(Operation) (a): In the above (1), the related display means is a graph display section in which the execution result of the evaluation program is graphed and displayed in the order of execution steps, the address of trace data and the address of function list data And a corresponding information display section that displays which function each execution step was executed in is displayed in association with each other.

As described above, since the graph display section and the correspondence information display section are displayed in association with each other, it is possible to directly judge which function in the evaluation program is the execution result. The parts can be identified intuitively and efficiently.

As a result, the reduction evaluation program can be efficiently optimized, and various processors using the reduction evaluation program can be efficiently developed. for that reason,
It is possible to reduce the development time of the processor and reduce the development cost.

(B): In the above (2), the layout display control means does not display the corresponding information display section in the same drawing area, but scrolls the corresponding information display section to increase the number of display areas. By making the function of (3) compatible with the graph display unit, it becomes possible to enhance the list of a large number of functions.

(C): In the above (3), in the line drawing means, the graph display unit draws a line from an arbitrary point on the graph to a point indicated by the corresponding information display unit corresponding to the arbitrary point (the line is drawn). draw). In this way, it is possible to efficiently check the function called at an arbitrary position on the graph without overlooking it.

(D): In the above (4), when the arbitrary display section of the graph display section is selected, the enlarged display means displays the details of each function in the corresponding information display section corresponding to the range of the section. Enlarge the display as shown in.

With this configuration, it becomes easy to know the function corresponding to the local variation of the graph, and it is possible to efficiently know the more appropriate optimization part of the reduction evaluation program.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

§1: Description of Functions of Processor Operation Display Device and Data Processing Device (1): Description of Processor Operation Display Device FIG. 1 is a configuration diagram of the processor operation display device. The processor operation display device 1 shown in FIG. 1 is for optimizing an evaluation program for evaluating the performance of a new processor in the process of developing a new processor to a reduced (simplified for each step) evaluation program. Data processing device 2
This is a device that displays the data created in step 3 on the screen. In the present embodiment, the display of processor evaluation data of the CPU regarding cache miss data of the cache memory built in the CPU will be described.

In the processor operation display device 1, for example, a display unit 3 composed of a display device having a liquid crystal display screen, a display control unit 4 for controlling display of data on the screen of the display unit 3, A cache miss data storage unit 15 for storing cache miss data, a trace data storage unit 16 for storing trace data, and a function list data storage unit 17 for storing function list data.
And a reduced evaluation program data storage unit 18 storing reduced evaluation program data.

The display control unit 4 also includes a window layout unit 5 for performing window layout processing, a scroll control unit 6 for performing scroll control, an enlargement display unit 7 for performing enlargement display processing, and a graph for performing graph drawing processing. Drawing unit 8, first associating unit 10 that performs associating processing of the drawn graph and corresponding information, and second associating unit 11
Is equipped with.

The first associating unit 10 is a processing means for associating the cache miss data with the execution section (execution step), and the second associating section 11 has the function list and the execution section (execution step). It is a processing means for associating execution steps).

The data processing device 2 is a device for creating data for optimizing a reduced evaluation program for reducing the evaluation program for evaluating the performance of the processor in the process of developing a new processor. Part 3
While the person viewing the data displayed on the screen operates the input device or the like manually, the processing is performed.

Then, the cache miss data, the trace data, and the function list data created by the data processing device 2 are sent to the processor operation display device 1, and the cache miss data storage unit 15 and the trace data storage unit 16 are sent.
And stored in the function list data storage unit 17.

In the processor operation display device 1, display processing on the display unit 3 is performed using the stored data. A combination of the processor operation display device 1 and the data processing device 2 will be referred to as a processor development support device.

(2) Description of display function of processor operation display device and data processing function of data processing device FIG. 2 is an explanatory diagram of the processor operation display device and the data processing device. FIG. 3 is an explanatory diagram of a display function of the processor evaluation result, and FIG. 4 is an explanatory diagram of a partially enlarged display function of the processor evaluation result. The display functions of the processor operation display device and the data processing device will be described below with reference to FIGS.

Description of FIG. 2 In FIG. 2, b is each generated data (e in FIG. 2,
This is a data display function of the processor operation display device 1 that displays graphs and numerical data in association with each other based on f, g, h). c is a tool of the data processor 2 that integrates the tools in the tool group (d in FIG. 2) and causes the tools to generate various data (f, g, h in FIG. 2) from the reduced evaluation program data (e in FIG. 2). It is a tool management function.

D is a tool group which is a collection of tools called when generating each data (f, g, h in FIG. 2). e is reduced evaluation program data in which the evaluation program is being optimized or optimized. f is function list data generated based on the reduction evaluation program (e in FIG. 2). g is trace data recording the execution status of the reduced evaluation program data (e in FIG. 2). h
Is cache miss data recording the data of the cache miss that occurred when the reduced evaluation program data (e in FIG. 2) was executed.

Note that e, f, g, h, c, d are those in the data processing device 2, e, f, g, h are numerical data, and c, d are programs. It is a means.

Description of FIG. 3 FIG. 3 is a diagram for explaining the function of displaying the processor evaluation result (processor evaluation result display function explanatory diagram). In FIG. 3, a is a graph display unit (graph display area) that graphs and displays the cache miss data. b
Is the error rate that represents the Y axis (vertical axis of the graph), and c is the time (horizontal axis) that represents the progress. Further, d is a function list (e, f, g, h in FIG. 3) corresponding to each point of the graph.
Is a line representing (drawn line).

E and g are addresses, f and h are functions corresponding to the addresses, and i is a correspondence information display section (display area of correspondence information) for displaying numerical values (function list) corresponding to the graph.
Is. k is a scroll bar for scrolling a large number of function lists to find a function list called at an arbitrary point of the graph, and is operated by an operator.

Description of FIG. 4 FIG. 4 is an explanatory view of a partially enlarged display function of the processor evaluation result. By specifying a specific range in FIG. 3 (see j in FIG. 3), the specified range The graph part is enlarged and the detailed list of the corresponding function list (Fig. 4) is displayed.
The display of e, f, g, and h) is described.

As described above, the evaluation program is optimized by drawing a line (drawing a line) between an arbitrary point of the graph of the graph display section a and the corresponding function list of the correspondence information display section i. Since the location can be easily specified, the optimization (reduction) process of the evaluation program can be efficiently performed, and as a result, the development time of a new processor can be shortened.

§2: Description of data processing function of data processing device and display function of CPU operation display device (1): Description of CPU operation display device FIG. 5 is a block diagram of the CPU operation display device. The CPU operation display device 12 shown in FIG. 5 is an example in which the processor operation display device 1 is applied for CPU operation display.
This is a device for displaying on the display screen of the CPU operation display device 12 data (CPU operation data) created by the data processing device 21 for optimizing the evaluation program for evaluating the performance of U to a reduced evaluation program.

The CPU operation display device 12 includes, for example, a display unit 3 composed of a display device having a liquid crystal display screen, and a display control unit 4 for controlling the display of data on the screen of the display unit 3. A cache miss data storage unit 15 for storing cache miss data, a trace data storage unit 16 for storing trace data, and a function list data storage unit 17 for storing function list data.
And a reduced evaluation program data storage unit 18 storing reduced evaluation program data.

The display control unit 4 also includes a window layout unit 5 for performing window layout processing, a scroll control unit 6 for performing scroll control, an enlargement display unit 7 for performing enlargement display processing, and a graph for performing graph drawing processing. Drawing unit 8, first associating unit 10 that performs associating processing of the drawn graph and corresponding information, and second associating unit 11
Is equipped with.

The first associating unit 10 is a processing means for associating cache miss data with an execution section (execution step), and the second associating section 11 has a function list and an execution section (execution step). It is a processing means for associating execution steps).

The data processing device 21 is a device for creating data for optimizing the reduced evaluation program for reducing the evaluation program for evaluating the performance of the CPU, and the data displayed on the display unit 3 can be changed by a person. The processing is performed while manually operating an input device or the like while looking.

Then, the cache miss data, trace data, and function list data created by the data processing device 21 are sent to the CPU operation display device 12, and the cache miss data storage unit 15 and the trace data storage unit 1 are sent.
6, the function list data storage unit 17, and the reduced evaluation program data storage unit 18. Then, the CPU operation display device 12 performs display processing on the display unit 3 using the stored data.

The combination of the CPU operation display device 12 and the data processing device 21 will be referred to as a CPU development support device (see the conventional example).

(2): the display function of the CPU operation display device,
Description of Data Processing Function of Data Processing Device FIG. 6 is an explanatory diagram of the CPU operation display device and the data processing device. FIG. 7 shows an example of the CPU evaluation result display function, and FIG. 8 shows the CP.
An example of a partially enlarged display function of the U evaluation result, and FIG. 9 is an example of display of a graph and a function list data correspondence line. The display functions of the CPU operation display device and the data processing device will be described below with reference to FIGS.

A: Description of Reduction Evaluation Program Generation Process in Data Processing Device 21 The reduction evaluation program generation process in the data processing device 21 is as follows.

(B): With respect to the evaluation program, a graph of the average cache miss rate and the cache miss rate of the entire processing is created.

(B): Based on the result of (a), the variables of the evaluation program and the number of loops are reduced in accordance with the following procedure.

[A]: Arrangement of a graph pattern (a graph of the variation of the cache miss rate, the shape of which is called a graph pattern) [a-1]: Created based on the trace data of the evaluation program A graph of the fluctuation is created from the data of the cache miss rates obtained. From the multiple graphs of cache miss rate fluctuations created, find graph patterns that appear to be similar. Based on the found graph pattern, the graph is divided into several Phases with the pattern as the base point.

[B]: Check validity of classification as Phase [a-2]: Correlation of each pattern with function Graphs classified in [a-1] and the function used therein Correspond with. This is "Fcoun
This is done using a tool called "t". It can be created using the trace data from which the graph is created.

[A-3]: Confirm numerical approximation of similar pattern in each Phase Confirm the numerical approximation of the cache miss rate shown on the y-axis in each cache miss rate graph.

[A-4]: It is confirmed that the processing of each Phase is similar. The respective shapes of the graphs showing the fluctuations of the cache miss rate constituting each Phase are compared. It is confirmed whether or not there is a graph close to each other in each Phase and its possibility.

[C]: Confirmation of reduction range [a-5]: Indicates the range of program processing included in Phase.

According to the function name corresponding to the pattern from the above [a-2], a corresponding area is established on the actual program source code and the range to be reduced is determined.

(C): As a result of the above (b), if it can be confirmed that the pattern (shape) of the graph of the average cache miss rate and the cache miss rate of the entire processing of the reduced evaluation program is not different from that of the evaluation program, the development is performed. CP inside
The CPU performance evaluation under development is carried out by U simulation, and the performance evaluation is compared with the conventional (old) CPU.

B: Description of FIGS. 6 to 9 In FIG. 6, a process of generating various data (e, f, g, h) will be described, and in FIG. 7, an example of the entire display of the graph and the function list will be described. In FIG. 9, an example of enlarging and displaying an arbitrary designated range of the graph will be described, and in FIG. 9, an example of the graph and the function list correspondence line will be described.

(1): A tool for selecting a reduction evaluation program to be optimized from the reduction evaluation program data (e in FIG. 6) and extracting the function and its address defined therein ( The tool management mechanism (c in FIG. 6) instructs the tool group (d in FIG. 6) to execute the program.

(2): The tool that has received the instruction generates function list data from the corresponding program data of the reduced evaluation program.

(3): Next, the tool management function first generates a tool for generating trace data (g in FIG. 6) in order to generate cache miss data (h in FIG. 6). Command d).

(4): Tool group that has received the command (d in FIG. 6)
Executes the reduction evaluation program and collects trace data (g in FIG. 6).

(5): When the collection of the trace data (g in FIG. 6) is completed, the tool management function (c in FIG. 6) generates the cache miss data (h in FIG. 6) and the tool group (in FIG. 6). command d).

(6): Tool group that has received the command (d in FIG. 6)
Generates cache miss data (h in FIG. 6) based on the trace data.

(7): Since all the data have been collected, the data display function is to function list data (also called function / address correspondence data) (f in FIG. 6) and cache miss data (h in FIG. 6). Access (of FIG. 6) and display the result (FIG. 7).

(8): Next, for the entire display, a graph display section (a in FIG. 7) for displaying a graph drawn based on the cache miss data (h in FIG. 6) in FIG. 6 and the function list data. The corresponding information display section (i in FIG. 7), which is displayed as a list based on (f in FIG. 7), has a corresponding line in an L-shape in the function list called at points at equal time intervals on the graph. Be drawn.

For example, the point j in the graph of FIG. 7 corresponds to the address "323" shown by e of FIG.
It can be seen that it corresponds to 8 "and" calcl ".
That is, the function list that enters the steady state is known from j of FIG. 7, and at least the cache does not change among the characteristics of this function, so the processing is optimized (reduced).
It seems that there is a possibility.

The corresponding function is scroll (see FIG. 7).
By moving k) up and down, it is possible to easily retrieve even a large number of functions defined in the evaluation program.

(9): Enlargement will be described with reference to FIG. When it is desired to enlarge the point (j) in the graph of FIG. 7 and to know the corresponding function list, the range of (j) of FIG. 7 is designated with the mouse. Then, as shown in FIG. 8, j of FIG. 7 is enlarged, and the function part that was only visible as calcl (f of FIG. 7) in FIG. 7 is further added to the function list ( Parts (g, h) in FIG. 8 are displayed as detailed information. This makes it possible to intuitively grasp which part of the point f designated in FIG. 7 should be optimized.

(10): An example of a graph and a function list correspondence line will be described with reference to FIG. From the points in the graph display section (a in FIG. 9) at even intervals of the graph to the points in the graph by the corresponding lines drawn in the corresponding information display section (b in FIG. 9) to the corresponding function list. You can intuitively and accurately know the corresponding function list.

Further, in the correspondence information display section (b in FIG. 9),
A part of the list of the function list is displayed, and the corresponding function list is not necessarily displayed there. In this case, if there is no corresponding line, it will be overlooked. For example, it can be easily seen that there are corresponding function lists below the currently displayed corresponding information display section (b in FIG. 9), such as c and f in FIG. 9.

C: Description of Trace Data The structure of trace data is shown in FIG. 10A and FIG. 10B is an example. The trace data is a set of execution steps, and each execution step has four elements (Program Counter, Instruct) as shown in the middle of FIG.
ion Word, Effective Address, Flags).

The trace data is an element generated by executing a reduction evaluation program (execution module) on the shadow by a tool called "shadow" for simulating a CPU (see FIG. 10A). It is created by writing the information in (see) to a file.

D: The data structure of the function list (Function List) is shown in FIG. 10C and its example in FIG. 10D. An explanatory diagram of the function list generation process is shown in FIG.

The function list data is obtained by creating a reduced evaluation program (execution module) by a tool called "funcList", and then from the data portion relating to the function and its address defined in the reduced evaluation program, It is created by extracting those portions (writing data) (see FIG. 11A). And
The data of the function list has a function name, a start address and an end address, as shown in FIGS. 10C and 10D.

When the function list data is displayed as a list based on the above data, the execution address executed within 400K steps from the current execution step is acquired from the trace data. General CPU
, The execution address is derived from the Program Counter in the trace data. By comparing the acquired execution address with the start and end addresses defined in the function list data (see FIGS. 10C and 10D), it is determined which function the execution step is executed on. Prove.

E: Structure of cache miss data and description thereof The structure of cache miss data is shown in FIG. 11B and its example in FIG. 11C.

For cache miss data, after creating trace data with a cache simulation tool called "Cachesim", the above Cachesim is one of the elements of the trace data, Instruction Code, Effective
It is created by referring to Address (see FIG. 10A) and writing the information of cache miss occurring in Cachesim to a file.

F: Description of the processing of the data processing device 21 The processing of the data processing device 21 is as follows. In the data processing device 21, a trace data generating means, a function list generating means, a cache miss data generating means, a cache miss data, which are configured by a program in advance,
An execution section associating unit, a function list-execution section associating unit, and the like are provided.

Then, in the data processing device 21, the trace data generating means generates the trace data from the reduced evaluation program data. Next, the function list generation means generates function list data from the reduced evaluation program data. Then, the cache miss data generation means generates the cache miss data from the generated trace data.

Next, the cache miss data-execution section associating means acquires the cache miss rate within a fixed number of execution steps and sends it to the CPU operation display device 12. Next, the function list-execution section associating means acquires an address within a certain number of execution steps from the trace data, acquires a function name corresponding to the address from the function list data,
It is sent to the CPU operation display device 12.

Next, based on the data sent from the function list-execution section associating means and the cache data-execution section associating means, respectively, the corresponding information display section i of the CPU operation display device 12 and the clutter display. Calculate the screen coordinates and display the result in the CPU
It is sent to the operation display device 12.

Then, plotting from the trace data, the function list, and the cache miss data on a graph is performed as follows. That is, from the current execution step,
For example, the address executed within 400K steps is acquired from the trace data, the acquired address is compared with the start and end addresses defined in the function list data, and the address is used in the acquired address. Display the list of function names.

Similarly, the cache miss data is acquired from the current execution step, for example, for 400K steps, and is drawn in the graph. Thereby, the graph is plotted from the trace data, the function list, and the cache miss data.

§3: Description of Processing by Flowchart FIG. 12 is a CPU operation display processing flowchart (part 1), FIG. 13 is a CPU operation display processing flowchart (part 2), and FIG. 14 is a CPU operation display processing flowchart (part 3). FIG. 15 is a CPU operation display processing flowchart (part 4).

The CPU will be described below with reference to FIGS.
The operation display process will be described. Note that S1 to S37 indicate processing steps.

First, the window layout section 5 creates a main window (S1), and a graph display section for displaying a graph of the cache miss rate is displayed above the main window (S2). In addition, a corresponding information display section that displays the corresponding function name is displayed at the bottom of the main window (S
3). Then, the display control unit 4 sets the current execution step to 0 (S4).

Next, the first associating unit 10 acquires the cache miss rate data for 400K steps from the current execution step (S5), and from the current execution step,
The address executed within 400K steps is acquired from the trace data (S6). Then, the acquired address is compared with the start and end addresses defined in the function list data to create a list of function names used in the acquired address (S7).

Next, the graph drawing unit 8 plots the cache miss rate corresponding to the current execution step on the graph display unit, and the display control unit 4 handles the correspondence based on the correspondence information of the second correspondence unit 11. "*" Mark is added to the line of the corresponding function name in the information display section (S8). Next, the display controller 4
Draws a corresponding line from the point of the corresponding cache miss rate to the corresponding function name (S9). Then, the display control unit 4 adds the current execution step by 400K steps (S10), and determines whether all the data of the cache miss rate have been displayed (S11).

As a result, when all the cache miss rate data are not displayed, the process proceeds to S5, and when all the cache miss rate data is displayed, the display control unit 4 performs the scroll operation. It is determined whether it has been performed (S12). As a result, when the scroll operation is performed, the process proceeds to S21 (described later), and when the scroll operation is not performed, it is determined whether the cache miss ratio graph enlarged display operation is performed. Yes (S1
3).

As a result, when the cache miss ratio graph is enlarged and displayed, the process proceeds to S29 (described later). When the cache miss ratio graph is enlarged and not displayed, It is determined whether or not the operation of ending the display has been performed (S14). As a result, if the operation of ending the display is not performed, the process proceeds to S13, and if the operation of ending the display is performed, this process is ended.

In the process of S12, when the scroll operation is performed, the scroll control unit 6 determines whether the scroll direction is the upward direction (S21). If the scroll direction is the upward direction, the scroll amount is increased. The variation amount Δ of (S2
2) The current function name is moved upward by the display variation amount Δ (S23). Then, as a result of the upward movement, the display control unit 4 displays the function name of the high address corresponding to the variation amount Δ in the vacant lower part (S24).

Next, the display control unit 4 determines whether or not the scroll is continued (S25), and if the scroll is continued, the process proceeds to S21. If the scroll is not continued, the process returns. Further, in the process of S21, if the scroll direction is not the upward direction, the scroll is performed in the downward direction.
Is calculated (S26), and the current function name is moved downward by the display variation amount Δ (S27).

As a result of the downward movement, the display control unit 4 displays the function name of the low address corresponding to the variation amount Δ on the vacant upper part (S28), and shifts to the processing of S25. If an operation for enlarging the cache miss rate graph is performed in the process of S13, the enlarging display unit 7
Sets the start point of the expansion range as the current step (S29). Then, the difference between the step at the end point of the expansion range and the step at the start point of the expansion range is calculated and set as the number of display steps (S30).

Next, the first associating unit 10 acquires the cache miss rate data for 400K steps from the current execution step (S31), and is executed within 400K steps from the current execution step. The address is acquired from the trace data (S32). Then, the acquired address is compared with the start / end address defined in the function list data to create a list of function names used in the acquired address (S33).

Next, the graph drawing unit 8 plots the cache miss rate corresponding to the current execution step on the graph display unit, and the display control unit 4 displays "*" on the line of the corresponding function name on the correspondence information display unit. "(S34), a corresponding line is drawn from the corresponding cache miss rate point to the corresponding function name (S35), and the current execution step is 400.
K steps are added (S36).

Then, the display control section 4 judges whether or not the number of display steps has been displayed (S37), and if it is judged that the number of display steps has not been displayed, the processing shifts to S31. If the number of display steps is displayed, the process returns.

By the processing described above, it is optimal to satisfy the list items of the original evaluation program, execute the logic simulator, and confirm the test items using the trace data within a realistic time. (Reduction)
By creating a simplified evaluation program (reduced evaluation program), it becomes possible to perform the measurement evaluation within a realistic time while maintaining the accuracy of the CPU evaluation. In this way, according to the present invention, by visually displaying numerical data, the optimization (reduction) operation can be efficiently performed.

As described above, in the case of performing the operation display, the address executed within 400K steps from the current execution step is acquired from the trace data, and the acquired address and the function list are acquired. By comparing the start and end addresses defined in the data, it becomes clear on which function the execution step is executed. Display the list of function names from this result.

Similarly, cache miss data is acquired from the current execution step, for example, for 400K steps, and drawn in the graph. Thereby, the graph is plotted from the trace data, the function list, and the cache miss data.

In the above example, the cache miss data is graphed and displayed as the execution result of the evaluation program. However, the present invention is not limited to this example, and the CPI (average number of clocks per instruction) ), Etc., and the result of control by the processor, etc., can be similarly applied. As a result of the control, control of screen drawing, control of the storage device, and the like can be considered.

Further, in the above example, the optimization of the reduced evaluation program in which the evaluation program for the performance evaluation of the processor is reduced has been described. However, the present invention is not limited to such an example, the program development of the processor and the processor The same can be applied to the verification by the control result of 1.

§4: Description of Specific Device Example, Program, and Recording Medium Recording the Program FIG. 16 shows a specific device example. The processor operation display device 1 (or the CPU operation display device 12) can be realized by any computer such as a workstation or a personal computer. This device is shown in FIG.
As shown in FIG. 6, the computer main body 31, a display device 32 connected to the computer main body 31, an input device (keyboard / mouse, etc.) 33, a removable disk drive (referred to as “RDD”) 34, a hard disk device (“HDD ")) And the like.

In the computer main body 31, a CPU 36 for performing various internal controls and processes, a ROM 37 (nonvolatile memory) for storing programs and various data, a work memory 38, and interface control. Unit (referred to as “I / F control unit”) 39 and communication control unit 4
0 and the like are provided. The RDD 34 includes a flexible disk drive, an optical disk drive and the like.

In the apparatus having the above structure, for example, an HDD
A program for realizing the processing of the processor operation display device 1 (or the CPU operation display device 12) is stored in the magnetic disk (recording medium) 35, and the CPU 36 reads and executes this program, The processing performed by the processor operation display device 1 (or the CPU operation display device 12) is executed.

However, the present invention is not limited to such an example. For example, a program is stored in the magnetic disk of the HDD 35 as follows, and this program is stored in the CPU 36.
It is also possible to perform the above processing by executing.

: Read a program (program data created by another device) stored in a removable disk created by another device by the RDD 34,
It is stored in the recording medium of the HDD 35.

Data such as a program transmitted from another device via the communication line is received via the communication control unit 40, and the data is stored in the recording medium (magnetic disk) of the HDD 35.

Although the CPU evaluation data has been described in the above example, the present invention is not limited to such an example.
It can be similarly applied to other various processors (CPU, MPU, DSP, logic IC, etc.).

In addition to the above description, the following configuration will be added.

(Supplementary Note 1) The performance of the processor is evaluated,
A processor operation display device having a function of displaying an execution result of an evaluation program composed of a plurality of functions, wherein a graph display unit for displaying the execution result of the evaluation program in the order of execution steps and each function of the evaluation program Function list data describing the start address and end address of the above is compared with trace data in which the state of the processor at the time of execution of the evaluation program is recorded in the order of execution steps, and which function is executed at each execution step is displayed. A processor operation display device comprising: an information display unit; and a related display unit that displays the graph display unit and the corresponding information display unit in association with an execution step.

(Supplementary Note 2) By scrolling the correspondence information display unit instead of displaying the correspondence information display unit in the same drawing area, more functions can be handled in the graph display unit. According to the above, the processor operation display device according to (Supplementary note 1), further comprising a layout display control means having a function of enhancing a list of a large number of functions.

(Supplementary Note 3) Line drawing means is provided for connecting an arbitrary point on the graph of the graph display section with a point corresponding to the execution step of the arbitrary point by the corresponding information display section with a line. The processor operation display device according to (Supplementary Note 1).

(Supplementary Note 4) Corresponding information corresponding to a range when an arbitrary section of the graph display section is selected in a state where the graph display section and the corresponding information display section are displayed in association with each other. The processor operation display device according to (Supplementary Note 1), further comprising an enlargement display unit that enlarges and displays the display of each function on the display unit in more detail.

(Supplementary Note 5) A graph display unit for evaluating the performance of a processor on a computer and displaying the execution result of an evaluation program composed of a plurality of functions in the order of execution steps and a start address of each function of the evaluation program A correspondence information display unit that compares the function list data describing the end address with the trace data in which the state of the processor at the time of execution of the evaluation program is recorded in the order of execution steps, and displays which function each execution step is executed by. And a program for realizing the function of a related display unit that displays the graph display unit and the correspondence information display unit in association with an execution step.

(Supplementary Note 6) A graph display section for evaluating the performance of a processor on a computer and displaying the execution result of an evaluation program consisting of a plurality of functions in the order of execution steps and a start address of each function of the evaluation program A correspondence information display unit that compares the function list data describing the end address with the trace data in which the state of the processor at the time of execution of the evaluation program is recorded in the order of execution steps, and displays which function each execution step is executed by. And a recording medium recording a program for realizing a function of an associated display unit that displays the graph display unit and the correspondence information display unit in association with an execution step.

[0120]

As described above, the present invention has the following effects.

(1): In Claims 1 and 5, the related display means is a graph display section for displaying the execution result of the evaluation program during processor operation in the form of a graph in the order of execution steps, and
The address of the trace data is compared with the address of the function list data, and the corresponding information display section for displaying which function each execution step is executed is displayed in association with the function.

In this way, since the graph display section and the corresponding information display section are displayed in association with each other, it is possible to directly judge which function in the evaluation program is the execution result, so that the relationship between the two is Visually intuitive and easy to understand.
For example, conventionally, the variable portion of the graph was identified, the execution step was specified, and the corresponding function name was identified. However, according to the present invention, there is an advantage that the correspondence between the graph portion and the function name can be recognized on one screen.

That is, since the graph display portion and the correspondence information display portion are displayed in association with each other, the optimized portion of the reduction evaluation program can be intuitively and efficiently identified. As a result, the reduction evaluation program can be efficiently optimized, and various processors using the reduction evaluation program can be efficiently developed. Therefore, it becomes possible to reduce the development time and the development cost.

(2): In claim 2, the layout display control means compares the address of the trace data with the address of the function list data and displays which function each execution step was executed by. By displaying more functions in the graph display section by scrolling the correspondence information display section instead of displaying all the sections in the same drawing area, a larger list of functions can be displayed. It becomes possible to raise.

In this way, an environment is realized in which a large number of functions are displayed in correspondence with each other on the graph. For example, in the past, when the number of function names was small, it was seen on one sheet of paper, but when the number of functions was large, multiple sheets of paper had to be prepared, and it was difficult to organize, manage, and associate with graphs. is there. However, in the present invention, since the scroll function is added, there is no need to organize and manage.

(3): In claim 3, the line drawing means is a graph display section for displaying the execution result of the evaluation program during the operation of the processor in the order of execution steps, and the address of the trace data and the address of the function list data. When associating with a corresponding information display unit that displays which function each execution step is executed by comparing with, any point of the graph of the graph display unit and the corresponding execution step of the arbitrary point, The points indicated by the correspondence information display section are connected by lines.

In this way, the function list called at an arbitrary position on the graph can be efficiently searched without missing the function list. For example, when the graph and the function name are simply displayed, the display may be mistaken.
In the present invention, by drawing the line as described above, the corresponding function is not overlooked.

(4): In claim 4, the magnifying display means is a graph display section for displaying the execution result of the evaluation program during processor operation in the form of a graph in the order of execution steps, the address of the trace data and the address of the function list data. When any section of the graph display section is selected while the corresponding information display section that displays which function executed each execution step is displayed in association, The function list portion of the corresponding information display section is enlarged and displayed so as to be displayed in more detail.

By doing so, it becomes easy to know the function corresponding to the local fluctuation of the graph, and it is possible to efficiently know the more appropriate optimization part of the reduction evaluation program.

In this way, an environment in which detailed functions can be displayed and specified can be realized. For example, conventionally
Even if you capture the whole image of the graph of the execution result of the evaluation program, in that case, many execution steps are drawn on a narrow screen, so it is difficult to read the execution step corresponding to any point on the graph, or conversely , If a part of the graph of the execution result of the evaluation program is displayed while maintaining a sufficient execution step interval, it may be difficult to capture the whole image.

However, if the present invention is applied, a part of the whole image is enlarged and the corresponding function name is known, so that it is possible to obtain local information of the graph while capturing the whole image of the graph. .

[Brief description of drawings]

FIG. 1 is a configuration diagram of a processor operation display device of the present invention.

FIG. 2 is an explanatory diagram of a processor operation display device and a processor evaluation data processing device according to the embodiment of the present invention.

FIG. 3 is an explanatory diagram of a display function of a processor evaluation result according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram of a partially enlarged display function of a processor evaluation result according to the embodiment of the present invention. .

FIG. 5 is a configuration diagram of a CPU operation display device according to the embodiment of the present invention.

FIG. 6 is an explanatory diagram of a CPU operation display device and a data processing device according to the embodiment of the present invention.

FIG. 7 is a display function example of a CPU evaluation result according to the embodiment of the present invention.

FIG. 8 is a partial enlarged display function example of a CPU evaluation result in the embodiment of the present invention.

FIG. 9 is a display example of a graph and a function list data correspondence line according to the embodiment of the present invention.

10A and 10B are numerical data and an explanatory diagram thereof (No. 1) in the embodiment of the present invention, FIG. A is a trace data structure, B is a trace data structure example, C is a function list data structure, and D is a diagram. Is an example of the data structure of the function list.

11A and 11B are numerical data and an explanatory view thereof (No. 2) in the embodiment of the present invention, FIG. A is an explanatory view of a function list generation process, B is a cache miss data structure, and C is a cache miss data structure. Here is an example.

FIG. 12 is a flowchart (part 1) of an operation display process according to the embodiment of the present invention.

FIG. 13 is an operation display processing flowchart (part 2) in the embodiment of the present invention.

FIG. 14 is an operation display processing flowchart (part 3) in the embodiment of the present invention.

FIG. 15 is an operation display processing flowchart (Part 4) in the embodiment of the present invention.

FIG. 16 is a specific device example according to the embodiment of the present invention.

FIG. 17 is an explanatory diagram of a conventional example, FIG. A is an explanatory diagram of a CPU evaluation method, and FIG. B is an explanatory diagram of a CPU evaluation support device.

[Explanation of symbols]

1 Processor operation display device 2 Data processing device 3 Display 4 Display control unit 5 Window layout section 6 Scroll controller 7 Enlarged display area 8 Graph drawing section 10 First associating unit 11 Second associating unit 12 CPU operation display device 15 Cache miss data storage 16 Trace data storage 17 Function list data storage 18 Reduced evaluation program data storage 21 Data processing device 31 Computer body 32 display device 33 Input device 34 Removable Disk Drive (RDD) 35 Hard Disk Drive (HDD) 36 CPU 37 ROM 38 memory 39 I / F control unit 40 Communication control unit

Claims (5)

[Claims] 1. A processor operation display device having a function of evaluating the performance of a processor and displaying an execution result of an evaluation program composed of a plurality of functions, wherein the execution result of the evaluation program is displayed in a graph in the order of execution steps. A graph display unit that compares the function list data describing the start address and the end address of each function in the evaluation program and the trace data in which the state of the processor at the time of executing the evaluation program is recorded in the execution step order, A processor, comprising: a correspondence information display unit that displays in which function the execution step is executed; and an association display unit that displays the graph display unit and the correspondence information display unit in association with the execution step. Operation display device. 2. Corresponding more functions to the graph display unit by scrolling the correspondence information display unit instead of displaying the correspondence information display unit on the same drawing area. Therefore, the processor operation display device according to claim 1, further comprising a layout display control unit having a function of enhancing a list of a larger number of functions. 3. A line drawing means for connecting an arbitrary point on the graph of the graph display section and a point indicated by the correspondence information display section corresponding to an execution step of the arbitrary point with a line. The processor operation display device according to claim 1, which is characterized in that. 4. A corresponding information display unit corresponding to a range when an arbitrary section of the graph display unit is selected in a state where the graph display unit and the corresponding information display unit are displayed in association with each other. 2. The processor operation display device according to claim 1, further comprising an enlarging display means for enlarging and displaying so that the display of each function is displayed in more detail. 5. A graph display unit for performing a performance evaluation of a processor on a computer and displaying the execution result of an evaluation program composed of a plurality of functions in the order of execution steps, and a start address of each function in the evaluation program. A correspondence information display unit that compares the function list data in which the end address is described with the trace data in which the state of the processor at the time of execution of the evaluation program is recorded in the order of execution steps, and displays in which function each execution step is executed. A program for executing related display means for displaying the graph display unit and the correspondence information display unit in association with an execution step.