JP2003194923A - Radar equipment and distance measuring method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide radar equipment and a distance measuring method which enables use of a low-speed inexpensive analog-to-digital converter, and reduction of the scale of hardware. <P>SOLUTION: By the radar equipment and the distance measuring method, distance measurement is carried out in the following way. A transmitting signal obtained by modulating a clock signal by a chaos signal is transmitted, and its reflected wave is received and sampled as 2N voltage signals at predetermined sampling timing. N voltage signals beginning from a voltage signal at the point of the leading edge of a chaos signal detected by a control unit 5 from the 2N voltage signals, are integrated by an analog integration portion 8 accumulating them on N voltage signals obtained last time. Its result is converted into a digital signal, and a delay time is calculated, and a distance-is measured. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radar device and a distance measuring method using a chaotic code.

[0002]

2. Description of the Related Art Conventionally, a signal wave in which a signal whose pulse width has been changed by a chaos code (chaotic signal) is modulated is radiated into space, the reflected wave is received and demodulated, and a fixed cycle is obtained. By performing a correlation operation between the signal sequence obtained by encoding with the chaotic signal previously transmitted, the time when the signal wave containing the specific chaotic signal was transmitted, and the reflected wave when the signal wave was reflected by the target. A technique (chaotic radar technique) for measuring the difference (delay time) from the time received as is being developed. The specific contents of this technique are described in, for example, British Patent GB2345149, "Time delay determination and
determination of signal shift "and the like.

The basic structure of a conventional chaotic radar is shown in FIG.
As shown in, the chaotic signal generator 51 and the arithmetic controller 5
2, a clock generator 53, a mixer 54, a transmitting antenna 55, a receiving antenna 56, and an A / D converter 57.
And a chaos processing unit 58.

The chaotic signal generator 51 outputs a pulse signal obtained by binarizing a chaotic signal (noise signal) as a chaotic signal. Here, specifically, the chaotic signal has a pulse width pseudo-randomly changed by a chaotic code. That is, ideally, one part of this chaotic signal does not exactly overlap another part.

The arithmetic control unit 52 includes a chaotic signal generation unit 51.
The chaotic signal output by is sampled at a predetermined cycle, converted into a digital signal, and output to the chaos processing unit 58. The clock generator 53 outputs a clock signal of a predetermined frequency. The mixer 54 includes a chaotic signal generator 51.
The chaotic signal input from the device and the clock signal output from the clock generation unit 53 are mixed and modulated, and the modulated signal is radiated via the transmission antenna 55.

The receiving antenna 56 receives and demodulates the reflected wave of the signal wave radiated from the transmitting antenna 55 which hits the target and is reflected, and outputs it to the A / D converter 57 as a baseband signal. The A / D converter 57 converts the baseband signal into a digital value at a predetermined cycle to generate a signal series, and outputs the signal series to the chaos processing unit 58. Then, the chaos processing unit 58 performs a correlation operation between the signal sequence and the sampled signal (original chaos signal) input from the operation control unit 52, and outputs the delay time information as the processing result.

The contents of the correlation processing here are as follows. That is, the pulse of the chaotic signal is set to "-1" and "1".
(A) The rising edge of the pulse is detected from the signal sequence obtained from the baseband signal, and the time point of this rising edge is used as the reference time. (B) After this reference time, a plurality of rising edges of the chaotic signal output from the chaotic signal generation unit 51 are detected, and the difference between the detection time of each rising edge and the reference time (τ1, τ2 ... τM; M is positive). Is calculated. (C) τ1, τ2 calculated from the reference time
.. .tau.M has elapsed, and a signal sequence made up of a plurality (N; N is an integer of 1 or more) of digital values (d1, d2, ... dN) obtained from the baseband signal is stored for each predetermined period. To do. As a result, M signal sequences are stored. (D) Each component (d1, d2, ...) Of the M signal sequences
dN) are respectively accumulated, and accumulated signal series (S1, S2,
... SN). (E) Find Sk (1 ≦ k ≦ N) at the point where the value suddenly changes in the accumulated signal sequence,
The time corresponding to the position of Sk is output as the delay time.

This is to make a plurality of received signal sequences for a certain period while shifting the time from the reference time to the rising edge of the chaotic signal to be transmitted, align the positions of these sequences, and average the plurality of received signal sequences. When (chaotic integration processing) is performed, the result of the averaging becomes “0” at the timing when the rising edges are concentrated and received, and the sign of the pulse is aligned around that, so the value changes rapidly from a negative value to a positive value. That is, the sign of the pulse varies and becomes "0" at other points.

A detailed explanation of this principle can be found in the GB mentioned above.
Since it is disclosed in detail in the 2345149 patent, no further description is given here.

In such a conventional chaotic radar, the range resolution is determined by the frequency of the chaotic code. This is because the correlation calculation between the chaotic signal and the signal series obtained from the reflected wave is finely performed. That is, as the frequency of the chaos code increases, the distance resolution also improves. Therefore, in the high resolution chaotic radar, the frequency of the chaotic code is increased and the sampling period in the arithmetic control unit 52 and the conversion period of the A / D converter 57 are set short.

[0011]

As described above, in the above-mentioned conventional high-resolution chaotic radar, for example, the conversion cycle of the A / D converter is shortened, so that high-speed conversion capability is required. However, the current conversion performance of the A / D converter or the like is often not sufficient for the range resolution depending on the application, no matter how high the speed is. For example, when the received signal is directly received by the A / D converter, a high-speed A / D converter of 100 MHz and about 12 bits is required. Such an A / D converter is expensive, and it is expensive to manufacture a radar device. When the chaotic integration process is performed with a digital signal, for example, 100
A multi-stage adder circuit operating at MHz and having 12 bits or more, a shift register of several 100 bits, and the like are required, which increases the scale of hardware.

The present invention has been made in view of the above circumstances, and uses an A / D converter or the like having a normal conversion capability to improve the range resolution and reduce the hardware scale. And a distance measuring method.

[0013]

In order to solve the problems of the above-mentioned conventional example, the present invention generates a pulse signal obtained by binarizing a chaotic signal as a chaotic signal and uses the chaotic signal to generate a carrier wave. Is a radar device for radiating a signal wave obtained by modulating a reflected wave, and measuring the distance to a target object by the correlation between the baseband signal obtained by receiving the reflected wave and the chaotic signal, at a predetermined reference time. The rising edge time of the chaotic signal after that is detected, a plurality of voltage signals obtained by sampling the baseband signal as a voltage signal in a predetermined cycle are held, and the rising edge time and the reference are stored. N (N is an integer equal to or greater than 1) voltage signals after the voltage signal corresponding to the time when a difference from the time has elapsed are taken out, and the N voltage signals taken out by the integrator circuit are taken out. Then, the process of adding to the N voltage signals held as the accumulated results up to the previous time and executing the process of retaining the added result is repeated a plurality of times to obtain N accumulated values, Is converted into N digital values, and the distance to the target is calculated based on the N digital values.

The present invention further comprises a plurality of holding means for holding the plurality of voltage signals obtained by the sampling, and a switch means provided corresponding to the holding means.
The holding means is provided with at least 2N so as to hold at least 2N voltage signals, and holds a voltage signal corresponding to a time point when a difference between the rising edge time and the reference time has elapsed (k is k Holding means provided corresponding to each switch means by turning on the k-th switch means corresponding to the (integer of 1 or more and N or less) -th, from the k-th switch means to the k + N-th switch means in order at a predetermined cycle. Includes a sample-and-hold unit that sequentially outputs N voltage signals that are held at, and adds the N voltage signals that the sample-and-hold unit outputs to the N voltage signals that are held as the accumulation results up to the previous time Then, the process of holding the added result is repeated a plurality of times to obtain N accumulated values, and the N accumulated values are converted into N digital values, respectively. Based on N digital values,
It is intended to calculate the distance to the target object.

Further, the present invention has a plurality of holding means for holding the plurality of voltage signals obtained by the sampling, and a switch means provided corresponding to the holding means.
The holding means is provided with at least N pieces so as to hold at least N voltage signals, and holds a voltage signal corresponding to a time point when a difference between the rising edge time and the reference time has elapsed (k is k An integer greater than or equal to 1 and less than or equal to N) equal to a remainder value obtained by dividing (k + N) by N in order from the kth switch means corresponding to the holding means.
The L-th switch means is turned on at a predetermined cycle,
A result of accumulating the N voltage signals output from the sample and hold unit up to the previous time, including a sample and hold unit that sequentially outputs N voltage signals held by the holding unit provided corresponding to each switch unit. Is added to the N number of voltage signals that are held, and the process of holding the added result is repeated a plurality of times to obtain N accumulated values, and the N accumulated values are respectively The number of digital values is converted, and the distance to the target is calculated based on the N digital values.

Further, according to the present invention, a pulse signal obtained by binarizing a chaotic signal is generated as a chaotic signal, and a signal wave obtained by modulating a carrier wave with the chaotic signal is radiated,
A method of measuring the distance to a target object by the correlation between the baseband signal obtained by receiving the reflected wave and the chaotic signal, and detecting the time of the rising edge of the chaotic signal after a predetermined reference time. , A voltage signal that holds a plurality of voltage signals obtained by sampling the baseband signal as a voltage signal in a predetermined cycle, and corresponds to a time point when a difference between the rising edge time and the reference time has elapsed Subsequent N voltage signals (N is an integer of 1 or more) are taken out, and the N voltage signals taken out by the integrator circuit are added to the N voltage signals held as the accumulation results up to the previous time, respectively. , A process of holding the added result is repeated a plurality of times to obtain N accumulated values, and the N accumulated values are converted into N digital values respectively, and the N accumulated values are converted. Based on the digital value is obtained by the computing the distance to the target.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. A first embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, the radar device according to the present embodiment includes a chaotic signal generation unit 1, a clock generation unit 2, a mixer 3, a transmission antenna 4, a control unit 5, a reception antenna 6, and Sample and hold circuit section 7, analog integrator section 8, A / D
It is configured to include a converter 9 and a distance calculation unit 10.

The chaotic signal generator 1 generates a noise signal having a frequency within the maximum frequency with the reference clock as the maximum frequency from the noise source, binarizes the noise signal and chaotically changes its width. Generates and outputs a pulse signal (chaos signal) that changes. Clock generator 2
Outputs a clock signal having a predetermined frequency. The mixer 3 generates and outputs a transmission signal obtained by modulating a clock signal with a chaotic signal. The transmission antenna 4 radiates this transmission signal.

As shown in FIG. 2, the control unit 5 detects the rising edge of the chaotic signal output from the chaotic signal generating unit 1 based on the clock signal output from the clock generating unit 2 by using a differentiating circuit or the like. The edge detection unit 11, the counter 12 that counts and outputs the number Nx of rising edges detected by the edge detection unit 11, and the time when the rising edge is detected by the edge detection unit 11 (time signal measured by a clock signal) is Nx. And an edge detection time counter 13 that outputs the edge occurrence time tx.

The receiving antenna 6 receives and demodulates the reflected wave radiated from the transmitting antenna 4 and reflected by the target object.
Generates and outputs a baseband signal. The sample hold circuit section 7 samples 2N baseband signals at a predetermined cycle and holds them as 2N voltage signals. In addition, the sample-hold circuit unit 7 sequentially outputs N voltage signals from the time point corresponding to the edge generation time output by the control unit 5 out of the held 2N voltage signals. The specific configuration and operation of the sample hold circuit section 7 will be described later in detail.

The analog integrator 8 includes N integrating circuits,
It has N integration result holders provided corresponding to the respective integration circuits, and N which the sample hold circuit section 7 sequentially outputs.
Among the voltage signals, the kth (1 ≦ k ≦ N) voltage signal is received by the kth integration circuit, and the kth integration result holder provided corresponding to the kth integration circuit is The voltage signal held at that time and the received k-th voltage signal are added (integrated) and held again in the k-th integration result holder. Further, the analog integrator 8 performs integration a predetermined number of times, and then sequentially outputs N voltage signals (accumulated voltage signals) as a result of integration held in each integration result holder. To do. The configuration and operation of the analog integrator 8 will also be described in detail later.

The A / D converter 9 converts the N voltage signals output by the analog integrator 8 into N digital values and outputs the digital values. The distance calculation unit 10 specifies a position where the digital value suddenly changes in the digital signal sequence including these N digital values, obtains the time corresponding to the position as the delay time, and determines the delay time. Is multiplied by the propagation speed of the radio wave (usually the speed of light c) and output as distance information.

Here, the structure and operation of the sample and hold circuit section 7 will be described. Sample and hold circuit section 7
3, includes a buffer 21, a sampling clock generator 22, an input side switch 23, a switch group 24, a hold capacitor group 25, and an output side switch 26.

The buffer 21 receives an input of the baseband signal and temporarily holds it. The sampling clock generator 22 outputs a rectangular wave having a sampling period determined from a desired measurement distance resolution.

The input side switch 23 is turned on at the timing when the rectangular wave rises and supplies the voltage signal held by the buffer 21 to the switch group 24 side. The switch group 24 has 2N switches 24-2 provided corresponding to the number 2N of rectangular waves having a sampling period, which are output at a time twice as long as the attention time determined from the desired maximum measurement distance.
1 to 24-2N, and the switches 24-1 to 24-2N are sequentially turned on when the rectangular wave of the sampling period rises. Also, this switch group 2
When outputting the voltage signal, each of the switches 24-1 to 24-2N of No. 4 switches from the switch 24-m (1 ≦ m ≦ 2N) to the switch 24-m at the position corresponding to the edge occurrence time output by the control unit 5.
Only the number of switches (up to the switch 24- (m + N)) is controlled to be sequentially turned on in synchronization with a predetermined cycle (hereinafter referred to as an output cycle).

The hold capacitor group 25 includes 2N hold capacitors 25-1 to 25-2 provided corresponding to the 2N switches 24-1 to 24-2N, respectively.
Each hold capacitor includes a voltage signal supplied through the input side switch if the input side switch 23 is turned on when the corresponding switch of the switch group 24 is turned on. Hold. If the output side switch 26 is on while the corresponding switch of the switch group 24 is on,
The held voltage signal is output via the output side switch 26.

The output side switch 26 is controlled to be turned on when the voltage signal held by the hold capacitor group 25 is output.

Therefore, the sample hold circuit section 7
Generates a rectangular wave as a sampling clock as shown in FIG. 4 (b) when the baseband signal is changing as shown in FIG. 4 (a). The voltage signal as shown in FIG. 4 (c) is held. Then, when outputting, the voltage signals held in each of the hold capacitors are sequentially output.

The structure and operation of the analog integrator 8 will be described below. As shown in FIG. 5, the analog integrator 8 includes a first buffer 31, a first switch 32, and a second switch 31.
The switch 33, the second buffer 34, and the third switch 3
5 and an integrator circuit group 36, the integrator circuit group 36 corresponding to the number N of voltage signals sampled during the time of interest determined from the desired maximum measured distance, N,
41-N, and an integrating circuit 4 provided corresponding to each of the input switches 41.
2-1, 42-2, ... 42-N and output switches 43-1 and 43- provided corresponding to each of the integrating circuits 42.
2, ... 43-N, and hold capacitors 44-1 and 4-4
4-2, ..., 44-N. In addition, N units including the input switch 41, the integrating circuit 42, the output switch 43, and the hold capacitor 44 will be described below.
They are referred to as integrating units 36-1 to 36-N.

Then, the analog integrator 8 outputs the voltage signal as it is without performing integration (operation without calculation).
And the operation of performing integration. In the non-calculating operation, the voltage signal input from the sample hold circuit unit 7 is temporarily held in the first buffer 31, the first switch 32 and the second switch 33 are turned on, and the third switch 3
Turn off 5. Then, the voltage signal held in the first buffer 31 is passed through the second switch 33 to the second buffer 3
4 is output.

In the operation of executing the integration, the voltage signal input from the sample hold circuit section 7 is applied to the first buffer 31.
Then, the first switch 32 is initially turned off and the third switch 35 is turned on. Here, when the first switch 32 is turned on at the timing when N voltage signals are sequentially input from the sample hold circuit section 7, each of the N voltage signals is output to the integration circuit group 36.

Here, when the kth (1≤k≤N) voltage signal is input, the input switch 41-k of the kth integrating section 36-k in the integrating circuit group 36 is turned on. Control. Then, the k-th voltage signal is introduced into the integrating circuit 42-k and accumulated in the voltage signal held in the integrating circuit 42-k, and the accumulated result is held by the hold capacitor 44-k. Retained.

The analog integrator 8 has a predetermined A / A
At the D conversion timing, receiving an instruction to sequentially turn on the output switch 43 of each of the integrators 36-1 to 36-N, the output switches 43-1 to 43-N are sequentially turned on at a predetermined A / D conversion timing. And Also, the second switch 33 is turned on at this A / D conversion timing. Then, the results of the accumulation (integration) performed by each of the integrators 36-1 to 36-N are sequentially accumulated in the second buffer 34. The voltage signal sequentially accumulated in the second buffer 34 is A
The A / D converter 9 sequentially converts the signals into digital values at the A / D conversion timing.

Next, the operation of the radar device according to this embodiment will be described.

The chaotic signal output from the chaotic signal generating section 1 is mixed with the clock signal output from the clock generating section 2 in the mixer 3 into a transmission signal, which is radiated by the transmitting antenna 4. On the other hand, based on the clock signal output from the clock generation unit 2, the control unit 5 controls the chaos signal generation unit 1
The number of rising edges detected by detecting the rising edges of the chaotic signal output by
And the edge occurrence time tx, which is the detection time of Nx edges. These Nx edge occurrence times tx
Are queued in a queue, for example.

The receiving antenna 6 receives and demodulates the reflected wave radiated from the transmitting antenna 4 and reflected by the target object,
Generates and outputs a baseband signal. This baseband signal is sampled by the sample and hold circuit unit 7 as 2N voltage signals at a predetermined sampling period. Here, the frequency f of the sampling cycle is determined according to the desired distance resolution, and the time T = L / c (here, c is the speed of light) required to measure the desired maximum measurable distance L is used. Can be defined as N = T × f. Therefore, here, the number of voltage signals that is twice the number N of the voltage signals of the baseband signal required to measure the distance to the target object within the desired maximum measurable distance with the desired distance resolution is sampled. become.

When the sampling of the 2N voltage signals is completed, the control section 5 starts the operation as shown in FIG. 6, and first checks whether or not the number Nx of the detected edges is 0 (S1). Here, if the number Nx of edges is 0 (Yes), the control unit 5 turns on the output side switch 26 of the sample hold circuit unit 7 in a predetermined cycle, and 2N switches in this cycle. The switches 24-1 to 24-2N are sequentially turned on (hold result output process; S2). Then switch 2 turned on
Hold capacitor 25-corresponding to 4-k
The kth voltage signal held at k is the output side switch 2
It is sequentially output to the analog integrator 8 via 6.

Further, the control section 5 controls the first switch 32 and the second switch 33 to be turned on so that the analog integrator section 8 operates without calculation (control without calculation;
S3). As a result, the voltage signals sequentially output from the sample and hold circuit unit 7 are directly output to the A / D converter 9. Here, the A / D converter 9 may discard the voltage signal without converting it into a digital signal. Then, the control unit 5 ends the process. This processing S2-S3
As a result, the voltage signal of the hold capacitor 25 of the sample hold circuit unit 7 is cleared.

In process S1, the number N of edges detected
When x is not 0 (No), the controller 5 decrements Nx (S4), extracts one queued edge occurrence time tx, and extracts the edge occurrence time tx.
The voltage signal sampled at the time corresponding to (the Y-th voltage signal here) is specified (S5). This can be determined, for example, by a value Y obtained by converting the value obtained by multiplying the edge occurrence time tx (expressed by the difference from the reference time point, that is, the sampling start time point) by the sampling frequency f into an integer.

Then, the variable Z is set to Y (S6),
It is checked whether or not Z matches Y + N (N is a half of the number of sampled voltage signals and is equal to the number of integrators 36-1 to 36-N) (S7). If not (No), Z is incremented (S8), the output side switch 26 of the sample hold circuit unit 7 is turned on, and the Zth switch 24-Z of the switch group 24 is turned on. . Along with this, the third switch 35 of the analog integrator 8 is turned on (at this time, the first switch 32 is controlled to be turned off), and the C-th (C = (Z = Z -Y)
The input switch 41-C of the integrating section 36-C is turned on (S9). As a result, the C-th integration unit 36-
In the C integration circuit 42-C, the C-th input (Y to C-th) voltage signal is added to the accumulated value of the voltage signals input up to the previous time.

Then, the control section 5 turns on in the process S9, the output side switch 26, the switch 24-Z, and the third switch.
The switch 35 and the input switch 41-C are turned off (S10), and the process returns to the process S7 to continue the process. If Z = Y + N in the process S7, the control unit 5 (Y
If es), the process returns to step S1 to continue the process (A).

By the processing of the control unit 5 shown in FIG. 6,
The accumulated value of the voltage signal based on the baseband signal at the k-th (1 ≦ k ≦ N) from the reference time point is held in each of the N integrating units 36-1 to 36-N. Then, the analog integrator 8 turns on the second switch 33 to output the output switches 43-1 to 4-4 of the integrators 36-1 to 36-N.
3-N are sequentially turned on at A / D conversion timing of a predetermined cycle. As a result, the contents of the hold capacitor 44 (accumulation result) corresponding to the turned-on output switch 43
Are sequentially output to the second buffer 34, and the contents of the hold capacitor 44 are cleared.

The N accumulation results temporarily held in sequence in the second buffer 34 are A / s of a predetermined cycle, respectively.
At the D conversion timing, it is converted into N digital signals by the A / D converter 9, and the distance calculation unit 10 calculates the N digital signals.
In the digital signal sequence containing the digital values,
The position at which the digital value changes abruptly is specified, the time corresponding to the position is obtained as a delay time, and the delay time is multiplied by the propagation speed of the radio wave (usually the speed of light c) and output as distance information.

Here, the A / D conversion timing can be set irrespective of the frequency of the chaotic signal. Therefore, the distance resolution can be improved while using the low speed and inexpensive A / D converter. Moreover, since only an integrator that integrates the voltage signal in an analog manner is used, the circuit scale can be reduced.

Embodiment 2. Next, a radar device according to the second embodiment of the present invention will be described. The radar device according to the present embodiment has the same configuration and operation as those of the radar device according to the first embodiment already described, but the configuration and operation of the sample hold circuit section 7 are slightly different. .

Therefore, the configuration and operation of the sample hold circuit section 7 of the present embodiment will be described below. As shown in FIG. 7, the sample hold circuit section 7 of this embodiment includes a buffer 21 and a sampling clock generating section 2.
2, an input side switch 23, a switch group 24, a hold capacitor group 25, and an output side switch 26. Here, the switch group 24 includes N switches 24-1 to N provided corresponding to the number N of rectangular waves having a sampling period, which are output during a time of interest determined from a desired maximum measurement distance. 24-2N is provided, and the switches 24-1 to 24-N are sequentially turned on when the rectangular wave of the sampling period rises.

The hold capacitor group 25 has N hold capacitors 25-1 to 25-N provided corresponding to the N switches 24-1 to 24-N, respectively.
Each of the hold capacitors includes a voltage signal supplied via the input side switch if the input side switch 23 is turned on when the corresponding switch of the switch group 24 is turned on. Hold. Further, when the output side switch 26 is turned on when the corresponding switch of the switch group 24 is turned on, the held voltage signal is output via the output side switch 26.

Further, in the present embodiment, the control unit 5 sets the remainder value Z obtained by dividing Z by N in the process of turning on any one of the switches 24 of the sample hold circuit unit 7 (process S9 of FIG. 6). ', The switch 24-Z' is turned on. In the process S10, the switch 24-
Turn off Z '. According to this processing, the Y + 1th to Nth switches 24-k (1 ≦ k ≦ N) are sequentially turned on / off, and then the 1st to Yth switches 24-k (1 ≦ k ≦ N). ) Are sequentially turned on / off. According to the configuration of this embodiment, the sample hold circuit section 7
The number of the switch group 24 and the hold capacitor group 25 can be halved, and the hardware scale can be further reduced.

[0049]

According to the present invention, a pulse signal obtained by binarizing a chaotic signal is generated as a chaotic signal, a carrier wave is modulated by the chaotic signal, and a signal wave obtained is radiated and reflected. A radar device for measuring a distance to a target by correlation between a baseband signal obtained by receiving a wave and the chaotic signal, and detecting a rising edge time of the chaotic signal after a predetermined reference time, Holds a plurality of voltage signals obtained by sampling the baseband signal as a voltage signal in a predetermined cycle, and N pieces of voltage signals after the time point corresponding to the time when the difference between the rising edge time and the reference time has elapsed (N is an integer of 1 or more) voltage signals are taken out, and the N voltage signals taken out by the integrator circuit are respectively held as accumulation results up to the previous time.
The number of voltage signals is added, and the process of holding the added result is repeated a plurality of times to obtain N accumulated values, and the N accumulated values are converted into N digital values. However, since the distance to the target object is calculated based on the N digital values, the conversion cycle to the digital value is
A low-speed, inexpensive A / D converter can be used without depending on the cycle (and sampling cycle) of the chaotic signal,
In addition, the hardware scale can be reduced.

Further, according to the present invention, this radar apparatus has a plurality of holding means for holding the plurality of voltage signals obtained by the sampling, and a switch means provided corresponding to the holding means. And the holding means holds at least 2N voltage signals so as to hold at least 2N voltage signals.
N is provided and holds a voltage signal corresponding to a time point when the difference between the rising edge time and the reference time has elapsed
(K is an integer of 1 or more and N or less), the k-th switch means corresponding to the (k) -th N-th switch means are sequentially turned on at a predetermined cycle, and the holding means is provided corresponding to each switch means. The voltage signal held by the means
Each including a sample-and-hold unit that sequentially outputs, and adds the N voltage signals output by the sample-and-hold unit to the N voltage signals that are held as the accumulation results up to the previous time.
The process of holding the added result is repeated a plurality of times to obtain N accumulated values, and the N accumulated values are respectively N accumulated.
Number of digital values and the distance to the target object is calculated based on the N number of digital values, so that the cycle of conversion to digital values depends on the cycle (and sampling cycle) of the chaotic signal. No, slow and cheap A
The / D converter can be used, and the hardware scale can be reduced.

Further, according to the present invention, this radar apparatus has a plurality of holding means for holding the plurality of voltage signals obtained by the sampling, and a switch means provided corresponding to the holding means. However, the holding means is provided with at least N pieces so as to hold at least N voltage signals, and holds the voltage signal corresponding to the time point when the difference between the rising edge time and the reference time has elapsed (k is k From the k-th switch means corresponding to the 1st to N-th holding means) to the L-th switch means, which is equal to the remainder value obtained by dividing (k + N) by N, are turned on in a predetermined cycle. A N-voltage signal output from the sample-hold unit is included, which includes a sample-hold unit that sequentially outputs N voltage signals held by a holding unit provided corresponding to each switch unit. Is added as the accumulated result up to the previous time to the N number of voltage signals, and the process of retaining the added result is repeated a plurality of times to obtain N accumulated values to obtain N accumulated values. Since the accumulated values are converted into N digital values and the distance to the target is calculated based on the N digital values, the hardware scale can be further reduced.

Further, according to the present invention, the chaotic signal is
Generate the pulse signal obtained by binarization as a chaotic signal,
A method of radiating a signal wave obtained by modulating a carrier wave by the chaotic signal, and measuring a distance to a target by correlation between the chaotic signal and the baseband signal obtained by receiving the reflected wave thereof, Detects the rising edge time of the chaotic signal after a predetermined reference time, holds multiple voltage signals obtained by sampling the baseband signal as a voltage signal in a predetermined cycle, and then sets the rising edge time and the reference N (N is an integer equal to or greater than 1) voltage signals after the voltage signal corresponding to the time when only the difference from the time has elapsed are taken out, and the N voltage signals taken out by the integration circuit are accumulated up to the previous time. Are added to the N voltage signals that are held as, and the process of holding the added result is repeated a plurality of times to obtain N accumulated values, and the N accumulated values are calculated. It converted respectively into N digital values,
Since the distance to the target object is calculated based on the N digital values, a low-speed and inexpensive A / D converter can be used, and it can be realized with small-scale hardware.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a radar device according to a first embodiment of the present invention.

FIG. 2 is a configuration block diagram of a control unit.

FIG. 3 is a configuration block diagram of a sample hold circuit section of the radar device according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram illustrating an operation of a sample hold circuit.

FIG. 5 is a configuration block diagram of an analog integrator of the radar device according to the first embodiment of the present invention.

FIG. 6 is a flowchart showing the operation of the radar device according to the first embodiment of the invention.

FIG. 7 is a configuration block diagram of a sample hold circuit section of a radar device according to a second embodiment of the present invention.

FIG. 8 is a configuration block diagram of a conventional radar device.

[Explanation of symbols]

1,51 Chaotic signal generator, 2,53 Clock generator, 3,54 Mixer, 4,55 Transmit antenna, 5
Control unit, 6,56 reception antenna, 7 sample hold circuit unit, 8 analog integration unit, 9,47 A / D converter, 10 distance calculation unit, 11 edge detection unit, 12 counter, 13 edge detection time counter, 21, 31,
34 buffer, 23 input side switch, 24 switch group, 25 hold capacitor group, 26 output side switch, 32 first switch, 33 second switch, 35
Third switch, 36 integration circuit group, 41 input switch, 42 integration circuit, 43 output switch, 44 hold capacitor, 52 arithmetic control unit, 58 chaos processing unit.

Claims (4)

[Claims] 1. A pulse signal obtained by binarizing a chaotic signal is generated as a chaotic signal, a carrier wave is modulated by the chaotic signal to emit a signal wave, and a reflected wave thereof is received to obtain. A radar device for measuring the distance to a target object by correlating the baseband signal and the chaotic signal, detecting the rising edge time of the chaotic signal after a predetermined reference time, and converting the baseband signal to a voltage. As a signal, a plurality of voltage signals obtained by sampling in a predetermined cycle are held, and N (N is a voltage signal after the voltage signal corresponding to a time point when a difference between the rising edge time and the reference time has elapsed. (1 or more integer) voltage signal is taken out, and the N voltage signals taken out by the integrator circuit are respectively added to the N voltage signals held as accumulation results up to the previous time. , The process of holding the added result is repeated a plurality of times to obtain N accumulated values, and the N accumulated values are converted into N digital values, respectively, and the N digital values are converted. A radar device which calculates a distance to a target object based on a value. 2. A plurality of holding means for holding a plurality of voltage signals obtained by the sampling, and a switch means provided corresponding to the holding means, the holding means being at least 2N in number. At least 2N number of voltage signals are provided to hold the voltage signal, and the k-th (k is an integer not less than 1 and not more than N) th voltage signal corresponding to the time point when the difference between the rising edge time and the reference time has elapsed The k-th switch means corresponding to the holding means to the k + N-th switch means are sequentially turned on at a predetermined cycle, and N voltage signals are held in the holding means provided corresponding to each switch means. , Including the sample-and-hold unit that outputs sequentially, adds the N voltage signals output by the sample-and-hold unit to the N voltage signals that are held as the accumulation results up to the previous time , The process of holding the added result is repeated a plurality of times to obtain N accumulated values, and the N accumulated values are converted into N digital values, respectively, and the N digital values are converted. The radar device according to claim 1, wherein the distance to the target is calculated based on the value. 3. A plurality of holding means for holding a plurality of voltage signals obtained by the sampling, and a switch means provided corresponding to the holding means, wherein the holding means has at least N pieces. At least N number of voltage signals are provided to hold the voltage signal, and the k-th (k is an integer of 1 or more and N or less) th voltage signal corresponding to a time point when a difference between the rising edge time and the reference time has elapsed From the k-th switch means corresponding to the holding means to the L-th switch means, which is equal to the remainder value obtained by dividing (k + N) by N in order, are turned on in a predetermined cycle to correspond to each switch means. A sample hold unit that sequentially outputs N voltage signals held by the holding means provided is provided, and the N voltage signals output by the sample hold unit are used as accumulation results up to the previous time. The process of adding to the N voltage signals that it has and holding the result of the addition is repeated a plurality of times to obtain N accumulated values, and each of the N accumulated values is N units. 2. The radar device according to claim 1, wherein the radar device calculates the distance to the target object based on the N digital values. 4. A pulse signal obtained by binarizing a chaotic signal is generated as a chaotic signal, a carrier wave is modulated by the chaotic signal, a signal wave obtained is radiated, and a reflected wave thereof is received and obtained. A method of measuring the distance to a target object by correlating the baseband signal and the chaotic signal, detecting the rising edge time of the chaotic signal after a predetermined reference time, and converting the baseband signal to a voltage signal. As a result, a plurality of voltage signals obtained by sampling in a predetermined cycle are held, and N (N is 1) after the voltage signal corresponding to a time point when a difference between the rising edge time and the reference time has elapsed. (The above integer) voltage signals are taken out, and the N voltage signals taken out by the integrator circuit are respectively added to the N voltage signals held as the accumulation results up to the previous time, The process of holding the addition result is repeated a plurality of times to obtain N accumulated values, convert the N accumulated values into N digital values, respectively, and convert the N accumulated values into the N digital values. A distance measuring method characterized in that the distance to the target object is calculated based on the distance.