JP2003173153A - Signal line wiring method and thin film transistor array board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display panel array board which is suitable for downsizing equipment, especially portable equipment, and enlarging screen and which gives a high degree of freedom to portable equipment design. <P>SOLUTION: In a thin film transistor array board where a plurality of thin film transistors are arranged in a matrix form on the surface of a non- conductive substrate, among a group of source signal lines and a group of gate signal lines, one of the groups of signal lines are almost linear and arranged in parallel to each other, and the other group of signal lines constitute an almost cross-shape including almost linear main line parts arranged in parallel to the signal lines and almost linear branch line parts orthogonal to the main line parts and connected with the thin film transistors, and a plurality of them are arranged in a lattice form. In an area where a pair of almost cross-shaped signal lines are crossing, one of them is partly arranged on the other layer with an insulating layer interposed between them and via a hole arranged in the insulating layer so that they are electrically insulated from each other and cross each other three-dimensionally. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of elements arranged in a matrix on a substrate, which is represented by a thin film transistor array substrate for an active matrix type display panel for controlling each pixel by using a thin film transistor. , Arrangement of a pair of signal lines for supplying signals from outside the system.

[0002]

2. Description of the Related Art In recent years, portable terminal devices such as mobile phones and PDAs (personal digital assistants) have been remarkably spread. Along with this, developments have been actively made to make these devices more compact or lighter. Liquid crystal display panels, which have advantages of low power consumption and light weight, are widely used as display panels for these devices. Also,
A device using an electroluminescence (EL) display panel having a wider viewing angle instead of the liquid crystal display panel has been developed. In a liquid crystal display panel, a voltage is applied to a liquid crystal layer sandwiched between a pair of substrates facing each other to change the orientation of a liquid crystal material in the liquid crystal layer and adjust the amount of light passing through the liquid crystal layer. Form images, etc. The EL display panel forms an image or the like by applying voltage or current to the light emitting layer to emit light.

In these display panels, an active matrix type display panel in which each pixel is independently driven by using a switching element such as a thin film transistor (TFT) can display a more vivid image,
Since it is possible to display at higher speed, it has been widely used in place of the simple matrix type display panel. Conventionally, since a TFT, which is a MOS type transistor, can be formed on an insulating substrate, it is used for controlling each pixel of a display device such as an active matrix type liquid crystal display device and an electroluminescence (EL) display device. Widely used as a switching element.

In these active matrix type display devices, a large number of TFTs are arranged in a matrix on an insulating substrate such as glass. As an example, FIG. 16 shows an array substrate of an active matrix type liquid crystal display panel.
Shown in. As shown in FIG. 16A, a plurality of gate signal lines 3 are arranged on the substrate 2 in parallel with each other, and a plurality of source signal lines 4 are orthogonal to them with an insulating layer therebetween. Are arranged. In a region surrounded by a pair of adjacent gate signal lines 3 and a pair of adjacent source signal lines 4, that is, a pixel region, as shown in FIG. 16B, a transparent material such as indium tin oxide (ITO) is used. A pixel electrode 5 made of a conductive material and a thin film transistor 6 as a switching element thereof are arranged.

The gate signal line 3 and the source signal line 4 are
The connection terminals 13 and 14 respectively arranged on the peripheral portion of the substrate 2 are formed by COG (chip on glass) or T on the array substrate 1 as shown in FIG.
L mounted by AB (tape automated bonding)
A drive circuit 80 including elements such as SI, or FIG.
As shown in (b), it is connected to a drive circuit (not shown) arranged on another substrate (not shown) via the flexible substrate 90. In this way, since the gate signal line 3 and the source signal line 4 are arranged to intersect with each other, the connection terminal 13 of the gate signal line 3 and the connection terminal 1 of the source signal line 4 are arranged.
4 are provided on the peripheral portions of a pair of end sides that are adjacent to each other with the corner portion of the substrate 2 separated. That is, these were arranged in the asymmetrical regions on the substrate.

Similarly, in the EL display panel of the active matrix type, a plurality of source signal lines and gate signal lines are arranged orthogonal to each other on the same substrate. Therefore, since the source signal line and the gate signal line are arranged orthogonally to each other, the connection portion of the source signal line with the driving circuit and the like and the connection portion of the gate signal line with the driving circuit and the like are provided on the substrates adjacent to each other. It was provided on each side. The drive circuits that drive the source signal lines and the gate signal lines are connected to these signal lines at the edges of the substrate.

Since the space for mounting the elements on the pair of adjacent edges of the substrate is a so-called non-display area, the provision of the space restricts downsizing of the device or upsizing of its display panel. Further, it regulates the degree of freedom in designing devices, especially portable devices that are highly demanded to be small and have a large screen. However, the conventional arrangement of signal lines is inevitable.

[0008]

SUMMARY OF THE INVENTION The present invention is intended to solve the above-mentioned problems, and enables the arrangement of signal lines with a high degree of freedom in equipment design, and makes equipment, especially portable equipment, smaller and has a larger screen. It is an object of the present invention to provide an array substrate for a display panel, which is suitable for, and has a high degree of freedom in designing a mobile device.

[0009]

According to the present invention, in a layout pattern of a pair of signal lines for supplying a signal from outside the system to each of a plurality of elements arranged in a matrix on a substrate, The pair of connection terminals for connecting to an external circuit are replaced with two sides which are inevitably defined in the past and which are orthogonal to each other with a corner portion of the panel therebetween, and a pair of opposite edges or the same edge of the substrate. Place on the side.

For example, an insulating substrate, a plurality of thin film transistors arranged in a matrix on the surface of the substrate, each having a semiconductor layer, a source electrode, a drain electrode and a gate electrode, and respectively connected to the drain electrode of the thin film transistor. The pixel electrode and the surface of the substrate,
A plurality of source signal lines for supplying source signals to the source electrodes of the thin film transistors in predetermined columns, and a gate for supplying a gate signal to the gate electrodes of the thin film transistors in predetermined rows arranged on the surface of the substrate. In a thin film transistor array substrate including a signal line and an insulating layer arranged between a layer on which a source signal line is arranged and a layer on which a gate signal line is arranged, the thin film transistor array substrate is provided on two opposite sides or the same side of the substrate. Connection terminals for these signal lines are arranged.

One of the signal wirings is substantially linear and is arranged in parallel with each other, and the other signal wiring is arranged substantially parallel to the substantially linear trunk portion and is orthogonal to the trunk portion and connected to the thin film transistor. The shape is a substantially cross shape including substantially linear branch lines, and a plurality of them are arranged in a grid pattern. A plurality of thin film transistors as switching elements are arranged in a plurality of rows (or columns) on the substrate, and are also arranged in a direction at right angles thereto, as in a so-called diagonal arrangement. In addition, like a so-called delta arrangement, a plurality of rows (or columns) are arranged on the substrate, and a pair of thin film transistors adjacent to each other on the same row (or column) and adjacent rows (or adjacent rows) located closest to them are arranged. The thin film transistors on the (rows) are arranged at the respective vertices of the triangle. The signal line is arranged between the thin film transistors. For example, in the diagonal array, the one of the signal wirings and the trunk portion of the other signal line are linear ones,
In the delta arrangement, the signal wiring and the main line portion are linear or have a linear portion having a bent portion.

The present invention is applied regardless of the layout of thin film transistors, and in a region where a pair of substantially cross-shaped signal lines intersect, they are electrically insulated from each other and three-dimensionally intersect each other. Are partially disposed in the other layers sandwiching the insulating layer through the holes provided in the insulating layer. When the signal line elements arranged on the other layers are formed simultaneously with, for example, the same material as the substantially linear signal line, no new process is added as compared with the conventional signal line forming process.

Here, the substantially linear signal lines arranged in parallel with each other and the main line portion of the other signal line are overlapped with each other except for the end portions which connect to the signal line elements of the other layer. The area occupied by these in the substrate can be reduced, and the aperture ratio of the display panel can be increased.
When arranging the end portions of these signal lines for connecting to a signal circuit or the like on the same end side, it is preferable to arrange these on separate columns.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described in detail below with reference to the drawings, taking a thin film transistor array substrate for an active matrix type display panel as an example.

<< Embodiment 1 >> An array substrate of this embodiment is shown in FIG.
Shown in. As shown in FIG. 1, a substantially linear source signal line 4 and a substantially cross shape are formed on an insulating substrate 2 made of glass or the like, that is, a gate signal line having a trunk line portion and a branch line portion in the present invention. Three are arranged. The gate signal line 3 and the source signal line 4 are connected to the gate signal line connection terminal 13 and the source signal line connection terminal 14 arranged on one end side of the substrate 2, respectively. In the gate signal line 3, one line segment that constitutes the main line portion is arranged in parallel with the source signal line 4, and the cross-shaped element 3a and the cross-shaped element 3 that include a part of the main line portion and the branch line portion.
a line segment element 3b which is arranged in the same layer as a in parallel with the source signal line 4 and constitutes a part of the main line portion, and a line segment element 3b which is arranged in a different layer separated from them by an insulating layer and constitutes a part of the main line portion Bridging element 3c.

As shown in FIG. 2A, a pixel electrode 5 and a thin film transistor (TFT) 6 as a switching element for the pixel electrode 5 are arranged in each region partitioned by the gate signal line 3 and the source signal line 4 in a grid pattern. Has been done. The TFT 6 shown here is a so-called top gate type, and
As shown in (b), the semiconductor layer 60 of the TFT 6 is arranged on the undercoat layer 9 of the substrate 2, and the gate electrode 61 is arranged on the insulating layer 10a. The cross-shaped elements 3a are the semiconductor layers 60 of the TFTs 6 arranged in the same row.
Is integrally formed with the gate electrode 61 covering the channel region 60b.

The cross-shaped element 3a and the line segment element 3b of the gate signal line 3 are disconnected at a position intersecting with the branch line portion of the cross-shaped element 3a of another gate signal line 3 as shown in FIG. 2 (c). The other cross-shaped element 3a and the line segment element 3b or the pair of line segment elements 3b facing each other with the branch line portion of the cross-shaped element 3a interposed therebetween are the bridging elements 3c arranged with the insulating layer 10b interposed therebetween. Are electrically connected through the contact hole 11a. Therefore, the gate signal lines 3 are electrically isolated from each other in the regions intersecting with each other.

The source signal line 4 is arranged in the same layer as the bridging element 3c, that is, in a layer above the cross-shaped element 3a and the line segment element 3b with the insulating layer 10b interposed therebetween. The source signal line 4 is integrally formed with a source electrode 62 that connects the source regions 60a of the TFTs 6 in the same column to the source signal lines 4 through the contact holes 11b, and the drain regions 60c of the TFTs 6 are formed in the same layer. The pixel electrode 5
A drain electrode 63 is formed to connect with the.

In the array substrate of this embodiment, since the gate signal line connecting terminals 13 and the source signal line connecting terminals 14 are arranged on the same side of the substrate 2, these are connected near the other three sides. It is not necessary to provide a region in which terminals are provided, that is, a non-display region that does not directly contribute to display. Therefore, the degree of freedom in designing the device is significantly improved. Further, the drive circuit for the gate signal line 3 and the drive circuit for the source signal line 4 can be formed in the same element. That is, the device can be made into one chip.

An example of the method of manufacturing the array substrate will be described below. First, an undercoat layer 9 made of SiO _x and having a thickness of 400 nm is formed on the insulating substrate 2.
After further forming an amorphous silicon film with a thickness of 60 nm thereon, this substrate is heat-treated for 2 hours in a vacuum at a temperature of 450 ° C. or in an atmosphere replaced with an inert gas, and further amorphous in vacuum. The silicon film is irradiated with an excimer laser to crystallize it. After that, the polycrystalline silicon film formed on the substrate 2 with the undercoat film 9 interposed therebetween is processed into individual pieces, and as shown in (a) and (b) of FIG.
A semiconductor layer 60 for TFTs arranged in an array is formed.

Next, an insulating layer 10a made of SiO _x and having a thickness of 90 nm is formed on the surface of the substrate 2 so as to cover them, and a conductive film made of an aluminum alloy is further formed on the insulating layer 10a, which is shown in FIG. As shown, it is processed into a predetermined pattern. As a result, the cross-shaped elements 3a and the line segment elements 3b as the constituent elements of the gate signal line 3 are formed in a substantially lattice shape, and at the same time, the gate signal line connection terminal 13 and the gate electrode 61 connected to them are respectively formed.

Here, as shown in FIG. 4A, the cross-shaped element 3a has a pair of ends on each of the semiconductor layers 60 whose branch lines are arranged in the row direction (horizontal direction in the drawing). Integrated with the gate electrode 61 arranged so as to cover except the portion,
They are formed parallel to each other. The number of formed cross-shaped elements 3a, that is, the number of branch lines thereof is equal to the number of rows of the semiconductor layers 60 arranged in an array. These cross-shaped elements 3a are arranged in a region where the branch line portion thereof is arranged, that is, a region which becomes a display region when assembled in a display panel. In the column direction (vertical direction in the figure), as shown in FIG. 4C, the gate signal line connection terminals 13, the trunk line portion of the trunk line element 3a, and the line segment element 3b arranged near one end side of the substrate 2.
Are arranged on the same row. That is, the trunk line element of the gate signal line 3 is formed intermittently at a position intersecting with the trunk line element 3a of the other gate signal line 3.

After the respective elements of the gate signal line 3 and the gate electrode 61 are formed as described above, the gate electrode 6 is formed.
Using the mask 1 as a mask, an n-type impurity such as As is implanted into the semiconductor layer 60. As a result, impurities are sucked into the pair of end portions of the semiconductor layer 60 exposed from the gate electrode 61.
As shown in (b), a channel region 60b containing no impurities, and a source region 60a and a drain region 60c sandwiching the channel region 60b are formed in the semiconductor layer 60.

After the impurity implantation, an insulating layer 10b in which a film made of SiO _x and a film made of SiN _x are laminated is formed on the entire surface of the substrate 2 so as to cover them, and further, as shown in FIG. The insulating layer 10b in the region directly above the pair of elements (that is, the end of the main line portion and the end of the line segment element 3b) facing each other with the branch line portion 3a interposed therebetween, and the source region 60.
a and the drain region 60c, contact holes 11a and
1b is formed. After that, a conductive film in which a titanium film and an aluminum film are stacked is formed on the entire surface of the substrate 2 so as to cover them, and the conductive film is processed into a predetermined pattern, and gate signal connection is performed as shown in FIG. A source signal connection terminal 14 is provided near one end of the substrate 2 on which the terminal 13 is arranged.
Is connected to the source signal line 4 in the arrangement direction of the trunk portion of the cross-shaped element 3a of the gate signal line 3, and the source region 60a of the semiconductor layer 60 and the source signal line 4 arranged in the same direction are connected to the contact hole 11a. The source electrode 62 connected through is formed integrally. At this time, the drain region 6 of the semiconductor layer 60 is further inserted through the contact hole 11b.
The drain electrode 63 connected to 0c and the bridging element 3c connecting the constituent elements of the pair of gate signal lines 3 facing each other with the branch portion of the cross-shaped element 3a interposed therebetween are formed at the same time. Due to the formation of the bridging element 3c, the constituent elements of the gate signal line 3 are electrically connected.

An insulating layer 10c made of, for example, SiO _x is formed on the entire surface of the substrate 2 so as to cover them, and a contact hole 11c is formed immediately above the drain electrode 63 of the insulating layer 10c, and then these are covered. A transparent conductive layer made of ITO or the like is formed on the entire surface of the substrate 2. The transparent conductive layer is processed into a predetermined pattern to form the pixel electrode 5. It is also possible to first form the bridging element together with the other signal line and then connect the bridging element to form the cross-shaped element and the line segment element. For example, using a substantially cross-shaped source signal line and a substantially linear gate signal line, as shown in FIG. 7, the bridging element 4c of the source signal line is replaced by the cross-shaped element 4a.
It is also possible to arrange it in a layer lower than the line segment element 4b. Of course, which of the source signal line and the gate signal line has a substantially cross shape can be arbitrarily selected.

An array substrate for a liquid crystal display panel is obtained by forming an alignment film made of, for example, polyimide on the surface of the substrate on which the pixel electrodes are formed by a predetermined method.

FIG. 8 shows an example of a transmissive active matrix type liquid crystal display panel using the array substrate obtained as described above. Array substrate 1 having alignment film 15 on the surface
Are arranged so as to face each other with the counter substrate 20 similarly provided with the alignment film 15. Liquid crystal layer 24 between both substrates
Are arranged. A counter electrode 21 made of a transparent conductive material is arranged on the surface of the counter substrate 20. T on the array substrate 1
When the FT 6 is turned on, an electric field is formed between the pixel electrode 5 and the counter electrode 21, and the orientation of liquid crystal molecules in the liquid layer 24 changes. Due to this change in the orientation of the liquid crystal molecules, the turning angle of the polarized light that is emitted from the backlight 27 and transmitted through the polarizing plate 25 is adjusted, and the intensity of the light transmitted through the light analyzing plate 26 is adjusted.

In a so-called semi-transmissive liquid crystal display panel, the drain electrode may be used as the reflective electrode 5a as shown in FIG. 9, for example. In addition, the reflective electrode 5
Protrusions 50 for scattering incident light may be provided on the surface of a.

When the gate signal line connection terminals 13 and the source signal line connection terminals 14 are arranged so that the distances from the edges of the substrate 2 are different from each other as shown in FIG. As shown in (c), the connection with the drive circuit or the connection with the flexible substrate 90 on which the drive circuit is mounted becomes easy. Also, when the driving element is directly arranged on the substrate, the connection with the same becomes easy. The two types of connection terminals 13 and 14 are arranged on the same side of the substrate as shown in the above-described embodiment, and
They may be arranged on opposite sides as shown in FIG.

<< Embodiment 2 >> FIG. 12 shows a main part of an array substrate of the present embodiment. In this array substrate 1, the bridging element 3c
The main line portion of the cross-shaped element 3a and the line segment element 3b are arranged so as to be superposed on the source signal line 4 with an insulating layer (not shown) interposed therebetween, except for the end portion for connecting with. In the cross-shaped element 3a and the line segment element 3b arranged in the lower layer, the end portion connected to the bridging element 3c in order to three-dimensionally intersect the branch line portion of the other gate signal line 3 is bent and the source signal line is bent. It is exposed from just below 4. In this array substrate 1, by overlapping the gate signal lines 3 and the source signal lines 4, it is possible to reduce the area occupied by the source signal lines and the like that do not directly contribute to the display. The aperture ratio of the pixel can be increased. That is, it is possible to display with higher brightness than that of the first embodiment.

Here, as shown in (b), in the vicinity of the intersection of the main line portion and the branch line portion of the cross-shaped element 3a, the same shape as the end portion of the main line portion or the bent end portion of the line segment element 3b is formed. By providing the dummy pattern 3d, it is possible to reduce the non-uniformity of the display quality that occurs between the pixels in the vicinity of the cross-shaped element 3a and the other pixels when used as a display panel. That is, it is possible to suppress the influence of light shielding by the bent wiring end portion and the influence of such wiring end portion on the electric field formed in the pixel electrode 5.

Example 3 For example, VGA (640 ×
In the case of 480 dots, the number of source signal lines is 1440 (= 480 × 3), while the number of gate signal lines is 640 which is less than half. Therefore, when the number of source signal lines and the number of gate signal lines are different as described above, a plurality of signal lines may be arranged between the pixel electrodes 5 as shown in FIG. Here, as described above, in order to keep the display quality of the pixels uniform, it is desired that the pixel configurations and the intervals between the pixel electrodes are equal. Therefore, in the case where the number of source signal lines (the number of pixel columns) is larger than the number of gate signal lines (the number of pixel rows), such as the VGA described above, FIG.
As shown in (b), the number of main line portions of the source signal line 4 arranged between the pixels is made constant, and the redundant main line portions are further connected to branch line portions connected to other main line portions. Connect multiple trunk lines to the same branch line, that is, TF from multiple terminals
By enabling output to T, even if there is a pattern defect such as disconnection in one of the paths of the source signal to the pixel column in the manufacturing process, the signal is normally supplied to the pixel column from the other path. Therefore, the pixels in that column can display excellently. In addition, it also contributes to lowering the resistance of the wiring. The surplus signal line is preferably a dummy pattern for suppressing a difference in display quality between pixels. The dummy signal line can be used as a repair wiring depending on the case.

Example 4 In this example, another example of an array substrate for a transflective liquid crystal display panel will be described.
The array substrate of this embodiment is shown in FIG. The cross-shaped element 4a and the line segment element 4b of the source signal wiring 4 are connected to the reflective electrode 5
It is formed in the same layer as a using the same material as that.
Part of each of these is arranged so as to overlap the reflective electrode 5a and the transmissive electrode 5b. Although the element arranged immediately below the transparent electrode 5b blocks the transmission of light in the transmissive display mode, the aperture ratio equivalent to that in the case where it is arranged between the pixel electrodes can be obtained. On the other hand, in the reflective display mode, since the wiring element arranged directly under the transparent electrode 5b functions as a reflector, it is possible to display with higher brightness.

Similarly, in a display panel such as an EL display panel or a reflective liquid crystal display panel which is connected to the TFT and has a display electrode that is not transparent such as a reflective electrode. A signal line may be arranged directly below.

Example 5 In this example, an example of an organic EL panel will be described. In the organic EL panel,
Basically, one switching element is arranged in each pixel similarly to the array substrate for the liquid crystal display panel shown in the above-mentioned embodiment. EL panels have also been proposed.
For example, as shown in FIG.
6d is provided, terminals A and B are connected to gate signal lines 30a and 30b, respectively, and terminals C and D are connected to source signal lines 40a and 40b, respectively. These signal lines are three-dimensionally crossed between the pixels as shown in (b).

[0036]

According to the present invention, it becomes possible to dispose the drive circuit or the connection terminal to the drive circuit on the same side or the opposite side on the substrate, and it becomes possible to design a device with a high degree of freedom. Therefore, it is possible to provide a small-sized and large-screen mobile device.

[Brief description of drawings]

FIG. 1 is a plan view showing a main part of an array substrate according to an embodiment of the present invention.

2B is an enlarged plan view showing a pixel region of the same substrate, FIG. 2B is a vertical cross-sectional view of a thin film transistor formed on the same substrate and its periphery, and FIG. 2C is a gate signal. It is a longitudinal cross-sectional view of a three-dimensional intersection of lines.

FIG. 3 is a diagram showing a step in the manufacturing process of the array substrate, in which (a) is a plan view of a main portion, and (b) is a vertical cross-sectional view of a semiconductor layer formed on the substrate and the periphery thereof. It is a figure.

FIG. 4 is a view showing still another stage of the manufacturing process of the array substrate, (a) is a plan view of a main part, and (b) is a semiconductor layer formed on the same substrate and its surroundings; It is a longitudinal cross-sectional view, (c) is a vertical cross-sectional view of a region to form a three-dimensional intersection of the gate signal line.

5A and 5B are diagrams showing still another stage of the manufacturing process of the array substrate, FIG. 5A is a plan view of a main part, and FIG. 5B is a diagram showing a semiconductor layer formed on the substrate and its periphery. It is a longitudinal cross-sectional view, (c) is a vertical cross-sectional view of a region to form a three-dimensional intersection of the gate signal line.

6A and 6B are views showing still another stage of the manufacturing process of the array substrate, FIG. 6A is a plan view of a main part, and FIG. 6B is a vertical cross-sectional view of a thin film transistor formed on the substrate and its periphery. FIG. 3C is a plan view, and FIG. 3C is a vertical cross-sectional view of a three-dimensional intersection of gate signal lines and the surroundings thereof.

FIG. 7 is a vertical cross-sectional view showing a signal line grade intersection and its surroundings of an array substrate according to another embodiment of the present invention.

FIG. 8 is a vertical cross-sectional view of a main part showing a configuration of a liquid crystal display panel according to an embodiment of the present invention.

FIG. 9 is a view showing a main part of an array substrate according to still another embodiment of the present invention, (a) is a plan view of the main part,
(B) is a longitudinal cross-sectional view of a main part.

10A and 10B are diagrams showing signal line connection terminals arranged on an array substrate according to still another embodiment of the present invention, FIG. 10A is a plan view of a main part of the array substrate, and FIG. It is a longitudinal cross-sectional view of a connection portion between a signal line connection terminal and a flexible substrate after being assembled to a liquid crystal display panel, and (c) is a plan view of the display panel to which the flexible substrate is connected.

FIG. 11 is a plan view showing an array substrate of still another embodiment of the present invention.

FIG. 12 is a plan view of a main part showing a main part of an array substrate according to still another embodiment of the present invention, in which (a) is a plan view of a region including a connection terminal and a pixel region, and (b). FIG. 4 is an enlarged plan view of a pixel area.

13A and 13B are diagrams showing an array substrate of still another embodiment of the present invention, wherein FIG. 13A is a plan view and FIG. 13B is a model diagram showing a circuit of a signal line.

14A and 14B are diagrams showing an array substrate of still another embodiment of the present invention, in which FIG. 14A is a plan view of a region including a connection terminal and a pixel region, and FIG. Is.

15A is a circuit diagram showing a pixel configuration of an array substrate for an electroluminescent display panel according to an embodiment of the present invention, and FIG. 15B is a circuit showing an arrangement of signal lines on the substrate. It is a figure.

16A and 16B are diagrams showing the arrangement of signal lines in a conventional array substrate, FIG. 16A is a schematic plan view of the same substrate, and FIG. 16B is a plan view of a pixel region of the same substrate. .

FIG. 17 is a schematic plan view showing a form of connection between an array substrate and a drive circuit in a conventional display panel,
(A) shows an array substrate in which a drive circuit is directly mounted on the surface, and (b) shows an array substrate connected to the drive circuit via a flexible substrate.

[Explanation of symbols]

1 Array substrate 2 substrates 3, 30a, 30b Gate signal line 3a, 4a Cruciform element 3b, 4b Line segment element 3c, 4c bridging element 3d dummy pattern 4, 40a, 40b Source signal line 5 pixel electrodes 5a reflective electrode 5b transparent electrode 6, 6a, 6b, 6c, 6d thin film transistor 9 Undercoat layer 10a, 10b, 10c insulating layer 11a, 11b, 11c Contact hole 13 Gate signal line connection terminal 14 Source signal line connection terminal 15 Alignment film 20 Counter substrate 21 Counter electrode 22 Color filter 23 Black Matrix 24 Liquid crystal layer 25 Polarizer 26 Analyzer 27 Backlight 50 protrusions 60 semiconductor layers 60a source area 60b channel region 60c drain region 61 Gate electrode 62 source electrode 63 drain electrode 70 Organic electroluminescence device 80 drive circuit 90 Flexible board 100 LCD display panel

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) // G02F 1/1368 H01L 21/88 F term (reference) 2H092 GA50 GA51 JA25 JA29 JA36 JA38 JA42 JA44 JA46 KA04 KA12 KA18 KA22 MA05 MA08 MA13 MA17 MA30 MA35 MA37 PA06 PA13 5C094 AA14 AA15 BA03 BA27 BA43 CA19 EA04 EA07 5F033 GG04 HH08 HH18 JJ08 JJ18 KK04 KK08 HG05 GG05 JJ05 JJ05 JJ26 GG06 GG26A02 BB06 V13 V6 HL04 HL11 HM19 NN03 NN23 NN24 PP01 PP03 PP10 PP13 PP29 QQ11

Claims (8)

[Claims] 1. A method of arranging a pair of signal lines for supplying a signal from outside the system to each of a plurality of elements arranged in a matrix on a substrate, the signal line comprising: A wiring method in which a pair of terminal portions for connecting to an external circuit are arranged on a pair of opposite edges or the same edge of the substrate. 2. An insulating substrate, a plurality of thin film transistors arranged in a matrix on the surface of the substrate, each having a semiconductor layer, a source electrode, a drain electrode, and a gate electrode, and the drain electrode of the thin film transistor, respectively. Pixel electrodes connected to each other, a plurality of source signal lines arranged on the surface of the substrate for supplying source signals to the source electrodes of the thin film transistors in predetermined columns, and arranged on the surface of the substrate. A plurality of gate signal lines for supplying a gate signal to the gate electrodes of the thin film transistors in predetermined rows, and between a layer on which the source signal line is arranged and a layer on which the gate signal line is arranged. An insulating layer is provided, and one of the source signal line and the gate signal line is substantially linear and parallel to each other. And the other signal wiring includes a substantially linear trunk line portion arranged in parallel with the one signal wiring line, and a substantially linear branch line portion orthogonal to the trunk line portion and connected to the thin film transistor. A plurality of cross-shaped insulating layers are arranged through a hole provided in the insulating layer so that they are three-dimensionally crossed by being electrically insulated from each other in a region where a pair of them are arranged in a lattice. A thin film transistor array substrate arranged on another layer sandwiched therebetween. 3. The thin film transistor array substrate according to claim 2, wherein the elements arranged on the other layer of the other signal line are formed of the same material as the one signal line in the same layer as the one signal line. . 4. The one signal wiring and the main line portion of the other signal line are arranged so as to be overlapped with each other except for respective end portions for connecting with a signal circuit and the intersecting regions. 3. The thin film transistor array substrate described in 3. 5. The thin film transistor array substrate according to claim 2, wherein the one signal wiring is the source signal line and the other signal wiring is the gate signal line. 6. The thin film transistor array substrate according to claim 2, wherein both end portions of the source signal line and the end portion of the source signal line for connecting to a signal circuit are arranged on the same edge side of the substrate. . 7. The thin film transistor array substrate according to claim 6, wherein the end portion of the source signal line and the end portion of the source signal line are arranged on columns separated from each other. 8. The thin film transistor array according to claim 2, wherein an end portion of the source signal line and an end portion of the source signal line both for connecting to a signal circuit are arranged on opposite side edges of the substrate, respectively. substrate.