JP2003168769A - Power semiconductor device - Google Patents

Power semiconductor device

Info

Publication number
JP2003168769A
JP2003168769A JP2001365648A JP2001365648A JP2003168769A JP 2003168769 A JP2003168769 A JP 2003168769A JP 2001365648 A JP2001365648 A JP 2001365648A JP 2001365648 A JP2001365648 A JP 2001365648A JP 2003168769 A JP2003168769 A JP 2003168769A
Authority
JP
Japan
Prior art keywords
power semiconductor
main surface
insulating sheet
heat dissipation
dissipation plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001365648A
Other languages
Japanese (ja)
Inventor
Toshiaki Shinohara
利彰 篠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2001365648A priority Critical patent/JP2003168769A/en
Publication of JP2003168769A publication Critical patent/JP2003168769A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power semiconductor device which is excellent in heat dissipation even if an external radiator of low heat conductivity is used and is constituted to stant external impacts. <P>SOLUTION: The device has a plurality of power semiconductor elements 1, a plurality of conductive substrates 4 whereon the power semiconductor elements 1 are mounted, a wire line 3 for electrical connection between the power semiconductor elements 1, a plurality of terminal boards 61 and 62 for electrical connection between a plurality of power semiconductor elements 1 and an outside, an 0.2 to 0.8 mm-thick insulation sheet 5 disposed to cover an entire of a main surface (lower main surface) on the opposite side of a mounting surface (upper main surface) of the power semiconductor element 1 of the conductive substrate 4 and a flat heat sink 11 disposed so that its upper main surface comes into contact with a main surface on the opposite side of a contact surface of the insulation sheet 5 with the conductive substrate 4. An external radiator 8 is disposed so that its flat surface is in contact with a lower main surface of the heat sink 11 via grease 12 in between. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は電力用半導体装置に
関し、特に電力用半導体素子が樹脂封止されてパッケー
ジ化された電力用半導体装置の放熱構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and more particularly to a heat dissipation structure for a power semiconductor device in which a power semiconductor element is resin-sealed and packaged.

【0002】[0002]

【従来の技術】複数の電力用半導体素子がパッケージ化
された電力用半導体装置においては、電力用半導体素子
が発する熱を効率良く放熱するための工夫がなされてい
る。
2. Description of the Related Art A power semiconductor device in which a plurality of power semiconductor elements are packaged has been devised to efficiently dissipate heat generated by the power semiconductor element.

【0003】従来の電力用半導体装置の一例として、図
4および図5を用いて半導体パッケージ90の構成を説
明する。図4および図5に示すように半導体パッケージ
90は、複数の電力用半導体素子1と、該電力用半導体
素子1が搭載される複数の導電性基板4と、電力用半導
体素子1間の電気的接続を行うワイヤ線3と、複数の電
力用半導体素子1と外部との電気的接続を行う複数の端
子板61および62と、導電性基板4の電力用半導体素
子1の搭載面とは反対側の主面上に配設された絶縁シー
ト5とを備えている。
As an example of a conventional power semiconductor device, the structure of a semiconductor package 90 will be described with reference to FIGS. 4 and 5. As shown in FIGS. 4 and 5, the semiconductor package 90 includes a plurality of power semiconductor elements 1, a plurality of conductive substrates 4 on which the power semiconductor elements 1 are mounted, and an electrical connection between the power semiconductor elements 1. A wire wire 3 for connection, a plurality of terminal plates 61 and 62 for electrically connecting the plurality of power semiconductor elements 1 to the outside, and a side of the conductive substrate 4 opposite to the mounting surface of the power semiconductor element 1. And an insulating sheet 5 disposed on the main surface of the.

【0004】電力用半導体素子1は導電性基板4に面す
る側の主面(第1の主面と呼称)と、その反対側の主面
(第2の主面と呼称)とに、それぞれ主電極を備え、第
1の主面側の主電極は、導電性接合材2を介して導電性
基板4に電気的に接続され、導電性基板4を介して、端
子板61との間に主電流が流れる。
The power semiconductor element 1 has a main surface (referred to as a first main surface) facing the conductive substrate 4 and a main surface opposite to the main surface (referred to as a second main surface), respectively. A main electrode is provided, and the main electrode on the first main surface side is electrically connected to the conductive substrate 4 via the conductive bonding material 2 and between the terminal plate 61 and the conductive substrate 4. The main current flows.

【0005】従って、端子板61は導電性接合材2を介
して導電性基板4に電気的に接続されている。なお、端
子板62は、ワイヤ線3により電力用半導体素子1の第
2の主面側の主電極に電気的に接続され、導電性基板4
には接続されていない。
Therefore, the terminal board 61 is electrically connected to the conductive substrate 4 through the conductive bonding material 2. The terminal plate 62 is electrically connected to the main electrode on the second main surface side of the power semiconductor element 1 by the wire line 3, and the conductive substrate 4 is provided.
Not connected to.

【0006】そして、導電性基板4、端子板61および
62、ワイヤ線3および電力用半導体素子1は、例えば
エポキシ樹脂により封止され、端子板61および62の
一部分が樹脂パッケージ7から外部に突出する構造とな
っている。
The conductive substrate 4, the terminal plates 61 and 62, the wire 3 and the power semiconductor element 1 are sealed with, for example, an epoxy resin, and a part of the terminal plates 61 and 62 is projected from the resin package 7 to the outside. It has a structure that

【0007】なお、樹脂パッケージ7の底面には、絶縁
シート5の面積および厚さに対応する窪みが設けられ、
当該窪みの底面には導電性基板4の下主面が露出してい
る。絶縁シート5がこの窪みにはめ込まれ、外部放熱器
8上に搭載される構成となっている。
A depression corresponding to the area and thickness of the insulating sheet 5 is provided on the bottom surface of the resin package 7,
The lower main surface of the conductive substrate 4 is exposed on the bottom surface of the depression. The insulating sheet 5 is fitted into this recess and mounted on the external radiator 8.

【0008】従って、電力用半導体素子1が発する熱の
大部分は、導電性基板4および絶縁シート5を介して外
部放熱器8に伝わることで放熱されることになる。
Therefore, most of the heat generated by the power semiconductor element 1 is transferred to the external radiator 8 through the conductive substrate 4 and the insulating sheet 5 and is radiated.

【0009】図5に、図4におけるX−X線での矢視方
向断面の構成を示す。図6に示すように、複数の電力用
半導体素子1は、複数の導電性基板4上に所定個数ずつ
搭載される。
FIG. 5 shows the structure of a cross section taken along line XX in FIG. As shown in FIG. 6, a plurality of power semiconductor elements 1 are mounted on a plurality of conductive substrates 4 by a predetermined number.

【0010】図4および図5に示す半導体パッケージ9
0においては、1組の端子板61および62と、2つの
半導体素子1とが1つの導電性基板4上に搭載されて1
組の素子ユニットEUを構成し、複数の素子ユニットE
Uは、互いに電気的に絶縁された存在となるように絶縁
シート5上に搭載されている。
The semiconductor package 9 shown in FIGS. 4 and 5.
In 0, one set of terminal boards 61 and 62 and two semiconductor elements 1 are mounted on one conductive substrate 4 and
A plurality of element units E that form a set of element units EU
The Us are mounted on the insulating sheet 5 so as to be electrically insulated from each other.

【0011】絶縁シート5は、素子ユニットEU間の電
気的絶縁を保つために必須の構成であるが、先に説明し
たように電力用半導体素子1が発する熱を外部放熱器8
に伝える必要もあるので、高熱伝導率を有する絶縁性フ
ィラーを含有した樹脂が使われるが、金属材料に比べる
と熱伝導率が小さく、熱抵抗を決定する要因となってい
る。
The insulating sheet 5 is an essential component for maintaining electrical insulation between the element units EU, but as described above, the heat generated by the power semiconductor element 1 is applied to the external radiator 8
Therefore, a resin containing an insulating filler having a high thermal conductivity is used, but the thermal conductivity is smaller than that of a metal material, which is a factor that determines the thermal resistance.

【0012】また、一般的には導電性基板4の材料とし
ては銅が使用されるが、外部放熱器8の材料としてはア
ルミニウムが使用され、両者の間には熱伝導率の差が存
在する。ここで、銅材の熱伝導率は約380W/mKで
あり、純アルミニウム材の熱伝導率は約240W/mK
であるので、外部放熱器8として純アルミニウムを用い
る場合には熱伝導率の差はそれほど大きくならないが、
シリコン(Si)を含んだアルミニウムを用いるため、
熱伝導率が小さくなる。
Copper is generally used as the material of the conductive substrate 4, but aluminum is used as the material of the external radiator 8, and there is a difference in thermal conductivity between the two. . Here, the thermal conductivity of the copper material is approximately 380 W / mK, and the thermal conductivity of the pure aluminum material is approximately 240 W / mK.
Therefore, when pure aluminum is used as the external radiator 8, the difference in thermal conductivity does not become so large,
Since aluminum containing silicon (Si) is used,
The thermal conductivity becomes small.

【0013】すなわち、外部放熱器8は図4に示すよう
に、複数のフィン81を有した複雑な形状を有してお
り、その製造は鋳造により行う。この場合、良好な成形
性を得るため、アルミニウムにSiを含有させるが、S
iを含有することで熱伝導率が低下し、180W/mK
程度となる。
That is, as shown in FIG. 4, the external radiator 8 has a complicated shape having a plurality of fins 81, and its manufacture is performed by casting. In this case, in order to obtain good moldability, Si is added to aluminum, but S
The thermal conductivity is lowered by containing i, and 180 W / mK
It will be about.

【0014】従って、電力用半導体素子1が発する熱
は、熱伝導率の高い導電性基板4から、熱伝導率の低い
絶縁シート5を介して外部放熱器8に伝わるが、外部放
熱器8の熱伝導率が低いため、十分な放熱が行われな
い。
Therefore, the heat generated by the power semiconductor element 1 is transmitted from the conductive substrate 4 having a high thermal conductivity to the external radiator 8 through the insulating sheet 5 having a low thermal conductivity. Due to its low thermal conductivity, it does not release sufficient heat.

【0015】特に、半導体パッケージ90のように、複
数の素子ユニットEUを有する構成においては、面積的
な制約から、各導電性基板4の素子搭載面となる上主面
の面積は限定され、絶縁シート5に接触する下主面の面
積も限定されたものとなる。従って、導電性基板4の熱
は、外部放熱器8の複数の場所、すなわち外部放熱器8
の下主面に対応する場所に、それぞれ局所的に集中して
与えられるが、熱伝導率が低い外部放熱器8においては
平面方向への熱拡散も効率的に行われないので、局所的
に温度が高くなって、十分な放熱が行われないなどの問
題も発生する。
In particular, in a structure having a plurality of element units EU such as the semiconductor package 90, the area of the upper main surface, which is an element mounting surface of each conductive substrate 4, is limited due to area restrictions, and insulation The area of the lower main surface that contacts the sheet 5 is also limited. Therefore, the heat of the conductive substrate 4 is applied to a plurality of places of the external radiator 8, that is, the external radiator 8.
Are locally concentrated at the locations corresponding to the lower main surface, but in the external radiator 8 having a low thermal conductivity, the heat diffusion in the planar direction is not performed efficiently, so that the local heat is locally distributed. There is also a problem that the temperature rises and sufficient heat is not released.

【0016】また、半導体パッケージ90においては、
その底面部に絶縁シート5が露出しているので、外力を
受けた場合に絶縁シート5が破損しやすいという問題も
有している。
Further, in the semiconductor package 90,
Since the insulating sheet 5 is exposed on the bottom surface, the insulating sheet 5 is easily damaged when an external force is applied.

【0017】なお、従来の電力用半導体装置の具体例と
しては、特開平10−93015号公報において、ヒー
トシンクとリードフレーム間に、高熱伝導率を有する樹
脂絶縁層、例えばガラス織布にエポキシ樹脂を含浸させ
た厚さ0.15mm程度の樹脂接着シートを挟んで熱圧
着し、ヒートシンクを含めて全体を樹脂封止する技術が
開示されている。しかし、ガラス織布接着シートは、通
常、1〜3W/mK程度の熱伝導率であり、大電力の電
力用半導体装置への適用には適さない。
As a concrete example of the conventional power semiconductor device, in Japanese Unexamined Patent Publication No. 10-93015, a resin insulating layer having a high thermal conductivity, such as a glass woven cloth, is coated with an epoxy resin between a heat sink and a lead frame. A technique is disclosed in which an impregnated resin adhesive sheet having a thickness of about 0.15 mm is sandwiched and thermocompression-bonded, and the whole is sealed with a resin including a heat sink. However, the glass woven fabric adhesive sheet usually has a thermal conductivity of about 1 to 3 W / mK and is not suitable for application to a high power electric power semiconductor device.

【0018】また、ヒートシンクを介しての放熱は、半
導体素子、半田層、熱拡散板、半田層、リードフレー
ム、樹脂絶縁層およびヒートシンクの計7つの層を通し
て行われるため、放熱特性には限界があり、この点から
も大電力の電力用半導体装置への適用には適さない。
Further, since the heat radiation through the heat sink is carried out through a total of seven layers including the semiconductor element, the solder layer, the heat diffusion plate, the solder layer, the lead frame, the resin insulating layer and the heat sink, the heat radiation characteristic is limited. Therefore, also from this point, it is not suitable for application to a high-power power semiconductor device.

【0019】従来の電力用半導体装置のさらなる一例と
しては、特開平6−310628号公報において、半導
体素子が搭載されたヒートシンクが素子ごとに分離さ
れ、基板の主面上に配設された導体層に半田付けにより
接合された構成が開示されているが、ヒートシンクを分
離する目的は、個々のヒートシンク上のみに被覆樹脂を
塗布することで、ヒートサイクルの信頼性を向上するこ
とにある。従って、ヒートシンク間の絶縁は空気絶縁で
あり、ヒートシンク間隔を広くする必要がある。
As a further example of a conventional power semiconductor device, in JP-A-6-310628, a heat sink on which a semiconductor element is mounted is separated for each element, and a conductor layer is provided on the main surface of a substrate. However, the purpose of separating the heat sinks is to improve the reliability of the heat cycle by applying the coating resin only on the individual heat sinks. Therefore, the insulation between the heat sinks is air insulation, and it is necessary to widen the heat sink intervals.

【0020】[0020]

【発明が解決しようとする課題】本発明は上記のような
問題点を解消するためになされたもので、熱伝導率が低
い外部放熱器を用いる場合であっても、放熱性に優れ、
また、外力による破損を受けにくい構成の電力用半導体
装置を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and is excellent in heat dissipation even when an external radiator having a low thermal conductivity is used.
It is another object of the present invention to provide a power semiconductor device that is less likely to be damaged by an external force.

【0021】[0021]

【課題を解決するための手段】本発明に係る請求項1記
載の電力用半導体装置は、金属で構成された放熱板と、
前記放熱板の上主上に配設され、前記放熱板に密着する
絶縁シートと、前記絶縁シートの上主面に、その下主面
が接触し、互いに電気的に独立して配設された複数の導
電性基板と、前記複数の導電性基板の上主面上にそれぞ
れ配設された電力用半導体素子と、少なくとも、前記複
数の導電性基板および前記電力用半導体素子を樹脂封止
する樹脂パッケージとを備え、前記放熱板は、前記複数
の導電性基板と同等以上の熱伝導率を有する材質で構成
されている。
According to a first aspect of the present invention, there is provided a power semiconductor device including: a heat dissipation plate made of metal;
An insulating sheet disposed on the heat radiating plate and closely attached to the heat radiating plate, and a lower main surface of the insulating sheet contacting the upper main surface of the insulating sheet, and the insulating sheets are electrically independent of each other. A plurality of conductive substrates, a power semiconductor element respectively disposed on the upper main surface of the plurality of conductive substrates, and at least a resin that seals the plurality of conductive substrates and the power semiconductor element with a resin. And a heat dissipation plate made of a material having a thermal conductivity equal to or higher than that of the plurality of conductive substrates.

【0022】本発明に係る請求項2記載の電力用半導体
装置は、前記放熱板が、前記上主面の一方向に渡る突条
部と直線状の溝部とが交互に平行して複数配設された波
打ち形状を有し、前記複数の導電性基板のそれぞれは、
前記下主面の全面に渡って突条部と溝部とが交互に平行
して複数配設された波打ち形状を有し、前記放熱板の波
打ち形状と前記導電性基板の波打ち形状とは合同な関係
を有し、前記複数の導電性基板の前記突条部と前記放熱
板の前記溝部とが、前記絶縁シートを間に介して対峙す
るように配設される。
According to a second aspect of the present invention, there is provided a power semiconductor device in which a plurality of ridges and linear grooves extending in one direction of the upper main surface are alternately arranged in parallel in the heat dissipation plate. Each of the plurality of conductive substrates has a wavy shape
It has a corrugated shape in which a plurality of ridges and grooves are alternately arranged in parallel all over the lower main surface, and the corrugated shape of the heat dissipation plate and the corrugated shape of the conductive substrate are congruent. In relation to each other, the protrusions of the plurality of conductive substrates and the groove of the heat dissipation plate are arranged so as to face each other with the insulating sheet interposed therebetween.

【0023】本発明に係る請求項3記載の電力用半導体
装置は、前記絶縁シートが、無機材料フィラーを含有し
たシリコーンゴムで構成され、その主面には粘着性物質
が塗布され、その硬度は、アスカーCスケールで、10
〜50の硬度を有する。
According to a third aspect of the present invention, there is provided a power semiconductor device in which the insulating sheet is made of silicone rubber containing an inorganic material filler, a principal surface of which is coated with an adhesive substance and has a hardness of , 10 on the Asker C scale
It has a hardness of -50.

【0024】本発明に係る請求項4記載の電力用半導体
装置は、前記放熱板および前記絶縁シートが前記樹脂パ
ッケージ内に封止された状態で、少なくとも前記樹脂パ
ッケージおよび前記放熱板の端縁部において連通する複
数の貫通穴を有し、前記電力用半導体装置は、外部に設
けられた放熱器に前記複数の貫通穴を介してネジ止めさ
れる。
According to a fourth aspect of the present invention, there is provided a power semiconductor device, wherein at least the edge portions of the resin package and the heat dissipation plate are in a state where the heat dissipation plate and the insulating sheet are sealed in the resin package. In, the power semiconductor device is screwed to a radiator provided outside through the plurality of through holes.

【0025】[0025]

【発明の実施の形態】<A.実施の形態1> <A−1.装置構成>本発明に係る電力用半導体装置の
実施の形態1として、図1および図2を用いて半導体パ
ッケージ100の構成を説明する。
BEST MODE FOR CARRYING OUT THE INVENTION <A. Embodiment 1><A-1. Device Configuration> As a first embodiment of a power semiconductor device according to the present invention, a configuration of a semiconductor package 100 will be described with reference to FIGS. 1 and 2.

【0026】図1および図2に示すように半導体パッケ
ージ100は、複数の電力用半導体素子1と、該電力用
半導体素子1が搭載される複数の導電性基板4と、電力
用半導体素子1間の電気的接続を行うワイヤ線3と、複
数の電力用半導体素子1と外部との電気的接続を行う複
数の端子板61および62と、導電性基板4の電力用半
導体素子1の搭載面(上主面)とは反対側の主面(下主
面)上に配設された厚さ0.2〜0.8mmの絶縁シー
ト5と、絶縁シート5の導電性基板4との接触面とは反
対側の主面に、その上主面が接触するように配設された
平板状の放熱板11とを備えている。そして、放熱板1
1の下主面には、グリス12を間に介してその平坦面が
接触するように外部放熱器8が配設されている。
As shown in FIGS. 1 and 2, the semiconductor package 100 includes a plurality of power semiconductor elements 1, a plurality of conductive substrates 4 on which the power semiconductor elements 1 are mounted, and power semiconductor elements 1 and 2. Wire lines 3 for making electrical connection with each other, a plurality of terminal plates 61 and 62 for making electrical connection between the plurality of power semiconductor elements 1 and the outside, and the mounting surface of the power semiconductor element 1 on the conductive substrate 4 ( An insulating sheet 5 having a thickness of 0.2 to 0.8 mm arranged on a main surface (lower main surface) opposite to the upper main surface, and a contact surface of the insulating sheet 5 with the conductive substrate 4. Is provided with a flat plate-shaped heat radiating plate 11 arranged on the opposite main surface so that its upper main surface is in contact. And the heat sink 1
An external radiator 8 is arranged on the lower main surface of 1 so that its flat surface contacts with the grease 12 interposed therebetween.

【0027】電力用半導体素子1は導電性基板4に面す
る側の主面(下主面)と、その反対側の主面(上主面)
とに、それぞれ主電極を備え、第1の主面側の主電極
は、導電性接合材2、例えば半田層を介して導電性基板
4に電気的に接続され、導電性基板4を介して端子板6
1との間に主電流が流れる。従って、導電性基板4は配
線導体としての機能も有し、端子板61は導電性接合材
2を介して導電性基板4に電気的に接続されている。な
お、導電性基板4には電導率および熱伝導率の良好な材
質、例えば、銅が使用される。なお、端子板62は、ワ
イヤ線3により電力用半導体素子1の第2の主面側の主
電極に電気的に接続され、導電性基板4には接続されて
いない。
The power semiconductor device 1 has a main surface (lower main surface) facing the conductive substrate 4 and a main surface (upper main surface) opposite to the main surface.
And a main electrode on the first main surface side, and the main electrode on the first main surface side is electrically connected to the conductive substrate 4 via a conductive bonding material 2, for example, a solder layer, Terminal board 6
The main current flows between 1 and 1. Therefore, the conductive substrate 4 also has a function as a wiring conductor, and the terminal plate 61 is electrically connected to the conductive substrate 4 via the conductive bonding material 2. The conductive substrate 4 is made of a material having good electric conductivity and thermal conductivity, for example, copper. The terminal plate 62 is electrically connected to the main electrode on the second main surface side of the power semiconductor element 1 by the wire 3 and is not connected to the conductive substrate 4.

【0028】そして、導電性基板4、端子板61および
62、ワイヤ線3および電力用半導体素子1は、例えば
エポキシ樹脂により封止され、端子板61および62の
一部分が樹脂パッケージ7から外部に突出する構造とな
っている。
Then, the conductive substrate 4, the terminal plates 61 and 62, the wire 3 and the power semiconductor element 1 are sealed with, for example, an epoxy resin, and a part of the terminal plates 61 and 62 is projected from the resin package 7 to the outside. It has a structure that

【0029】なお、樹脂パッケージ7の底面には、絶縁
シート5の面積および厚さに対応する窪みが設けられ、
当該窪みの底面には導電性基板4の下主面が露出してい
る。絶縁シート5がこの窪みにはめ込まれ、放熱板11
上に搭載される。窪みの深さは、絶縁シート5の厚さと
同等以下であれば良い。
A depression corresponding to the area and thickness of the insulating sheet 5 is provided on the bottom surface of the resin package 7,
The lower main surface of the conductive substrate 4 is exposed on the bottom surface of the depression. The insulating sheet 5 is fitted into this recess, and the heat sink 11
Mounted on. The depth of the depression may be equal to or less than the thickness of the insulating sheet 5.

【0030】図2に、図1におけるA−A線での矢視方
向断面の構成を示す。図2に示すように、複数の電力用
半導体素子1は、絶縁シート5上に配列された複数の導
電性基板4上に所定個数ずつ搭載されている。
FIG. 2 shows the structure of a cross section taken along line AA in FIG. As shown in FIG. 2, a plurality of power semiconductor elements 1 are mounted on a plurality of conductive substrates 4 arranged on an insulating sheet 5 in a predetermined number.

【0031】図1および図2に示す半導体パッケージ1
00においては、1組の端子板61および62と、2つ
の半導体素子1とが1つの導電性基板4上に搭載されて
1組の素子ユニットEUを構成し、複数の素子ユニット
EUは、互いに電気的に絶縁された存在となるように絶
縁シート5上に搭載されている。なお、素子ユニットE
Uは上述した構成に限定されず、さらに多くの半導体素
子1を有する場合や、端子板61および62を複数組有
する場合もあり、集積回路を備えている場合もある。ま
た、素子ユニットEU間が電気的に接続されている場合
もある。
A semiconductor package 1 shown in FIGS. 1 and 2.
In 00, one set of terminal boards 61 and 62 and two semiconductor elements 1 are mounted on one conductive substrate 4 to form one set of element units EU, and the plurality of element units EU are mutually connected. It is mounted on the insulating sheet 5 so as to be electrically insulated. The element unit E
U is not limited to the configuration described above, and may have a larger number of semiconductor elements 1, may have a plurality of sets of terminal plates 61 and 62, and may have an integrated circuit. Further, the element units EU may be electrically connected to each other.

【0032】ここで、放熱板11は、導電性基板4と同
じ材質、例えば銅で構成され、その主面は複数の導電性
基板4の配列を搭載して、さらに余裕を有する大きさに
設定されている。絶縁シート5は導電性基板4の配列領
域に対応する面積を有している。
Here, the heat dissipation plate 11 is made of the same material as the conductive substrate 4, for example, copper, and its main surface is mounted with an array of a plurality of conductive substrates 4 and is set to a size having a further margin. Has been done. The insulating sheet 5 has an area corresponding to the array region of the conductive substrates 4.

【0033】絶縁シート5は高熱伝導率を有する無機材
料フィラーを含有したシリコーンゴムなどで構成され、
その主面には粘着性物質が塗布されており、複数の導電
性基板4や放熱板11と密着している。上記無機材料フ
ィラーとしては、アルミナ(Al23)、窒化アルミニ
ウム(AlN)、窒化ホウ素(BN)、炭化シリコン
(SiC)、シリカ(SiO2)、あるいはこれらのう
ち複数を混合したものが使用される。そして、絶縁シー
ト5の熱伝導率は3〜15W/mKであり、その硬度
は、日本ゴム協会標準規格の膨張ゴムの試験方法の1つ
であるアスカー(Asker)C型硬度計を用いた測定(ア
スカーCスケール)で、10〜50の硬度を有してい
る。硬度は、数値が小さくなるほど柔らかくなり、放熱
板11との密着性が向上して接触熱抵抗が小さくなって
放熱特性が改善されるが、硬度10以下になると、機械
的強度が低下し、取り扱いが難しくなる。また、硬度5
0以上になると接触熱抵抗が無視できない程度に大きく
なる。
The insulating sheet 5 is made of silicone rubber or the like containing an inorganic material filler having a high thermal conductivity,
An adhesive substance is applied to its main surface and is in close contact with the plurality of conductive substrates 4 and the heat dissipation plate 11. As the inorganic material filler, alumina (Al 2 O 3 ), aluminum nitride (AlN), boron nitride (BN), silicon carbide (SiC), silica (SiO 2 ), or a mixture of a plurality of these is used. To be done. The thermal conductivity of the insulating sheet 5 is 3 to 15 W / mK, and its hardness is measured using an Asker C-type hardness tester, which is one of the testing methods for expanded rubber of the Japan Rubber Association standard. It has a hardness of 10 to 50 on the (Asker C scale). The hardness becomes softer as the numerical value becomes smaller, the adhesion with the heat dissipation plate 11 improves, the contact heat resistance decreases and the heat dissipation property improves, but when the hardness becomes 10 or less, the mechanical strength decreases and the handling Becomes difficult. Also, hardness 5
When it is 0 or more, the contact thermal resistance becomes so large that it cannot be ignored.

【0034】なお、グリス12は、当該電力用半導体装
置がインバータなどに使用される場合に、放熱板11の
他方主面に塗布され、外部放熱器8(ヒートシンク)の
平坦面(フィン81とは反対側の主面が)に密着してい
る。グリス12の熱伝導率は1〜3W/mKである。
When the power semiconductor device is used for an inverter or the like, the grease 12 is applied to the other main surface of the heat dissipation plate 11, and the flat surface of the external radiator 8 (heat sink) (fin 81 is not used). The main surface on the other side is in close contact with. The thermal conductivity of the grease 12 is 1 to 3 W / mK.

【0035】なお、半導体パッケージ100の製造にお
いては、導電性基板4、端子板61および62、ワイヤ
線3および電力用半導体素子1を、例えばエポキシ樹脂
により封止し、樹脂パッケージ7の底面に設けた、絶縁
シート5の面積および厚さに合致する窪みに絶縁シート
5はめ込み、放熱板11上に搭載すれば良い。
In the manufacture of the semiconductor package 100, the conductive substrate 4, the terminal plates 61 and 62, the wire 3 and the power semiconductor element 1 are sealed with, for example, an epoxy resin and provided on the bottom surface of the resin package 7. Further, the insulating sheet 5 may be fitted into a recess matching the area and thickness of the insulating sheet 5 and mounted on the heat dissipation plate 11.

【0036】なお、絶縁シート5上に複数の導電性基板
4を搭載し、導電性基板4上に電力用半導体素子1、端
子板61および62を搭載した状態で、エポキシ樹脂に
よる封止を行うことで、絶縁シート5が樹脂パッケージ
7に封止される構成としても良い。この場合、絶縁シー
ト5の下主面は樹脂パッケージ7の底面から露出させ
る。
Incidentally, a plurality of conductive substrates 4 are mounted on the insulating sheet 5, and the power semiconductor element 1 and the terminal plates 61 and 62 are mounted on the conductive substrate 4, and sealing is performed with an epoxy resin. Thus, the insulating sheet 5 may be sealed in the resin package 7. In this case, the lower main surface of the insulating sheet 5 is exposed from the bottom surface of the resin package 7.

【0037】また、絶縁シート5だけでなく、放熱板1
1も併せて樹脂封止される構成としても良い。
In addition to the insulating sheet 5, the heat sink 1
1 may also be resin-sealed together.

【0038】また、図2に示すように、樹脂パッケージ
7および放熱板11のそれぞれの端縁部において連通す
る貫通孔HLを設け、外部放熱器8には貫通孔HL対応
する位置にネジ穴SLを設け、両者をネジ13により締
結することで、放熱板11と外部放熱器8とが結合し、
その際に絶縁シート5が厚さ方向に加圧されて導電性基
板4および外部放熱器8との密着性が向上する。また、
このとき、グリス12も加圧され、極めて薄い層とな
る。
Further, as shown in FIG. 2, through holes HL communicating with the respective edge portions of the resin package 7 and the heat dissipation plate 11 are provided, and the external radiator 8 is provided with screw holes SL at positions corresponding to the through holes HL. Is provided, and both are fastened with screws 13, so that the radiator plate 11 and the external radiator 8 are coupled,
At that time, the insulating sheet 5 is pressed in the thickness direction to improve the adhesion between the conductive substrate 4 and the external radiator 8. Also,
At this time, the grease 12 is also pressed to form an extremely thin layer.

【0039】<A−2.作用効果>以上説明した半導体
パッケージ100においては、電力用半導体素子1が発
する熱は、まず、銅で構成される導電性基板4全体に拡
散し、絶縁シート5を介して放熱板11に伝わる。放熱
板11は熱伝導率が良好な銅で構成されており、導電性
基板4を介して局所的に伝えられる熱は平面方向にも拡
散して、放熱板11内に分布する。
<A-2. Function and Effect> In the semiconductor package 100 described above, the heat generated by the power semiconductor element 1 is first diffused to the entire conductive substrate 4 made of copper and transmitted to the heat dissipation plate 11 via the insulating sheet 5. The heat dissipation plate 11 is made of copper having a good thermal conductivity, and the heat locally transmitted through the conductive substrate 4 diffuses in the plane direction and is distributed in the heat dissipation plate 11.

【0040】放熱板11の熱は、グリス12の薄い層を
介して外部放熱器8に伝わるが、放熱板11は均一な温
度になっているので、外部放熱器8において熱の集中が
発生することがなく、フィン81によって放熱されるこ
とになる。
The heat of the radiator plate 11 is transmitted to the external radiator 8 through the thin layer of the grease 12, but since the radiator plate 11 has a uniform temperature, heat concentration occurs in the external radiator 8. And the heat is dissipated by the fin 81.

【0041】このように、熱伝導率の良好な材質で構成
された放熱板11を絶縁シート5と外部放熱器8との間
に備えることで、外部放熱器8が熱伝導率が低い材質で
構成されている場合であっても、放熱特性が低下しない
電力用半導体装置を得ることができる。
As described above, by disposing the heat dissipation plate 11 made of a material having a good thermal conductivity between the insulating sheet 5 and the external radiator 8, the external radiator 8 is made of a material having a low thermal conductivity. Even when configured, it is possible to obtain a power semiconductor device in which the heat dissipation characteristics are not deteriorated.

【0042】また、絶縁シート5の主面が放熱板11に
よって覆われているので、絶縁シート5が外力による破
損を受けにくく、破損に起因する絶縁不良などの発生を
防止できる。
Further, since the main surface of the insulating sheet 5 is covered with the heat dissipation plate 11, the insulating sheet 5 is less likely to be damaged by an external force, and the occurrence of insulation failure due to the damage can be prevented.

【0043】なお、半導体パッケージ100において
は、導電性基板4および放熱板11が銅で構成された例
を示したが、放熱板11が導電性基板4と同等以上の熱
伝導率を有する材質で構成されているのであれば、放熱
板11と導電性基板4との材質が異なっていても良い。
In the semiconductor package 100, the conductive substrate 4 and the heat sink 11 are made of copper, but the heat sink 11 is made of a material having a thermal conductivity equal to or higher than that of the conductive substrate 4. As long as it is configured, the heat dissipation plate 11 and the conductive substrate 4 may be made of different materials.

【0044】<B.実施の形態2> <B−1.装置構成>本発明に係る電力用半導体装置の
実施の形態2として、図3を用いて半導体パッケージ2
00の構成を説明する。
<B. Second Embodiment><B-1. Device Configuration> As a second embodiment of the power semiconductor device according to the present invention, a semiconductor package 2 will be described with reference to FIG.
The configuration of 00 will be described.

【0045】図3に示すように半導体パッケージ200
は、複数の電力用半導体素子1と、該電力用半導体素子
1が搭載される複数の導電性基板4Aと、電力用半導体
素子1間の電気的接続を行うワイヤ線3と、複数の電力
用半導体素子1と外部との電気的接続を行う複数の端子
板61および62と、導電性基板4Aの電力用半導体素
子1の搭載面(上主面)とは反対側の主面(下主面)全
面を覆うように配設された厚さ0.5mm程度の絶縁シ
ート5Aと、絶縁シート5Aの導電性基板4Aとの接触
面とは反対側の主面に、その上主面が接触するように配
設された放熱板11Aと、放熱板11Aの下主面に、グ
リス12を間に介してその平坦面が接触するように配設
された外部放熱器8とを備えている。なお、その他、図
1および図2に示した半導体パッケージ100と同一の
構成については同一の符号を付し、重複する説明は省略
する。
As shown in FIG. 3, the semiconductor package 200
Is a plurality of power semiconductor elements 1, a plurality of conductive substrates 4A on which the power semiconductor elements 1 are mounted, wire lines 3 for electrically connecting the power semiconductor elements 1, and a plurality of power A plurality of terminal plates 61 and 62 for electrically connecting the semiconductor element 1 to the outside, and a main surface (lower main surface) of the conductive substrate 4A opposite to the mounting surface (upper main surface) of the power semiconductor element 1 thereon. ) The insulating sheet 5A having a thickness of about 0.5 mm arranged so as to cover the entire surface and the upper main surface of the insulating sheet 5A are in contact with the main surface of the insulating sheet 5A opposite to the contact surface with the conductive substrate 4A. The heat radiating plate 11A thus arranged is provided, and the external heat radiator 8 is arranged on the lower main surface of the heat radiating plate 11A so that its flat surface is in contact with the grease 12 in between. In addition, other than that, the same components as those of the semiconductor package 100 shown in FIGS.

【0046】ここで、熱伝導率の良好な材質で構成され
た放熱板11Aを絶縁シート5Aと外部放熱器8との間
に備えるという点では、図1および図2を用いて説明し
た半導体パッケージ100と同様であるが、放熱板11
Aの導電性基板4Aを搭載する側の主面は、放熱板11
Aのほぼ全面に渡って突条部CPと直線状の溝部GPと
が交互に平行して複数配設された波打ち形状に成形さ
れ、当該主面の形状に対応するように導電性基板4Aの
下主面も波打ち形状に成形されている。
Here, in that the heat sink 11A made of a material having a good thermal conductivity is provided between the insulating sheet 5A and the external radiator 8, the semiconductor package described with reference to FIGS. Similar to 100, but with heat sink 11
The main surface of A on which the conductive substrate 4A is mounted is the heat sink 11
A plurality of ridges CP and linear grooves GP are alternately arranged in parallel over almost the entire surface of A to form a corrugated shape, and the conductive substrate 4A is formed so as to correspond to the shape of the main surface. The lower main surface is also formed in a wavy shape.

【0047】ここで、放熱板11Aおよび導電性基板4
Aに設けられる波打ち形状は、放熱板11Aの厚さの3
分の1程度の谷の深さおよび山の高さを有しており、放
熱板11Aの溝部GPには導電性基板4Aの突条部CP
が対峙し、放熱板11Aの突条部CPには導電性基板4
Aの溝部が対峙するように、複数の導電性基板4Aが配
列される。
Here, the heat sink 11A and the conductive substrate 4
The corrugated shape provided on A is 3 times the thickness of the heat sink 11A.
It has a depth of a valley and a height of a peak of about one-half, and the protrusion GP of the conductive substrate 4A is provided in the groove GP of the heat sink 11A.
And the conductive substrate 4 is attached to the ridge CP of the heat sink 11A.
A plurality of conductive substrates 4A are arranged so that the groove portions of A face each other.

【0048】<B−2.作用効果>以上説明したよう
に、放熱板11Aおよび導電性基板4Aの互いに対向す
る面を波打ち形状とすることで、両者の間に挟まれる絶
縁シート5Aの表面積が増え、熱抵抗を低減することが
できる。
<B-2. Effect> As described above, by making the surfaces of the heat dissipation plate 11A and the conductive substrate 4A facing each other into a wavy shape, the surface area of the insulating sheet 5A sandwiched between the two increases, and the thermal resistance is reduced. You can

【0049】なお、絶縁シート5Aの破損を防ぐ観点か
ら、放熱板11Aおよび導電性基板4Aに設けられる波
打ち形状は緩やかな曲面を有するサイン波状の形状とな
っているが、絶縁シート5Aの破損を防ぐことができる
のであれば、U字型の断面形状が連なった構成であって
も良い。
From the viewpoint of preventing damage to the insulating sheet 5A, the corrugated shape provided on the heat dissipation plate 11A and the conductive substrate 4A has a sine wave shape having a gentle curved surface. A configuration in which U-shaped cross-sectional shapes are continuous may be used if it can be prevented.

【0050】また、半導体パッケージ200において
は、樹脂パッケージ7が放熱板11Aも併せて樹脂封止
しているが、外部放熱器8の平坦面と対向する放熱板1
1Aの下主面は、樹脂パッケージ7の底面から露出して
おり、グリス12を間に介して外部放熱器8の平坦面に
接触する構成となっている。
Further, in the semiconductor package 200, the resin package 7 also seals the heat sink 11A with resin, but the heat sink 1 facing the flat surface of the external radiator 8 is also included.
The lower main surface of 1A is exposed from the bottom surface of the resin package 7, and is in contact with the flat surface of the external radiator 8 with the grease 12 interposed therebetween.

【0051】なお、樹脂パッケージ7が絶縁シート5A
上の構成を封止し、絶縁シート5Aおよび放熱板11A
については封止しない構成としても良いことは言うまで
もない。
The resin package 7 is the insulating sheet 5A.
Insulating sheet 5A and heat sink 11A that seal the above configuration
It goes without saying that the above may not be sealed.

【0052】また、放熱板11Aと外部放熱器8との結
合は、図2を用いて説明したように、樹脂パッケージ7
の端縁部にネジを挿入する貫通穴HLを設け、外部放熱
器8には貫通孔HL対応する位置にネジ穴SLを設け、
両者をネジ13により締結することで行えば良い。
The heat radiation plate 11A and the external heat radiator 8 are coupled to each other by the resin package 7 as described with reference to FIG.
A through hole HL into which a screw is inserted is provided at an edge portion of the external radiator 8, and a screw hole SL is provided at a position corresponding to the through hole HL in the external radiator 8.
It suffices to fasten both with screws 13.

【0053】なお、特開平4−94153号公報には、
半導体素子が搭載されるアイランドの下主面が波形に成
形され、対向配置された放熱フィンの一方主面も波形に
成形され、両者の波打ち形状が互いに向かい合うように
配置された構成が開示されている。しかし、アイランド
と放熱フィンとは樹脂封止されており、両者の向かい合
う波打ち形状の間隙には封止樹脂が充填されている。従
って、アイランド上の半導体層で発生する熱は、封止樹
脂を介して放熱フィンに伝わることになり、放熱特性は
封止樹脂の熱伝導率によって規定される。
Incidentally, Japanese Patent Laid-Open No. 4-94153 discloses that
A configuration is disclosed in which a lower main surface of an island on which a semiconductor element is mounted is formed in a corrugated shape, one main surface of a heat dissipating fin arranged oppositely is also formed in a corrugated shape, and the corrugated shapes of both are arranged to face each other. There is. However, the island and the radiating fin are resin-sealed, and the wave-shaped gaps facing each other are filled with the sealing resin. Therefore, the heat generated in the semiconductor layer on the island is transmitted to the heat radiation fin through the sealing resin, and the heat radiation characteristic is defined by the thermal conductivity of the sealing resin.

【0054】そして、熱伝導率を上げるためにフィラー
を高密度に含んだ樹脂を用いると、製造コストが増大
し、また、アイランドと放熱フィンとの間隙は熱抵抗を
下げるために狭く形成されるが、そこにフィラーを高密
度に含み、流動性が小さい樹脂を充填しようとすると、
ボイドが発生するなどの問題が発生する。
If a resin containing a high density of filler is used to increase the thermal conductivity, the manufacturing cost increases, and the gap between the island and the radiation fin is formed narrow to reduce the thermal resistance. However, if you try to fill a resin that contains filler with a high density and has low fluidity,
Problems such as voids occur.

【0055】しかし、本実施の形態における絶縁シート
5Aは、予めフィラーを高密度に含んで構成することが
可能であり、熱抵抗が小さくでき、ボイドが発生するこ
ともない。
However, the insulating sheet 5A in the present embodiment can be preliminarily configured to contain a high density of filler, the thermal resistance can be reduced, and voids are not generated.

【0056】また、樹脂パッケージ7の材質としては、
高熱伝導率を有する高価なフィラーを高密度に含んだ樹
脂である必要はないので、製造コストを低減することが
できる。
Further, as the material of the resin package 7,
Since it is not necessary for the resin to contain an expensive filler having a high thermal conductivity in a high density, it is possible to reduce the manufacturing cost.

【0057】[0057]

【発明の効果】本発明に係る請求項1記載の電力用半導
体装置によれば、電力用半導体素子が発する熱は、ま
ず、個々の導電性基板全体に拡散し、絶縁シートを介し
て放熱板に伝わる。導電性基板は例えば銅などの熱伝導
率が良好な材質で形成され、放熱板も導電性基板と同等
以上の熱伝導率を有する材質で構成されるので、複数の
導電性基板を介して局所的に伝えられる熱は放熱板の平
面方向にも拡散して、放熱板内に分布する。従って、例
えば、放熱板を外部に設けられた放熱器に取り付けた場
合に、外部放熱器において熱の集中部が発生することが
なく、外部放熱器が熱伝導率が低い材質で構成されてい
る場合であっても、放熱特性が低下しない電力用半導体
装置を得ることができる。絶縁シートの下主面が放熱板
によって覆われることになるので、絶縁シートが外力に
よる破損を受けにくく、破損に起因する絶縁不良などの
発生を防止できる。
According to the power semiconductor device of the first aspect of the present invention, the heat generated by the power semiconductor element is first diffused over the individual conductive substrates, and then the heat radiating plate is inserted through the insulating sheet. Be transmitted to. The conductive substrate is made of a material having a good thermal conductivity such as copper, and the heat dissipation plate is also made of a material having a thermal conductivity equal to or higher than that of the conductive substrate. The heat that is transmitted is diffused in the plane direction of the heat dissipation plate and distributed in the heat dissipation plate. Therefore, for example, when the radiator plate is attached to the radiator provided outside, a heat concentration portion does not occur in the external radiator, and the external radiator is made of a material having low thermal conductivity. Even in such a case, it is possible to obtain a power semiconductor device in which the heat dissipation characteristics are not deteriorated. Since the lower main surface of the insulating sheet is covered with the heat radiating plate, the insulating sheet is less likely to be damaged by an external force, and it is possible to prevent the occurrence of defective insulation due to the damage.

【0058】本発明に係る請求項2記載の電力用半導体
装置によれば、放熱板および導電性基板の互いに対向す
る主面が波打ち形状となっているので、両者の間に挟ま
れる絶縁シートの表面積が増え、熱抵抗を低減すること
ができ、放熱特性が向上した電力用半導体装置を得るこ
とができる。
According to the second aspect of the power semiconductor device of the present invention, since the main surfaces of the heat dissipation plate and the conductive substrate which face each other have a wavy shape, the insulating sheet sandwiched between the two faces is formed. A surface area is increased, thermal resistance can be reduced, and a power semiconductor device with improved heat dissipation characteristics can be obtained.

【0059】本発明に係る請求項3記載の電力用半導体
装置によれば、放熱板との密着性が向上して接触熱抵抗
が小さくなって放熱特性を改善できるとともに、機械的
強度を維持して、取り扱いに困難をきたさない絶縁シー
トを得ることができる。
According to the third aspect of the power semiconductor device of the present invention, the adhesion to the heat sink is improved and the contact thermal resistance is reduced to improve the heat dissipation characteristics, while maintaining the mechanical strength. Thus, it is possible to obtain an insulating sheet that is easy to handle.

【0060】本発明に係る請求項4記載の電力用半導体
装置によれば、電力用半導体装置を、外部に設けられた
放熱器に、複数の貫通穴を介してネジ止めするので、絶
縁シートが厚さ方向に加圧されて導電性基板および外部
の放熱器との密着性が向上する。
According to the power semiconductor device of the fourth aspect of the present invention, since the power semiconductor device is screwed to the radiator provided outside through the plurality of through holes, the insulating sheet is provided. The pressure is applied in the thickness direction to improve the adhesion between the conductive substrate and the external radiator.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明に係る実施の形態1の電力用半導体装
置の構成を示す断面図である。
FIG. 1 is a cross-sectional view showing a configuration of a power semiconductor device according to a first embodiment of the present invention.

【図2】 本発明に係る実施の形態1の電力用半導体装
置の構成を示す断面図である。
FIG. 2 is a cross-sectional view showing the configuration of the power semiconductor device according to the first embodiment of the present invention.

【図3】 本発明に係る実施の形態2の電力用半導体装
置の構成を示す断面図である。
FIG. 3 is a sectional view showing a configuration of a power semiconductor device according to a second embodiment of the present invention.

【図4】 従来の電力用半導体装置の構成を示す断面図
である。
FIG. 4 is a cross-sectional view showing a configuration of a conventional power semiconductor device.

【図5】 従来の電力用半導体装置の構成を示す断面図
である。
FIG. 5 is a cross-sectional view showing a configuration of a conventional power semiconductor device.

【符号の説明】[Explanation of symbols]

1 電力用半導体素子、4 導電性基板、5 絶縁シー
ト、7 樹脂パッケージ、8 外部放熱器、11 放熱
板、GP 溝部、CP 突条部、HL 貫通穴。
1 power semiconductor element, 4 conductive substrate, 5 insulating sheet, 7 resin package, 8 external radiator, 11 heat sink, GP groove, CP ridge, HL through hole.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 金属で構成された放熱板と、 前記放熱板の上主面上に配設され、前記放熱板に密着す
る絶縁シートと、 前記絶縁シートの上主面に、その下主面が接触し、互い
に電気的に独立して配設された複数の導電性基板と、 前記複数の導電性基板の上主面上にそれぞれ配設された
電力用半導体素子と、 少なくとも、前記複数の導電性基板および前記電力用半
導体素子を樹脂封止する樹脂パッケージと、を備え、 前記放熱板は、前記複数の導電性基板と同等以上の熱伝
導率を有する材質で構成される、電力用半導体装置。
1. A heat dissipation plate made of metal, an insulating sheet disposed on an upper main surface of the heat dissipation plate and in close contact with the heat dissipation plate, an upper main surface of the insulating sheet, and a lower main surface thereof. A plurality of conductive substrates that are in contact with each other and that are electrically independent of each other, and power semiconductor elements that are respectively disposed on the upper main surfaces of the plurality of conductive substrates, A power semiconductor, comprising: a conductive substrate and a resin package that seals the power semiconductor element with a resin, wherein the heat dissipation plate is made of a material having a thermal conductivity equal to or higher than that of the conductive substrates. apparatus.
【請求項2】 前記放熱板は、前記上主面の一方向に渡
る突条部と直線状の溝部とが交互に平行して複数配設さ
れた波打ち形状を有し、 前記複数の導電性基板のそれぞれは、前記下主面の全面
に渡って突条部と溝部とが交互に平行して複数配設され
た波打ち形状を有し、 前記放熱板の波打ち形状と前記導電性基板の波打ち形状
とは合同な関係を有し、 前記複数の導電性基板の前記突条部と前記放熱板の前記
溝部とが、前記絶縁シートを間に介して対峙するように
配設される、請求項1記載の電力用半導体装置。
2. The heat dissipation plate has a corrugated shape in which a plurality of ridges and linear grooves extending in one direction of the upper main surface are alternately arranged in parallel, and the plurality of conductive members are provided. Each of the substrates has a wavy shape in which a plurality of ridges and grooves are alternately arranged in parallel over the entire lower main surface, and the wavy shape of the heat dissipation plate and the wavy shape of the conductive substrate are provided. The shape has a congruent relationship, and the protrusions of the plurality of conductive substrates and the groove of the heat dissipation plate are arranged so as to face each other with the insulating sheet interposed therebetween. 1. The power semiconductor device according to 1.
【請求項3】 前記絶縁シートは、無機材料フィラーを
含有したシリコーンゴムで構成され、その主面には粘着
性物質が塗布され、その硬度は、アスカーCスケール
で、10〜50の硬度を有する、請求項1または請求項
2記載の電力用半導体装置。
3. The insulating sheet is composed of silicone rubber containing an inorganic material filler, an adhesive substance is applied to the main surface thereof, and the hardness thereof is 10-50 on the Asker C scale. The power semiconductor device according to claim 1 or 2.
【請求項4】 前記放熱板および前記絶縁シートが前記
樹脂パッケージ内に封止された状態で、少なくとも前記
樹脂パッケージおよび前記放熱板の端縁部において連通
する複数の貫通穴を有し、 前記電力用半導体装置は、外部に設けられた放熱器に前
記複数の貫通穴を介してネジ止めされる、請求項1また
は請求項2記載の電力用半導体装置。
4. The power radiating plate and the insulating sheet are sealed in the resin package, and have a plurality of through holes communicating at least at an edge portion of the resin package and the heat radiating plate. 3. The power semiconductor device according to claim 1, wherein the power semiconductor device is screwed to a radiator provided outside through the plurality of through holes.
JP2001365648A 2001-11-30 2001-11-30 Power semiconductor device Pending JP2003168769A (en)

Priority Applications (1)

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Country Link
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