JP2003167680A - Disk device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a disk device provided with a data buffer and an error detecting function by means of a CRC (Cyclic Redundancy Check), which can maintain the interchangeability of control software with the disk device which is not added with any CRC without needing any special memory. <P>SOLUTION: The data buffer is provided with an error detection code storage area, and the storage location of data and the error detection code are made correspond to each other for every sector, and the data storage area and the error detection code storage area are dividedly arranged. In this case, the data storage area and the error detection code storage area are continuously arranged for every sector unit. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk device that uses a data buffer for exchanging recording / reproducing data with a host device, and does not require a special memory when a CRC check function is added. The present invention relates to a disk device capable of maintaining compatibility of foamware for controlling the disk device.

[0002]

2. Description of the Related Art In a general disk device at present, it is called a data buffer in order to absorb a difference between a data transfer speed from a host device and a recording / reproducing speed of a recording disk and to shorten a response time as a cache. It has a semiconductor memory.

In the data buffer, the data storage position is managed with the same length as the sector length in the recording disk.
The sector length is generally 512 bytes.

For the purpose of improving the reliability of the data in the data buffer, CRC (Cy) for each sector is detected in order to detect an error in the stored data in the data buffer.
It is also widely practiced to add an error detection code such as cricRedundancy Code) to data.

An example of a disk device using such a CRC is an "electronic disk device" disclosed in Japanese Patent Laid-Open No. 10-214325. In this conventional technique, in order to store the CRC, a CR different from the memory storing the data is used.
It has a memory for storing C.

[0006]

The error detection technique based on CRC or the like described in the above-mentioned prior art is becoming indispensable for improving the reliability of the disk device. The logic for detecting an error by using such a CRC or the like and pointing out the error is generally realized by hardware.

However, the above-mentioned conventional technique has a problem in compatibility of control software of the disk device. The access to the recorded / reproduced data on the data buffer is normally performed by the control software of the disk device. However, a CRC is added and the sector and the CRC for the sector are linked and arranged as shown in FIG. Then, it is necessary to change the data length when managing the sectors in the data buffer to “sector length + error detection code length”, and the compatibility of the control software cannot be maintained as compared with the case where the CRC is not added. Because. Here, FIG. 8 is a schematic diagram of the arrangement of data and CRC in the data buffer according to the conventional technique.

Further, in the conventional technique disclosed in Japanese Patent Laid-Open No. 10-214325, since the CRC is stored in a memory different from the storage data, a dedicated memory for storing the CRC is required, which causes an increase in component cost. There was a point.

The present invention has been made to solve the above-mentioned problems of the prior art, and an object thereof is to provide a disk device having a data buffer and having an error detection function by CRC without requiring a special memory. , And to provide a disk device capable of maintaining compatibility of control software with a disk device to which CRC is not added.

[0010]

According to the present invention, an error detection code storage area is provided in a data buffer, and data storage positions and error detection codes are associated one-to-one on a sector-by-sector basis. The storage area and the error detection code storage area are arranged separately. At this time, both the data storage area and the error detection code storage area are continuously arranged for each sector.

[0011]

DETAILED DESCRIPTION OF THE INVENTION An embodiment according to the present invention will be described below with reference to FIGS. FIG. 1 is a configuration diagram of a magnetic disk device according to the present invention.

As shown in FIG. 1, a magnetic disk device 101 includes a magnetic recording disk 102 and a magnetic head 103.
, Spindle motor 104, head actuator 105, read / write channel 112 (hereinafter referred to as "RW
-CH ") and a microprocessor (hereinafter referred to as" M ").
PU ”) 110, work memory 111, and hard disk controller (hereinafter referred to as“ HDC ”) 113.
And a data buffer 114 and a motor control unit 115.

The magnetic recording disk 102 magnetically stores data, and the magnetic head 103 records / reproduces data on / from the magnetic recording disk 102. The spindle motor 104 is a motor for rotating the magnetic recording disk 102, and the head actuator 105 is a mechanism for supporting the magnetic head 103 and moving it in the radial direction of the magnetic recording disk 102.

The RW-CH 12 modulates data for magnetic recording and drives the magnetic head 103 at the time of recording data, amplifies the signal from the magnetic head 103 at the time of reproducing data, and outputs a digital value of "1" or "0". Discriminate.

The HDC 113 controls the format of data to be recorded on the magnetic recording disk 102 and the host device 102.
Connection and data transfer control, and data buffer 11
4 control is performed. The data buffer 114 is a place for temporarily storing data to be recorded / reproduced on / from the magnetic recording disk 102.

The MPU 110 is a device that controls the interpretation of commands from the host device 102 and the operation of other parts. The work memory 111 is an area for storing control information used by the MPU 110. Motor control unit 115
Drives the head actuator 105 to control the movement of the magnetic head 103 and the positioning to a fixed position.
In addition, the motor control unit 115 controls the spindle motor 104.
Is controlled to rotate at a constant speed.

The HDC 113 is an interface control unit (hereinafter, referred to as "HOST-IF") 1 with a host device.
21, a buffer control unit 122, a format control unit 123, and an error correction unit 124.

The HOST-IF 121 transmits / receives a command instructing a recording / reproducing operation and recording / reproducing data to / from the host device.

The buffer control unit 122 controls writing and reading of data in the data buffer 114. further,
The buffer control unit 122 also controls data transfer between the HOST-IF 121 and the data buffer 114, data transfer between the format control unit 123 and the data buffer 114, and data transfer between the error correction unit 124 and the data buffer 114. . In the present embodiment, the buffer controller 122 and the data buffer 114 will be described as being connected by a 2-byte width data bus.

In the disk device according to the present invention, the CRC detection unit 131 and the DATA / C are provided in the buffer control unit 122.
An RC address management unit 132 is provided. CRC detector 13
Reference numeral 1 is a circuit for detecting the occurrence of a data error in the data buffer 114. The CRC detection unit 131 adds a 2-byte CRC code to each 512-byte data when writing data to the data buffer 114. CRC
The detection unit 131 detects a data error by a CRC code when reading data from the data buffer 114. The CRC code used here may be a technique known as a general technique.

DATA / CRC address management unit 132
Is a circuit for managing the storage addresses of DATA and CRC in the data buffer 114.

The format control section 123 is a section for controlling the sector format of the recording / reproducing data to / from the magnetic recording disk 102, and at the time of data recording, the sector start code for data from the host device and the code management for data error correction. Information is added and sectors are detected and management information is separated during reproduction. The sector format will be described later.

The error correction unit 124 generates an error detection / correction code at the time of recording data, and detects the presence / absence of an error in the reproduced data and corrects the error at the time of reproducing the data. This error correction unit is related to an ECC code added after the data in the sector, as described later.

Next, the sector format of the recording / reproducing data will be described with reference to FIG. FIG. 2 is a schematic diagram for explaining the sector format of recorded / reproduced data.

Generally, the magnetic disk device 101 records data on the magnetic recording disk 102 concentrically. This circle is called a recording track. This recording track is divided into a plurality of units called “sectors”, and the magnetic disk device 101 records and reproduces data in units of these sectors.

The structure of this sector (called a format) is as shown in FIG. Sector is PL
OSSYNC, BYTESYNC, DATA, ECC and P
And AD. There is a buffer area called GAP between the sectors. PLOSYNC has a length of 10 bytes and is a code used for timing synchronization during reproduction on the RW-CH 112. DATA has a length of 512 bytes and is recording data sent from the host device. DATA is stored in the data buffer 114 before writing to the magnetic recording disk 102 or immediately after reading from the magnetic recording disk 102. BY
TESYNC is a 1-byte code, which is a 1-byte code for indicating the beginning of DATA. ECC is
It has a length of 40 bytes and is information for DATA error detection and correction. PAD is a part for adjusting the sector length.
There is an area called GAP between the sectors, and it prevents the subsequent sectors from being destroyed due to variations in the recording positions of the sectors.

Next, the arrangement of DATA and CRC in the data buffer 114 of the present invention will be described with reference to FIG. FIG. 3 illustrates the DAT in the data buffer 114 of the present invention.
It is a schematic diagram of arrangement | positioning of A and CRC.

The data buffer 114 is divided into two areas, a data storage area and a CRC storage area. Data of 512 bytes in length is continuously stored in the data storage area, and CRC is also stored in the CRC storage area.
Codes are stored consecutively. The DATA storage order and the CRC code storage order are the same, and C of DATA # 0
The RC code is CRC # 0. Below, DATA # 1 and C
RC # 1, DATA # 2 and CRC # 2 are in one-to-one correspondence with each other. The arrangement of the data storage area and the CRC storage area of the prior art shown in FIG. 8 is different, and such arrangement is a feature of the present invention.

Next, referring to FIGS. 4 and 5, DATA /
The configuration and operation of the CRC address management unit 132 will be described.
FIG. 4 is a diagram illustrating the configuration of the DATA / CRC address management unit 132 according to this embodiment. FIG. 5 is a timing chart explaining the operation of the DATA / CRC address management unit 132 according to this embodiment.

DATA / CRC address management unit 132
Is a data counter 140, an address control unit 141, a data pointer 142, a sector head pointer 143, and a CRC area head pointer 14 as shown in FIG.
4, a CRC address calculation unit 145, and an address selection circuit 146.

The data counter 140 is a counter for managing the data length in sector units. Address control unit 1
Reference numeral 41 controls the address selection circuit 146 according to the value of the data counter 140, and the DATA storage address and CRC
Switch to the code storage address. Also, DATA / C
The RC address management unit 132 stores the content of the data pointer 142 in the sector head pointer 143 at the head of the sector, and also controls the storage timing.

The data pointer 142 generates a DATA storage address. The sector head pointer 143 is a pointer for holding the storage address in the data buffer of the DATA part head for each sector. The CRC area head pointer 144 is a pointer for holding the head address of the CRC storage area in the data buffer.

The CRC address calculation unit 145 determines each DAT.
This is a circuit for calculating an address for storing the CRC code corresponding to the A section, and performs the address calculation shown in (Equation 2) below.

That is, the sector length is 512, and i
The numbered sector is calculated by i = (sector start pointer / 512), where the first sector starts from 0. Besides, since the CRC storage area is 2 bytes, 2
When multiplied by, the relative address from the CRC area start pointer is obtained.

Therefore, the CRC storage address is the following (Equation 2) in which the CRC area start pointer is added thereto.

CRC storage address = (sector start pointer / 512) × 2 + CRC area start pointer ... (Equation 2) In FIG. 4, when the CRC area start pointer 144 is C and the sector start pointer 143 is P , CRC
It is shown that the address calculation unit 145 generates an address called Y and outputs it as a data buffer address.

The change in the value of each part of the DATA / CRC address management part 132 is shown in FIG.

From time t11, reading or writing of the DATA portion of one sector from the data buffer 114 is started.

In this embodiment, since data is transferred by 2 bytes between the data buffer 114 and the HDC 113, the data count 140 and the data pointer 14 are set.
The value of 2 is incremented by 2 for each transfer. The sector head pointer 142 stores the value of p, which is the storage address of the sector head. Here, the value of p is 0,5
Note that the values are integer multiples of 12,1024, ..., And 512.

C is a CRC area head pointer.

Thus, from time t11 to t12,
The values of the data counter 140 and the data pointer increase by 2 and the sector head pointer 142 has a constant value. Then, at time t12, the last 2 bytes of the DATA portion are transferred.

From time t11 to time t13, the value of the data pointer 142 is output as it is as the data buffer address 146. Then, from time t13 to time t
At 14, the CRC storage address is calculated and output as the data buffer address 146. This time t1
From 3 to time t14, a fixed value is set and the value is not increased. As a result, from time t13 to time t14
During this period, the CRC storage area corresponding to the sector can be accessed.

Then, at the next t14, the storage address at the beginning of the sector increases by 512, so that after that,
The processing of the next sector and the CRC storage area is performed in the same manner.

Next, the data buffer access processing executed by the buffer controller 122 will be described with reference to FIGS. 6 and 7.

First, the procedure of the writing process will be described with reference to the flowchart of FIG. FIG. 6 shows data and CR in the data buffer executed by the buffer control unit 122.
It is a flowchart which shows the procedure of the writing process of C.

Before the memory writing process, the MPU
Sets the start address for storing data in the data pointer 142, and sets the start address of the CRC area in the CRC area start pointer 144.

First, the DATA / CRC address management unit 1
As the initialization of 32, the data counter 140 is set to "O" and the value in the data pointer 142 is copied to the sector head pointer 143 (step 161).

Next, the CRC detector 131 is initialized so that the previous calculation result does not affect the new calculation (step 162).

Next, 2 bytes of data are transferred to the data buffer 1
14 (step 163). Further, the data is put into the CRC detection unit 131 to perform the CRC calculation (step 164). Then, step 163 and step 164 are repeated for 512 bytes (step 16
5) At the end, 512 bytes of data are written in the data buffer 114, and the CRC for this 512 bytes of data is calculated.

Data of 512 bytes is transferred to the data buffer 1
After writing to 14, the calculated CRC 2 bytes are
The data is written in the address designated by the C address calculation unit 145 (step 166). Steps 162 to 166 above
Up to this, the data and CRC for one sector are written, and these are repeated until the writing of the predetermined number of sectors is completed (step 167).

Next, the procedure of the reading process will be described with reference to the flowchart of FIG. FIG. 7 shows data and CR in the data buffer executed by the buffer control unit 122.
It is a flow chart which shows the procedure of the reading processing of C.

Also here, similarly, before the memory read processing, the MPU sets the start address for storing data in the data pointer 142 and sets the start address of the CRC area in the CRC area start pointer 144. And

First, the DATA / CRC address management unit 1
As the initialization of 32, the data counter 140 is set to "O" and the value in the data pointer 142 is copied to the sector head pointer 143 (step 171).

Next, the CRC detector 131 is initialized so that the result of the previous calculation does not affect the new calculation (step 172).

Next, 2 bytes of data are transferred to the data buffer 1
It is read from 14 (step 173). Further, the data is put into the CRC detection unit 131 to perform the CRC calculation (step 174).

Then, step 173 and step 174
Is repeated for 512 bytes (step 175), 512
Reads bytes of data from the data buffer 114,
The CRC for this 512-byte data is calculated.

Data of 512 bytes is transferred to the data buffer 1
After reading from 14, the CRC 2 bytes are read from the address designated by the CRC address calculation unit 145 (step 176), and the read CRC is compared with the calculated CRC (step 177). If the read CRC and the calculated CRC match, it is determined that the read data has no error, and the read processing is continued.

If the read CRC and the calculated CRC do not match, it is determined that the read data has an error, and the read process is abnormally terminated.

In steps 172 to 177 above,
Data for one sector and CRC are read out, and these are repeated until the reading of a predetermined number of sectors is completed or abnormal termination (step 178).

As described above, in the disk device of the present invention, as shown in FIG. 3, since the DATA storage area and the CRC code storage area are separated, the DATA storage area has the same data length as that on the recording disk. Because it can be managed, C
The data buffer can be managed as in the case where the RC code is not added. Therefore, the compatibility of the control software of the disk device can be maintained.

In this embodiment, the data pointer 1
42 and the sector head pointer 143 are provided.
If the head of the section is limited to a multiple of 512, the CRC code storage area can be calculated even if the value of the data pointer instead of the value of the sector head pointer is input to the CRC address calculation section 145. Therefore, with such a configuration, the sector head pointer becomes unnecessary and the circuit can be simplified.

[0062]

According to the present invention, in a disk device having a data buffer and having an error detection function by CRC, no special memory is required and compatibility of control software with the disk device without CRC is maintained. It is possible to provide a disc device that can do this.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a magnetic disk device according to the present invention.

FIG. 2 is a schematic diagram illustrating a sector format of recorded / reproduced data.

FIG. 3 is a schematic diagram of the arrangement of DATA and CRC in the data buffer 114 of the present invention.

FIG. 4 is a diagram illustrating a configuration of a DATA / CRC address management unit 132 according to the present embodiment.

FIG. 5 is a timing chart explaining the operation of the DATA / CRC address management unit 132 according to this embodiment.

FIG. 6 is a flowchart showing a procedure of a process of writing data into a data buffer and a CRC, which is executed by a buffer control unit 122.

FIG. 7 is a flowchart showing a procedure of a process of reading data into a data buffer and a CRC, which is executed by a buffer control unit 122.

FIG. 8 shows data and C in a data buffer according to the related art.
It is a schematic diagram of arrangement | positioning of RC.

[Explanation of symbols]

101 ... Magnetic disk device, 102 ... Magnetic recording disk, 1
03 ... magnetic head, 104 ... spindle motor, 105
... head actuator, 110 ... microprocessor, 111 ... work memory, 112 ... read / write channel, 113 ... hard disk control section, 114 ... data buffer, 115 ... data control section, 121 ... host interface control section, 122 ... buffer control section, 123
... format control unit, 124 ... error correction unit, 131 ...
CRC detector 127, DATA / CRC address manager 140, data counter 141, address controller 142, data pointer 143, sector start pointer 144, CRC area start pointer 145, CR
C address calculator, 146 ... Address selection circuit.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G11B 20/18 544 G11B 20/18 544Z F term (reference) 5B065 BA01 CA12 CC08 CE12 EA03 5D044 AB01 BC01 CC05 DE12 DE69 EF03 FG10 HH07 HL02

Claims (3)

[Claims] 1. A disk device for temporarily storing the recording / reproducing data in a data buffer when exchanging the recording / reproducing data with a host device, comprising a data buffer control means for controlling the data buffer. The control means includes an error detecting means for detecting an error in the recording / reproducing data stored in the data buffer, and an error detecting means for storing the error detected by the error detecting means in the data buffer as the error detecting information. And a means for controlling the data buffer, wherein the recording / reproducing data and the error detecting information are divided and arranged. 2. A disk device for temporarily storing the recording / reproducing data in a data buffer when exchanging the recording / reproducing data with a host device, comprising a data buffer control means for controlling the data buffer. The control means includes an error detecting means for detecting an error in the recording / reproducing data stored in the data buffer, and an error detecting means for storing the error detected by the error detecting means in the data buffer as the error detecting information. This disk device records / reproduces the recording / reproducing data in sector units, and the error detecting information storing unit stores the error detecting information in each sector unit. The recording and reproducing data for each sector unit and the sector And said error detection information for each position, the disk apparatus characterized by disposing each in succession. 3. The sector unit is M bytes, and the size of the error detection information for each sector unit is
N bytes, the relative address of the beginning of the sector of the recording / reproducing data from the beginning of the storage area of the recording / reproducing data in bytes, DP, the beginning address of the storage area of the error detection information in bytes , CHP, when the relative address of the error detection information from the beginning of the storage area for the error detection information is set to CP in byte units, the relative address CP of the error detection information is as follows ( The disk drive according to claim 2, wherein the disk drive is given by equation (1). CP = (DP / M) × N + CHP (Equation 1)