JP2003162412A - Power-saving circuit for cpu - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power-saving circuit for a CPU (central processing unit) capable of controlling power saving state/full operation state by the CPU itself and at restarting, when restarting without delays in time. <P>SOLUTION: A wait signal instructing a wait state is written in the MSB (most significant bit) of a register 3 by a CPU 1. A wait time for maintaining the wait state is written in bits which excludes the MSB of the register 3 by the CPU 1. A counter 13 and a comparison circuit 6 measure the wait time and outputs a signal releasing wait, at the time when the wait time has elapsed. An AND gate 4 outputs a signal making the CPU 1 be in the wait state, when the wait signal is written and outputs the wait signal making the CPU 1 release from the wait state, when the signal releasing the wait is output from the comparison circuit 6. Outputs from the AND gate 4 are input to a wait terminal 'Wait' of the CPU 1 via a delay flip-flop D FF 15. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power saving circuit for a CPU (central processing unit) such as a microprocessor, which reduces power consumption.

[0002]

2. Description of the Related Art Conventionally, as a method for saving power of a CPU, a method of gating a clock pulse of the CPU or a PLL (Phase) for generating the clock pulse of the CPU
A method of controlling a Locked Loop circuit to slow down the frequency of a clock pulse is known. However, the method of gating the clock pulse is effective in terms of power saving because the CPU is completely stopped, but C
Since the operation of the PU itself is stopped, it is necessary to release the gate from the outside when restarting, and a circuit for gate control is required separately. On the other hand, in the method of slowing the frequency of the clock pulse, since the CPU itself is in the active state, the CPU itself can control the PLL circuit at the time of restart to restore the frequency of the clock pulse to the original value. Is an analog circuit,
There is a drawback that it takes time for the frequency of the clock pulse to return to its original value.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in consideration of such circumstances, and its purpose is to provide a CPU.
Without completely shutting down
It is an object of the present invention to provide a power saving circuit for a CPU, which can control the power saving state / full operation state by the PU itself and can be restarted without delay when restarting.

[0004]

The present invention has been made to solve the above-mentioned problems, and the invention according to claim 1 is provided with a weight terminal, and a control signal applied to the weight terminal is provided. In a power saving circuit that reduces the power consumption of a CPU that enters a power saving state based on a wait state, a first storage unit in which a wait signal indicating a wait state is written by the CPU, and a wait state by the CPU And a second storage unit in which a wait time for holding is stored, time measuring means for measuring the wait time and outputting a wait release signal when the wait time has elapsed, and a wait signal for the first storage unit. Is written into the CPU, the CPU is placed in a wait state, and the CPU waits when the wait release signal is output from the time measuring means. A power-saving circuit of the CPU, characterized by comprising a control circuit for releasing the state.

According to a second aspect of the present invention, in the power-saving circuit of the CPU according to the first aspect, the CPU has a release terminal to which a release signal for releasing a wait state is applied, and the control circuit releases the release signal. When the release signal is applied to the terminal, the wait state of the CPU is forcibly released.

According to a third aspect of the present invention, in the power saving circuit of the CPU according to the second aspect, the CPU has a "0" detection circuit for outputting a detection signal when the wait time is "0", When the detection signal is output from the "0" detection circuit, the control circuit puts the CPU in a wait state and continues the wait state until a release signal is applied to the release terminal.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a power saving circuit of a CPU according to the same embodiment. In this figure, reference numeral 1 is a CPU, 2 is a peripheral circuit of the CPU 1 and a memory which is read / written by the CPU 1. Reference numeral 3 is a register to which writing is performed by the CPU 1, whose MSB (most significant bit) is output to the AND gate 4 as a wait mode bit WMB, and bits other than MSB are wait cycle data WC.
It is output as D to the first input terminals of the ALL "0" detection circuit 5 and the comparison circuit 6.

On the other hand, the terminal 10 is a terminal to which a wait release signal WK is applied from the outside. Here, the wait release signal WK is a signal for instructing to forcibly release the wait state of the CPU 1, and is always a "1" signal, and becomes a "0" signal when instructing the wait release. The terminal 11 is a system clock pulse CL for driving the CPU 1.
This is a terminal to which K is applied. 13 is a clock pulse CL
It is a counter that counts up K, and its count output is applied to the second input terminal of the comparison circuit 6. The counter 13 is reset when the comparison circuit 6 outputs a "0" signal. The comparison circuit 6 is provided with the wait cycle data WCD output from the register 3 and the counter 1
The count output of 3 is compared, and when they are different, a "1" signal is output, and when they match, a "0" signal is output. The ALL "0" detection circuit 5 always outputs the "0" signal, and the wait cycle data WCD is ALL "0".
Only when, the "1" signal is output.

Reference numeral 14 is an OR gate, which is used for comparing circuit 6 and A.
The output of the LL "0" detection circuit 5 is ORed and output to the AND gate 4. AND gate 4 is a wait release signal W
K, output of OR gate 14, wait mode bit WM
The AND of B is taken and output to the D · FF (delay flip-flop) 15. The D / FF 15 reads the output of the AND gate 4 at the timing of the clock pulse CLK,
Output to the wait terminal Wait of CPU1.

Here, the weight terminal Wait is CP
This is a terminal for putting U1 in the wait state. When a "0" signal is applied, CPU1 operates normally, but "1"
When the signal is applied, the CPU 1 enters the wait state. C
When PU1 enters the wait state, the clock is internally gated, new events do not occur, and power consumption is reduced.

Next, the operation of the above circuit will be described. First, when the CPU 1 is in the normal operating state, the register 3
"0" is written in the MSB of the. As a result, the wait mode bit WMB becomes "0", and the AND gate 4
Output becomes "0", and the output of the D / FF 15 becomes "0". As a result, the wait terminal Wait of the CPU 1
The 0 "signal is applied, and the CPU 1 enters the wait release state (normal state).

Next, when the CPU 1 shifts to the power saving state for a certain time (a certain clock pulse cycle), the CPU 1
In register 3 as the wait mode bit WMB
1 "and the cycle number of the clock pulse corresponding to the power saving time are written as the wait cycle data WCD. Also, the counter 13 is reset (not shown). As the wait cycle data WCD, the predetermined cycle number is written from the register. When output, at this time, the count output of the counter 13 is "0", so that the output of the comparison circuit 6 becomes a "1" signal, and this "1" signal is transmitted through the OR gate 14 to the second gate of the AND gate 4. It is applied to two input terminals. The "1" signal of the wait mode bit WMB is applied to the third input terminal of the AND gate 4. Therefore, assuming that the wait release signal WK is the "1" signal, the output of the AND gate 4 becomes the "1" signal.
1 "signal is DFF by the next clock pulse CLK
It is read by 15, and applied to the weight terminal Wait of the CPU 1. As a result, the CPU 1 enters the wait state.

Next, when the count of the counter 13 advances and its count output coincides with the wait cycle data WCD, the output of the comparison circuit 6 becomes a "0" signal. As a result, the output of the OR gate 14 becomes the "0" signal, and the output of the AND gate 4 also becomes the "0" signal. As a result, the next clock pulse CLK causes the "0" signal to change to DFF1.
5, and applied to the wait terminal Wait of the CPU 1 to release the wait state of the CPU 1. CPU
1 receives the release of this wait state, and MS of register 3
B is set to "0". Further, when the output of the comparison circuit 6 becomes the "0" signal, the counter 13 is reset.

When the CPU 1 is in the wait state, the wait release signal WK applied to the terminal 10
Is a "0" signal, the output of AND gate 4 is "0".
It becomes a signal, therefore the output of DFF15 is "0".
It becomes a signal, and the wait state of the CPU 1 is released.

Next, when the CPU 1 shifts to the power saving state for a long time, the CPU 1 writes "1" as the wait mode bit WMB and "0" as the wait cycle data WCD in the register 3. . When "0" is output as the wait cycle data WCD,
The output of the ALL "0" detection circuit 5 becomes a "1" signal, and this "1" signal is passed through the OR gate 14 and the AND gate 4
Is supplied to. As a result, the wait release signal WK
When set to 1 ”, the output of the AND gate 4 becomes“ 1 ”,
Therefore, the output of DFF15 becomes "1" and CP
U1 is in a wait state. This wait state continues until a "0" signal is applied as a wait release signal WK from the outside.

When the wait release signal WK becomes a "0" signal, the output of the AND gate 4 becomes a "0" signal, which causes the output of the D / FF 15 to become a "0" signal and the CPU
The wait state of 1 is released. Upon receiving the release of the wait state, the CPU 1 writes the "0" signal in the MSB of the register 3.

In the circuit described above, the register 3 is a CP
U1 is mapped to a directly accessible area. As a result, the CPU 1 can select to insert the weight constantly according to the load to be processed, and can easily save power according to its own judgment. For example, when the CPU is used in a telephone, it is possible to judge when the CPU is busy depending on the operating state of the CPU, such as: busy when there is an incoming call, busy when making a call, and idle when waiting for reception. Is possible. Then, according to the above embodiment, it is possible to immediately enter the power saving state at the beginning of the code in the reception waiting state and immediately return to the normal state when there is an incoming call. Such a state change can be controlled by a microcomputer that externally monitors the entire system, but the above-described embodiment is not limited to such an easy-to-understand example, and the low power consumption is achieved by an internal state transition. It is possible to control the power state.

[0018]

As described above, according to the present invention, the first storage unit in which the wait signal for instructing the wait state by the CPU is written, and the second wait time in which the wait state for holding the wait state by the CPU is written. And a time measuring means for measuring the wait time and outputting a wait release signal when the wait time elapses, and when the wait signal is written in the first memory CP
Since the CPU is provided with a control circuit that puts U into a wait state and releases the wait state of the CPU when the wait release signal is output from the time measuring means, the power saving state / full operation state can be controlled by the CPU itself. At the same time, the effect of being able to restart without delay at the time of restart is obtained. As a result, power saving can be realized with a simple circuit configuration even if the CPU itself does not have the sleep power down function.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a power saving circuit of a CPU according to an embodiment of the present invention.

[Explanation of symbols]

1 ... CPU, 3 ... register, 4 ... AND gate, 5 ... A
LL “0” detection circuit, 6 ... Comparison circuit, 10 ... Terminal, 13
... counter, 14 ... OR gate, 15 ... DFF.

Claims (3)

[Claims] 1. A power-saving circuit comprising a weight terminal, wherein the CPU is in a power-saving state in a wait state based on a control signal applied to the weight terminal. A first storage unit in which a wait signal for instructing a state is written, a second storage unit in which a wait time for holding the wait state by the CPU is written, and a time point when the wait time is measured and the wait time elapses. And a time measuring means for outputting a wait canceling signal, and when the wait signal is written in the first storage section, the CPU is put in a wait state, and when the wait canceling signal is outputted from the time measuring means, A power saving circuit for a CPU, comprising: a control circuit for canceling the wait state. 2. A release terminal to which a release signal for releasing the wait state is applied from the outside, and the control circuit forcibly releases the wait state of the CPU when the release signal is applied to the release terminal. The power saving circuit for a CPU according to claim 1, wherein 3. The control circuit has a “0” detection circuit that outputs a detection signal when the wait time is “0”, and the control circuit outputs the C signal when the detection signal is output from the “0” detection circuit.
3. The power saving circuit for a CPU according to claim 2, wherein PU is placed in a wait state, and the wait state is continued until a release signal is applied to the release terminal.