JP2003158429A - Class-d power amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a class-D power amplifier which is suitable for a super woofer composed of inexpensive discrete components. SOLUTION: The class-D power amplifier 10 is provided with output FET drive circuits 1 and 2 which drive between positive and negative power sources with switching input signals S+/S-, a bootstrap circuit 4, and an output LPF 3 and further provided with an additional circuit 11 composed of a high- dielectric-strength PNP bipolar transistor Q3 which performs voltage-current converting operation for a switching voltage output, generated by passing S+ through a logic circuit Q9, in an invariably active area, a high-speed PNP bipolar transistor Q4, a Zener diode D2 which is connected between its emitter and an output end V0 on the source side of a Q1, a capacitor C1 and a diode D3 which are connected between an emitter of the Q4 and the ground in series, a resistance R5 which is connected between the emitter of the Q4 and the ground in parallel to a capacitor C1 and a diode D3 which are in series, a resistance R5 which is connected to C1 in parallel, and a diode D1 which is connected between the bases of a Q5 and a Q6 of the drive circuit 1 of the D2 and the Q1.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a class D power amplifier, and more particularly to an output FET drive circuit of a class D power amplifier used in a super woofer or the like. 2. Description of the Related Art An output FET (Field) of a conventional audio class D power amplifier used in a super woofer or the like.
Effect Transistor) drive circuits include (A) a 2D power amplifier as shown in the class D power amplifier 20 in the circuit diagram of FIG.
Each output FET has a complementary configuration of a P-channel output FET Q0 and an N-channel output FET Q2, and outputs voltages of general-purpose CMOS logic circuits Q9 and Q10 to which a plus-side switching input signal S + and a minus-side switching input signal S- are respectively input. The NPN transistor Q5 and the PNP transistor Q6 of the current amplifying transistor, the NPN transistor Q7 and the PNP transistor Q8 are alternately driven to drive the P channel output FETs Q0 and N
A configuration for switching by charging and discharging the charge of each gate G of the channel output FET Q2, and (b) D in the circuit diagram of FIG.
As shown in the class power amplifier 30, an N-channel output FET Q1 is also used on the plus side, and a bootstrap circuit 4 composed of a capacitor C2 and a diode D4 produces a voltage higher than the plus power supply + V _DD , and this voltage The high-voltage high-speed switching element Qx is turned on / off by the output voltage of the general-purpose CMOS logic circuit Q9 which receives the plus-side switching input signal S +, and the NPN on the gate G1 side of the N-channel FET Q1 of the plus-side output FET
A configuration has been adopted in which the transistor Q5 and the PNP transistor Q6 are driven to charge and discharge the gate G1 of Q1 to perform switching. [0003] Reference numeral 3 denotes an output low-pass filter (output LPF), _{V L} is the power supply for the logic circuit Q9, Q10, _{V B} is the power of the bootstrap circuit 4. The voltage amplitude of the output terminal voltages of the output FETs Q1 and Q2 in FIG. 5 (the source voltage of the positive side output FET Q1) is ± several tens of volts (up to ± 50 V in a large scale super woofer), and Qx is -V _SS to + V
Since _{DD +} V must swing at high speed very large voltage to _B it is there is a need to a high-voltage high-speed switching element. [0005] The problem of the output FET drive circuit of the class D power amplifier 20 described in (a) is that the PO
When comparing the N-channel / P-channel of the WER MOS FET, the P-channel is generally more difficult to improve the performance such as the ON resistance, the switching speed, the inter-electrode capacitance, and very expensive (N-channel having the same current capacity). Channel M
(Two to three times the price compared to the OS FET). Therefore, if the output FET is configured to have a complementary configuration, the output FET drive circuit can be simplified, but the overall configuration becomes expensive. The problem of the output FET drive circuits 1 and 2 of the class D power amplifier 30 described in (b) above is that the N-channel is used for the plus side output FET Q1, so that the overall cost can be suppressed. The output terminal voltage (the source voltage of the plus side output FET Q1) is changed to + _VDD voltage (the plus side F
In order to saturate the drain voltage) of ETQ1 _{+ V D D}
It is necessary to generate an even higher voltage at the gate G1 of the plus side output FET Q1, and the bootstrap circuit 4
The circuit configuration becomes complicated due to the addition of the above. In this regard, the output FET drive circuit including the Qx in FIG. 5 is currently integrated into a IC and is very expensive. Since it is not provided as a class D power amplifier for audio, unnecessary circuits are also added. It is not very suitable for use as a class D power amplifier for super woofers. On the other hand, if the drive circuit of FIG. 5 is composed of discrete components, it is generally difficult to manufacture the high-voltage high-speed element Qx with a bipolar transistor, resulting in a complicated circuit and the use of expensive elements, resulting in a stable operation. It is not preferable in terms of performance and cost. The present invention has been made in view of the above problems of an output FET drive circuit of a class D power amplifier used in a super woofer and the like, and is a low-cost discrete electronic component without using a high withstand voltage high speed element Qx. To provide an output FET drive circuit. SUMMARY OF THE INVENTION The present invention provides a + power supply + V
Positive N-channel output F with drain connected to _DD
And ETQ1, - power supply _-V source is connected to the negative side N-channel output FETQ2 the _SS, the plus-side N-channel output FETQ1 and negative side N-channel output F
The gates G1 and G2 of the ETQ2 are connected to the positive switching input signal S + or the negative switching input signal S.
-Plus output F comprising NPN / PNP bipolar transistors Q5, Q6 respectively driven by
In a class D power amplifier including an ET drive circuit 1 and a negative output FET drive circuit 2, a switching voltage output that passes a positive switching input signal S + to a logic circuit Q9 is supplied to the positive output FET drive circuit 1. A high-voltage PNP bipolar transistor Q3 which constantly performs a voltage-current conversion operation in an active region; a high-speed NPN bipolar transistor Q4 having a base connected to the collector of the high-voltage PNP bipolar transistor Q3 and supplied with a bias voltage by a bias resistor R4;
A Zener diode D2 connected between the emitter of the high-speed NPN bipolar transistor Q4 and the source-side output terminal of the plus-side N-channel output FET Q1, and a capacitor C1 connected in series between the emitter of the high-speed NPN bipolar transistor Q4 and ground; And diode D
3 and a resistor R5 connected in parallel with the capacitor C1.
The Zener diode D2 and the NPN / PNP
The object described above is achieved by providing a class D power amplifier 10 comprising a diode D1 connected between the bases of bipolar transistors Q5 and Q6. An embodiment of a class D power amplifier according to the present invention will be described with reference to the drawings. FIG. 1 is an example of a circuit diagram of a class D power amplifier according to the present invention. FIG. 2 is a circuit diagram showing the flow of current at the moment when the plus-side output N-channel FET Q1 of the class D power amplifier changes from ON to OFF. FIG. 3 is a circuit diagram showing a current flow when the plus-side N-channel output FET Q1 of the class D power amplifier is OFF and the minus-side N-channel output FET Q2 is ON. First, the present invention is based on the premise that the class D power amplifier 30 shown in FIG. 5 described above is used, and another additional power supply is made for a drive circuit for the positive side N-channel output FET Q1, and By combining the breakdown voltage PNP bipolar transistor Q3 and the (low breakdown voltage) general-purpose high-speed NPN bipolar transistor Q4, the gate drive circuit of Q1 is configured without using the high breakdown voltage high-speed element Qx. More specifically, as shown in FIG. 1, the class D power amplifier 10 according to the present invention comprises the class D power amplifier 3 shown in FIG.
0 Similarly, the positive side N-channel output FETQ1 having a drain connected to the + power supply _{+ V DD,} - power supply _-V source connected to _SS negative side N-channel output FETQ
2 and the gates G1, G2 of the plus-side N-channel output FET Q1 and the minus-side N-channel output FET Q2.
Output FET drive circuit 1 and NPN / PNP bipolar transistors Q7, Q8, which comprise NPN / PNP bipolar transistors Q5, Q6 of current amplifying transistors, respectively, which are driven by the plus side switching input signal S + or the minus side switching input signal S-. The output FET drive circuit 2 on the negative side, the bootstrap circuit 4, and the output LPF 3
In addition to the above, the additional circuit 11 surrounded by a broken line, that is, the plus side switching input signal S + is supplied to the plus side output FET drive circuit 1 by the CMOS.
Means for dividing the switching voltage output passed through the logic circuit Q9 by the resistors R1 and R2 and inputting the divided voltage to the base, and a general-purpose high-breakdown-voltage PNP bipolar transistor Q3 which always performs a voltage-current conversion operation in the active region by means of the resistor R3 inserted in the emitter; The high voltage PNP bipolar transistor Q3
The collector is connected to the base, and a bias voltage is applied by a bias resistor R4.
A PN bipolar transistor Q4; an emitter of the high-speed NPN bipolar transistor Q4;
Zener diode for connecting auxiliary voltage generated between the output terminal V ₀ which source side of channel output FET Q1 D2
And an auxiliary power supply capacitor C connected in series between the emitter of the high-speed NPN bipolar transistor Q4 and ground.
1 and a diode D3 for preventing auxiliary voltage discharge, a resistor R5 connected in parallel with the capacitor C1, and a Q6 for preventing saturation of Q6 connected between the Zener diode D2 and the bases of the NPN / PNP bipolar transistors Q5 and Q6. And an additional circuit 11 composed of a diode D1 for the purpose. The operation of this circuit will be described below. It is premised that the plus side switching input signal S + and the minus side switching input signal S- are level-shifted in advance to voltages suitable for the respective MOS logic circuits Q9 and Q10 and input. Is done. In the circuit of FIG. 1, a normal output is obtained by pulse input of S + and S− having opposite phases. The switching pulses of the input signals S + and S- are simultaneously output of Q1 and Q2.
There is provided a preset timing difference so that N does not occur. The switching of the negative side N-channel output FET Q2 is performed by the CMOS logic circuit Q
The operation is performed by alternately turning on / off the current amplifying transistors Q7 and Q8 of the drive circuit 2 by the voltage output of 10. On the other hand, the positive side N-channel output FET Q1
In the switching operation of (1), first, the output pulse voltage of the logic circuit Q9 is converted into a current pulse by Q3. This current pulse is level-shifted by R4 to a voltage based on the emitter voltage of Q4, and turns ON / OFF Q4. Further, R1, R2, and R3 have the output voltage of Q9 of H /
Regardless of the value of L, Q3 operates in the active region. Specifically, when the output of Q9 is L and the collector current of Q3 is maximum, the voltage between the emitter and collector of Q3 is sufficiently open. In addition, even when the output of Q9 is H, the collector current of Q3 is not set to 0 (setting example: When the output of Q9 is H, the collector current of Q3 is 0.1 mA, and when the output of Q9 is L, the collector current of Q3 is Q3). Is set to 2.0 mA.
If R4 is set to 1KΩ, the output of Q9 is L and Q3
The emitter-base voltage is 2.0 mA × 1 KΩ ≧ 0.6
V, so Q4 is ON / O by Q9 output
FF is possible. ). The reason for operating the above-mentioned Q3 in the active region is that it is necessary to use a high breakdown voltage transistor having a low switching speed for the Q3, but a general transistor having a low switching speed has a high reaction speed when operated in the active region. It is because it can secure enough. By the way, a low-voltage high-speed switching transistor which does not decrease in speed even when saturated is used for Q4. Such low-voltage transistors can be obtained relatively inexpensively. It is conceivable to use a low-speed NPN high-breakdown-voltage transistor in the active region by the same method and use it in the conventional circuit 30 shown in FIG. 5, but this method always leaves the collector-emitter voltage in the ON state. Need to
It is not practical because the voltage of the gate G1 of the positive side N-channel output FET Q1 cannot be sufficiently reduced and the driving force is weak due to the constant current operation and the speed cannot be increased. Next, in FIG. 2, the emitter voltage of Q4 needs to be sufficiently lower than the source voltage of Q1 (in this case, + _VDD ) when turning off Q1 from ON. This is because the current conversion circuit by the logic circuits Q9 and Q3 is a circuit in which + _VDD is a higher voltage, and Q
This is because 3 is not saturated. Emitter voltage of the Q4 from the output terminal voltage _{V 0} by Q1, Q2 D2, Cl, R
5, made by D3. When Q1 is ON, a current flows from the Q1 source to the Zener diodes D2, R5, and D3, and the voltage across R5 (source voltage of Q1 = + V _DD)
(A voltage obtained by subtracting a Zener voltage VZ of about 15 V from D2) to Cl (for example, 0.01 μF). Now, when the CMOS logic circuit Q9 changes from H to L
When the collector current of Q3 increases, a current flows from the base of Q4 to the emitter and C1 as indicated by arrow Y1, and Q4 turns ON. Since the collector of Q4 is connected to the base of Q6, Q6 rapidly discharges the gate charge of Q1 as indicated by arrows Y2 and Y3, so that Q1 changes from ON to OFF. Next, in FIG. 3, D1 is inserted for the purpose of preventing Q6 from saturating after Q6 discharges the charge of Q1 (the reason for not saturating is the same as described above). After this (this time delay is due to the previously set timing difference between the switching input signals S + and S−), the negative-side N-channel output FET Q2 turns from OFF to ON, and the output terminal voltages V1 of Q1 and Q2. ₀ is the _{-V SS} from _{+ V DD.} Q4 is still ON at this point
However, since D3 is OFF, its base current passes through the emitter of Q4 and D2
Flowing through the drain further _{-V SS} of Q2 from. That is,
The power charged to Cl is used only at the moment when the output is changed from H to L, and once the output becomes L, the power consumption is only discharge by R5. Therefore, the power consumed here is extremely small, and the size of the device can be reduced. If D3 is absent (short), the charge stored in Cl is rapidly discharged while the output is L, which is not preferable in terms of power saving. To switch Q1 from OFF to ON, the minus side switching input signal S- is switched from L to H,
After Q2 is turned off from ON, the plus side switching input signal S + is switched from H to L and Q4 is turned on from OF
If the F, current flowing through the bootstrap circuit 4 from the power source V _B for bootstrapping by the resistor R10 Q5
Is turned on from off, and the gate of Q1 is charged, so that Ql is turned on and the source voltage of Ql rises. As the source voltage of Q1 increases, the output voltage of bootstrap circuit 4 increases. As a result, Q1 saturates, and the source voltage becomes + _VDD . As can be seen from the above, V is applied between the collector and the emitter of the high-speed NPN bipolar transistor Q4.
Since only the voltage of V ₀ −V _Z (the zener voltage of the zener diode D2) is applied from ₀ + V _B , V _B =
_10V, when the V Z = 15V, generally will be sufficient if more than a breakdown voltage 25V, is the high-speed NPN bipolar transistor of low breakdown voltage can be applied. Since the low-voltage high-speed element is widely used and generally inexpensive, a low-cost output FET drive circuit as a whole can be relatively easily constituted by discrete components. Since the power supply by the added capacitor C1 consumes almost no power except at the moment when the plus-side N-channel output FET Q1 is turned off, the power capacity of each element can be suppressed, and power saving and miniaturization can be achieved. . As described above, the class-D power amplifier according to the present invention has a plus-side N-channel output FET by combining discrete low-cost high-voltage PNP bipolar transistors and high-speed NPN bipolar transistors. Has an excellent effect that an inexpensive class D power amplifier that does not use a high-voltage high-speed element can be configured.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram example of a class D power amplifier according to the present invention. FIG. 2 is a circuit diagram showing a current flow at the moment when a plus-side output N-channel FET Q1 of the class D power amplifier is turned from ON to OFF. FIG. 3 is a diagram showing a case where the plus side N-channel output FET Q1 of the class D power amplifier is OFF and the minus side N-channel output FET
FIG. 10 is a circuit diagram showing a current flow when Q2 is in an ON state. FIG. 4 is a circuit diagram of a conventional class D power amplifier having a complementary configuration for audio. FIG. 5 shows two N-channel outputs F for conventional audio.
FIG. 3 is a circuit diagram of a class D power amplifier constituted by ET. [Description of Signs] 1, 2 Output FET drive circuit 3 Output LPF 4 Bootstrap circuit 10, 20, 30 Class D power amplifier C1 Auxiliary power supply capacitor Q0 P-channel output FET Q1 Positive N-channel output FET Q2 Negative N-channel Output FET Q3 High voltage PNP transistor Q4 (Low voltage) High speed NPN transistor Q5, Q6, plus current amplifier transistor Q7, Q8 Negative current amplifier transistor Q9, Q10 CMOS logic circuit Qx High voltage high speed switching element R1-R10 Resistance V ₀ output voltage _{V B} bootstrap circuit of the power supply _{V L} logic circuit power source D1 Q6 saturated preventing diode D2 zener diode D3 auxiliary voltage discharge preventing diode

Continuation of front page    F term (reference) 5J091 AA02 AA19 AA41 AA66 CA87                       FA07 HA08 HA09 HA10 HA17                       HA18 HA19 HA20 HA25 HA29                       HA33 HA39 KA24 KA42 SA05                       UW10                 5J500 AA02 AA19 AA41 AA66 AC87                       AF07 AH08 AH09 AH10 AH17                       AH18 AH19 AH20 AH25 AH29                       AH33 AH39 AK24 AK42 AS05                       WU10

Claims (1)

Claims: 1. A positive N-channel output FET having a drain connected to a positive power supply, a negative N-channel output FET having a source connected to a negative power supply, and the positive N-channel output FET. And negative side N-channel output FET
A class D power amplifier comprising: a plus side output FET drive circuit and a minus side output FET drive circuit including NPN / PNP bipolar transistors for driving each of the gates by a plus side switching input signal or a minus side switching input signal, respectively. A high withstand voltage PNP bipolar transistor which always performs a voltage-current conversion operation in a positive active region on a switching voltage output obtained by passing a plus side switching input signal through a logic circuit to the plus side output FET drive circuit;
A high-speed NPN bipolar transistor having a base connected to the collector of the NP bipolar transistor and supplied with a bias voltage by a bias resistor, and connected between an emitter of the high-speed NPN bipolar transistor and a source-side output terminal of the plus-side N-channel output FET; A Zener diode, a capacitor and a diode connected in series between the emitter of the high-speed NPN bipolar transistor and ground, a resistor connected in parallel with the capacitor, and a connection between the Zener diode and the base of the NPN / PNP bipolar transistor. A class D power amplifier comprising: a diode;