JP2003152044A - Semiconductor device and method for evaluating the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decide whether the surface state of a film to be polished of a semiconductor wafer is a level capable of meeting microminiaturization or density enhancement by rapidly and accurately measuring the surface state of the film to be polished of the wafer without breaking the wafer. SOLUTION: The method for evaluating the semiconductor device comprises a step of previously disposing a measuring pattern of the same configuration as that of the circuit pattern of a chip at an arbitrary place of the semiconductor wafer. The method further comprises a step of implanting the impurity similar to that of other chip in the measuring pattern so that the pattern becomes the one as shown in Fig. That is, the retracted amount (u) of the SiO2 film 27 of a field region F adjacent to the N-channel active region 26 in which an N-type impurity is implanted is different from the retracted amount (w) of the SiO2 film 27 adjacent to the P-channel active region 25 in which the P-type impurity is implanted. The method also comprises a step of measuring the rugged step difference amount of the surface layer of the measuring pattern by an SFM measuring unit. Thus, the rugged step difference amount of the semiconductor wafer in a production lot can be quality managed. The management of the rugged step difference amount after the CMP treatment can also be performed by the measuring pattern and the AFM measuring unit.

Description

Detailed Description of the Invention

[0001]

The present invention relates to element isolation (STI: Shallow Trunk) by an active region and a field region.
The present invention relates to a semiconductor device in which ench Isolation) is formed and covered with a surface film, and a method for evaluating the same, and more specifically, a slurry-like polishing agent is supplied to the pad surface to perform chemical mechanical polishing (CMP: Chemical Mechanical Po
The present invention relates to a semiconductor device and a method for evaluating the same, which can easily confirm the polished state of a surface film when performing a lish) treatment and the finished state of the surface film during various manufacturing processes.

[0002]

2. Description of the Related Art In recent years, various microfabrication techniques have been developed in response to miniaturization and high density of semiconductor devices. As one of them, the CMP treatment has recently received more and more attention for polishing the surface film of a semiconductor wafer. The polishing by the CMP process is a process in which a slurry-like polishing agent in which polishing particles are suspended is supplied to the pad surface to perform a chemical and mechanical polishing process on the surface to be polished of a semiconductor wafer. In other words, in a semiconductor manufacturing process in which a semiconductor device is miniaturized or densified as desired, if there are steps or irregularities on the surface of the device formed on the semiconductor wafer, the depth of focus of the stepper etc. becomes shallow when the wiring pattern is formed. Therefore, it becomes impossible to obtain a sufficient resolution for photolithography when performing thin film photographic printing.

That is, as the degree of integration and performance of semiconductor wafers increases, the manufacturing process of semiconductor wafers becomes finer, and the minimum resolvable line width in the exposure process of semiconductor manufacturing becomes narrower. Therefore, it is required that the surface of the semiconductor wafer be highly flattened. Therefore, as in recent years, the minimum line width of the wiring pattern is 0.1.
When it becomes as thin as about 8 μm, the base film of the semiconductor wafer is flattened at an extremely high level by CMP processing,
It is necessary to resolve the pattern in the exposure process with high accuracy. Further, in the step of forming a groove on the insulating film by using RIE (Reactive Ion Etching), forming a metal film on the groove and removing the metal film formed on a portion other than the groove to perform groove wiring. Also, it is necessary to perform highly accurate CMP processing. In addition, shallow trench isolation in the field region adjacent to the active region (STI: Shallow Trench Isolation)
Also in the formation of, and the formation of a tungsten plug for connecting the interlayer wiring, it is necessary to highly flatten by a highly accurate CMP process.

Therefore, by CMP processing, the stepped portion and the uneven portion of the device surface on the semiconductor wafer are polished to highly flatten the surface. Particularly, in the production of semiconductor devices and the like that require a multilayer wiring structure, it is becoming more important to make the surface of a semiconductor wafer highly planarized by CMP. Further, in the evaluation and management of the film thickness and the unevenness by the CMP process performed in such a semiconductor manufacturing process, the film thickness value obtained by the optical film thickness measuring device and the cross-section SEM (Scanning Electron
Microscope: A scanning microscope is used to manage and operate a film thickness value for optimal CMP processing based on the unevenness value obtained.

[0005]

As described above, the CMP
The amount of unevenness relief of the surface of the film to be polished of the semiconductor wafer by the treatment, that is, the degree of flattening is set to be several tens nm to several hundreds nm in the next-generation semiconductor device that requires miniaturization and high density. It is required to finish to the extent. However, in the conventional method of evaluating and operating the film thickness in the CMP process, the film thickness value of the semiconductor wafer before and after the CMP process (that is, the film remaining film value to be polished) is measured by an optical film thickness measuring device and a cross-section SEM ( Scanning microscope). That is, one semiconductor wafer is extracted from a lot of polished semiconductor wafers and fractured, and the unevenness amount at various places in the chip of the fractured surface is measured by the cross-section SE.
It is measured by M. Furthermore, by identifying the part with a large amount of unevenness and measuring the film thickness value of that part with an optical film thickness measuring device, the correlation between the amount of unevenness and the film thickness value is obtained to evaluate and operate the film thickness. It is carried out.

However, in the case of measuring the unevenness step value using the cross-section SEM, a part of the semiconductor wafer to be evaluated must be destroyed to prepare a sample, so that a considerable labor and time are required for the measurement work. Become. Furthermore, the semiconductor wafer used as the measurement sample must be discarded.
Moreover, the chips of the semiconductor wafer include DRAM and SRA.
Since there are various patterns such as the M memory circuit, it is necessary to take a correlation between the unevenness amount and the film thickness value each time a new pattern reaches the polishing step, which requires a considerable number of measurement steps. Furthermore, in the film thickness measurement of the residual film by the above correlation, since the unevenness amount in the predetermined film thickness portion is obtained from the correlation, it is necessary to confirm the actual unevenness step value in the predetermined film thickness portion. Therefore, there are some problems such as lack of reliability of measurement results.

Japanese Patent Laid-Open No. 2001-127014 discloses a technique capable of controlling the CMP polishing amount by a nondestructive test by providing an element to be measured or the like on a scribe line outside the chip. According to this technique, a monitor element including an element to be measured having the same pattern as the chip and an optical film thickness measurement pattern is provided on the scribe line of the semiconductor wafer, thereby providing a CM.
The monitor element can control the film thickness of all the chips after the P treatment. However, in this technique, it is necessary to monitor the film thickness value by providing two types of patterns, a device to be measured and an optical film thickness measurement pattern, on the scribe line, which makes the circuit pattern for monitoring complicated. Become. Furthermore, although it is possible to control the thickness of the residual film, it is not possible to directly know the amount of unevenness on the surface.
It cannot cope with miniaturization and high density of semiconductor devices.

The present invention has been made in view of the above problems, and an object of the present invention is to polish a semiconductor wafer before and after completion of a CMP processing step and other processing steps without destroying the semiconductor wafer. It is an object of the present invention to provide a semiconductor device capable of quickly and accurately measuring the surface condition of a film and determining whether or not the unevenness has a level corresponding to miniaturization and high density, and a measuring method thereof.

[0009]

In order to achieve the above object, the semiconductor device of the present invention is a semiconductor device having a large number of chips each having an active region and a field region covered with a surface film. At least one measurement pattern for measuring the surface shape of the surface film by the surface shape measuring means is arranged at an arbitrary place on the semiconductor wafer which is an assembly of chips.

Further, in the semiconductor device of the present invention, the measurement pattern is arranged in a TEG pattern for evaluating a semiconductor manufacturing process existing in a semiconductor wafer or in a pattern of an arbitrary chip in a large number of chips. It is characterized by being.

Further, the semiconductor device of the present invention is characterized in that the measurement pattern is arranged between a plurality of chips existing in the semiconductor wafer.

Further, in the semiconductor device of the present invention, the measurement pattern is formed in either a wide pattern in which the interval between the active region and the field region is wide or a narrow pattern in which the interval between the active region and the field region is narrow. It is characterized by being.

In addition, the semiconductor device of the present invention is characterized in that the measurement pattern is adjusted to an appropriate size depending on the place where the measurement pattern is arranged.

Further, in the semiconductor device of the present invention, the measurement pattern is formed by the same pattern as any one of the patterns of a large number of chips.

Further, in the semiconductor device of the present invention, the measurement pattern is used for quality evaluation of the surface shape of the semiconductor wafer during or after the manufacturing process of the semiconductor wafer.

Further, in the semiconductor device of the present invention, the measurement pattern is used for quality evaluation of the surface shape in the CMP processing step and the impurity implantation step of the semiconductor wafer.

In the semiconductor device of the present invention, the surface shape measuring means is an AFM measuring apparatus, and the surface shape of the measurement pattern is measured by the AFM measuring apparatus during or at the end of the semiconductor wafer manufacturing process. , The quality of the surface shape of the semiconductor wafer is evaluated.

Further, the semiconductor device evaluation method of the present invention is an assembly of a large number of chips in the semiconductor device evaluation method in which the active region and the field region are composed of a large number of chips covered with a surface film. The semiconductor device is characterized in that at least one measurement pattern for measuring the surface shape of the surface film by the surface shape measuring means is arranged at an arbitrary position on the semiconductor wafer, and the semiconductor device is evaluated by the measurement pattern.

In the semiconductor device evaluation method of the present invention, the measurement pattern is a TEG pattern for evaluating a semiconductor manufacturing process existing in a semiconductor wafer, or a pattern of an arbitrary chip in a large number of chips. It is characterized by being arranged inside.

Further, the semiconductor device evaluation method of the present invention is characterized in that the measurement pattern is arranged between a plurality of chips existing in the semiconductor wafer.

Further, in the semiconductor device evaluation method of the present invention, the measurement pattern is either a wide pattern in which the interval between the active region and the field region is wide, or a narrow pattern in which the interval between the active region and the field region is narrow. It is characterized by being formed into a crab.

Further, the semiconductor device evaluation method of the present invention is characterized in that the measurement pattern is adjusted to an appropriate size depending on the place where the measurement pattern is arranged.

Further, the semiconductor device evaluation method of the present invention is characterized in that the measurement pattern is formed by the same pattern as one of the patterns of a large number of chips.

Further, the semiconductor device evaluation method of the present invention is characterized in that the measurement pattern is used for quality evaluation of the surface shape of the semiconductor wafer during or after the manufacturing process of the semiconductor wafer.

In the semiconductor device evaluation method of the present invention, the measurement pattern is CMP of the semiconductor wafer.
It is characterized in that it is used for quality evaluation of the surface shape in the processing step and the impurity implantation step.

Further, in the semiconductor device evaluation method of the present invention, the surface shape measuring means is an AFM measuring device, and the surface shape measuring means is used during or after the semiconductor wafer manufacturing process.
The quality of the surface shape of the semiconductor wafer is evaluated by measuring the surface shape of the measurement pattern with an AFM measuring device.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings. In the semiconductor device of the present invention, a pattern (hereinafter referred to as a measurement pattern) for measuring the surface shape is formed at an arbitrary place within the semiconductor wafer. For example, a measurement pattern is created in an evaluation TEG (Test Element Group) in a semiconductor wafer, in a circuit pattern in a chip, or in a scribe line between chips.
The configuration of this measurement pattern is the same as that of other chips. Further, the CMP process, the impurity implantation, and the like are performed in the same process both at the measurement pattern and at the other chip patterns.

Next, before and after the CMP treatment and before and after the impurity implantation, only a measurement pattern in the semiconductor wafer is measured by a surface shape measuring device, for example, an AFM (Atomic Force Microscower).
pe: Atomic force microscope) Measure the unevenness of the surface film with a measuring device. Then, if the unevenness amount is within a predetermined range, all the chips in the corresponding semiconductor wafer are sorted as non-defective products, or all the semiconductor wafers in the lot containing the relevant semiconductor wafer are sorted as non-defective products. Or That is, according to the present invention, if the surface shape is measured by an AFM measuring device or the like only at a measurement pattern provided in advance in the semiconductor wafer, it is possible to perform quality control of the unevenness amount in all the semiconductor wafers in the lot. .

Therefore, according to the semiconductor device of the present invention, by measuring the unevenness of the surface film of the measurement pattern by using an AFM measuring device whose measuring method is simple without breaking the measuring semiconductor wafer, Lot management can be performed in the wafer manufacturing process. As a result, the surface film can be managed in a short time in the CMP process and the impurity implantation process for coping with the miniaturization and high density of the semiconductor device.

FIG. 1 is a front view showing a part of a semiconductor wafer when a measurement pattern is arranged in a scribe line. That is, a semiconductor wafer has a large number of chips 15
Are arranged, and scribe lines 16 are formed between the chips. Then, the measurement pattern 17 is arranged at an arbitrary position on the scribe line 16. Such a measurement pattern 17 is a scribe line 1
It is desirable to arrange them at a plurality of six positions. After CMP processing or impurity implantation of the semiconductor wafer,
The surface shape of only the measurement pattern 17 is measured by the AFM measuring device. This controls the quality of the surface shape of the semiconductor wafer.

Here, a method of measuring the unevenness step value on the surface of the semiconductor wafer by the AFM measuring device which is a typical example of the surface profile measuring device will be described. FIG. 2 is a schematic diagram of an AFM measuring device for explaining the principle of measuring the unevenness of a semiconductor wafer. The AFM measuring device 1 includes an XY stage chuck 2 on which a semiconductor wafer 3 can be placed and which can be moved in a wide range in the XY directions, a probe 4 which comes into contact with the semiconductor wafer 3 by tracing uneven portions on the surface, and a probe. 4, a cantilever 5 which is always provided with a constant force and which is provided with a mirror 5 ′, an optical microscope 6, a laser oscillator 7 which emits a laser beam and irradiates the mirror 5 ′ of the cantilever 5 through the optical microscope 6, and a cantilever. A light receiver 8 that receives the laser beam reflected from the mirror 5'of No. 5 to detect the amount of unevenness of the semiconductor wafer 3, and outputs movement amount information in the Z-axis direction (hereinafter referred to as Z information) based on the amount of unevenness. A Z controller 9, an XY controller 10 that outputs movement amount information in the XY axis directions (hereinafter referred to as X information and Y information), and movement amount information in the XYZ axis directions (that is, X information, Y information). , Computer 1 calculates a relative position of the XYZ axes based on the Z information)
1 and a display screen 12 for displaying an image of the uneven portion on the semiconductor wafer 2 on the screen based on the data from the computer 11, and the probe 4 on the XY axis based on the X information and the Y information from the XY controller 10. XY fine movement mechanism 1 for fine movement in the direction
3 and a Z fine movement mechanism 14 that controls the tension of the cantilever so that the pressing of the probe 4 is always constant based on the Z information from the Z controller 9.

The XY stage chuck 2 is based on the X information and the Y information from the XY controller 10, for example,
The wide mode mechanism is configured to move a wide range of about 30 mm in the X-axis direction and the Y-axis direction so that the probe 4 can scan the entire area of the semiconductor wafer 2 having a diameter of 8 inches. In addition, the XY fine movement mechanism 13 includes the XY controller 1.
Based on the X information and Y information from 0, for example, the probe 4
Is a fine movement mechanism capable of moving in a narrow range of about 10 μm in the X-axis direction and the Y-axis direction on the chip of the semiconductor wafer 2. Furthermore, the Z fine movement mechanism 14 applies Z force so that a constant force of several nN is always applied to the surface of the semiconductor wafer 2 when the probe 4 rides on the convex portion of the semiconductor wafer 2 or falls into the concave portion. The tension of the cantilever 5 is adjusted by controlling the Z-axis direction based on the Z information from the controller 9.

Next, the operation of the AFM measuring device 1 shown in FIG. 2 will be described. First, the semiconductor wafer 3 is set as a measurement sample on the XY stage chuck 2 that can move wide in the X-axis direction and the Y-axis direction. Normally, the area in which the unevenness level difference of the semiconductor wafer 3 can be measured is about 0.1 μm square in one chip to 30 areas of the total area of the semiconductor wafer 3.
It is about a square mm. Therefore, within this range X
While moving the Y fine movement mechanism 13 and the XY stage chuck 2 in the X-axis direction and the Y-axis direction, the probe 4 scans the surface of the semiconductor wafer 3 to measure the unevenness of the surface of the semiconductor wafer 3.

That is, a contact force of several nN is applied to the surface of the semiconductor wafer 3 to the probe 4, and the contact force is made constant to scan the probe 4 in the X-axis direction. When one scan in the X-axis direction is completed, the XY stage chuck 2
Is shifted one line in the Y-axis direction to scan the next line on the X-axis. By performing such a scan until the measurement of the entire surface of the semiconductor wafer 3 is completed, the uneven step of the entire surface of the semiconductor wafer 3 is measured.

When scanning the probe 4 in the X-axis direction,
Depending on the amount of unevenness on the surface of the semiconductor wafer 3, the probe 4 is moved to Z
Since it moves in the axial direction, a force corresponding to the amount of movement of the probe 4 in the Z-axis direction is applied to the cantilever 5 to displace the cantilever 5. Therefore, the tilt of the mirror 5 ′ attached to the cantilever 5 changes. On the other hand, laser oscillator 7
Then, the mirror 5 ′ of the cantilever 5 is irradiated with the laser beam through the optical microscope 6 and reflected by the light receiver 8. Therefore, when the cantilever 5 is displaced and the tilt of the mirror 5'changes, the position where the light receiver 8 receives the laser beam changes. That is, since the light receiver 8 tracks the light receiving position of the laser beam to be received according to the change in the unevenness on the surface of the semiconductor wafer 3, the light receiver 8 can detect the unevenness amount on the surface of the semiconductor wafer 3. it can. In this way, the light receiver 8 detects the relative height with respect to the surface of the semiconductor wafer 3 as the unevenness amount.

Therefore, the detection data of the unevenness on the surface of the semiconductor wafer 3 detected by the trajectory of the laser beam received by the light receiver 8 is received from the receiver 8 to the Z controller 9
To Z-axis movement amount data (that is, Z information) and is input to the computer 11. On the other hand, X-axis movement amount data when scanning in the X-axis direction (that is,
(X information) is input to the computer 11 from the XY controller 10. That is, the computer 11 takes in the Z-axis movement amount data (Z information) for one line in the X-axis direction obtained by scanning the probe 4, and displays the image a on the display screen 12 as the amount of unevenness for one line in the X-axis direction. The uneven distribution is displayed.

In this way, when the unevenness amount of one line in the X-axis direction of the semiconductor wafer 3 is measured and the display on the display screen 12 is completed, the XY stage chuck 2 is moved to Y by the command information of the XY controller 10. By moving one line in the axial direction, the unevenness amount for one line in the X-axis direction is measured and loaded into the computer 11 as described above, and the unevenness amount data for the next one line in the X-axis direction is displayed on the display screen 12. It is displayed like image b. Hereinafter, similarly, the measured value of the unevenness step on the semiconductor wafer 2 is measured by the desired number of Y-axis lines,
The unevenness state of the surface of the semiconductor wafer 2 in a desired range is displayed like the unevenness distribution of the a, b, c, and d images shown on the display screen 12. Further, the computer 11 causes the display screen 12 to display the maximum value of the unevenness amount in the measurement area of the semiconductor wafer 2. That is, the maximum difference between the convex portion and the concave portion in the uneven step of the a, b, c, and d images shown on the display screen 12 is displayed on the screen.

Next, some embodiments of the manufacturing process of the measurement pattern for measuring the unevenness of the surface film by the above-mentioned AFM measuring device will be described. Figure 3
FIG. 3 is a schematic diagram showing a cross-sectional structure of a measurement pattern on a semiconductor wafer. The cross-sectional structure of the measurement pattern shown in FIG. 3 is exactly the same as the pattern structure of other chips in the same semiconductor wafer. In other words, in the structure of this measurement pattern, the semiconductor operating region in which SiN is formed on the Si wafer is the active region, and the non-operating region in which the trench is formed by etching is the field region. That is, etching is performed in the field region, and element isolation by a shallow groove (S
TI: Shallow Trench Isolation) is formed, and a SiO ₂ film, which is a common film to be polished, is formed on the active region and the field region.

First Embodiment First, the manufacturing process of the measurement pattern in the first embodiment will be described. FIG. 4 is a perspective sectional view of the measurement pattern before the CMP process, and FIG. 5 is a perspective sectional view of the measurement pattern after the CMP process. Further, FIG. 6 is a perspective cross-sectional view after removing the polishing-preventing SiN film and the sacrificial oxide film after the CMP process. The sacrificial oxide film is a protective oxide film that is removed and removed after the previous process is completed.
FIG. 7 is a perspective cross-sectional view of a measurement pattern showing an impurity implantation step, (a) shows impurity implantation into an N channel region,
(B) shows the impurity implantation into the P channel region. Also,
FIG. 8 is a perspective sectional view of a measurement pattern in which a gate SiO ₂ film is formed after implanting impurities. That is, FIG. 8 is a perspective sectional view of the measurement pattern before the gate wiring is formed.

Next, the manufacturing procedure of the measurement pattern and the AFM
The procedure for measuring the unevenness amount of the surface film by the measuring device will be described in the order of steps shown in the drawing. A measurement pattern as shown in the pre-CMP process diagram of FIG. 4 is created in advance at an arbitrary place on the semiconductor wafer, for example, in a pattern of an arbitrary chip or in a scribe line between chips. .
This measurement pattern, as shown in FIG.
Trenches 22 are formed at equal intervals on the upper surface of each of the Si substrates 21, and sacrificial SiO ₂ to be removed during the process is formed on the upper surface of each Si substrate 21.
A film 23 and a SiN film 24 for preventing polishing are formed.
The region in which one Si substrate 21 is formed is the P-channel active region 25, and the region in which the other Si substrate 21 is formed is the N-channel active region 26. Incidentally, these P channel active regions 25 and N
The channel active region 26 may be composed of a plurality of pairs.

Si is formed on the semiconductor substrate thus formed.
Since the O ₂ film 27 is formed, S is formed in the trench 22 portion.
The iO ₂ film 27 is in a buried state. As a result, a concave portion is formed on the surface layer in the field region F and a convex portion is formed on the surface layer in the active region A.
Therefore, the uneven portion of the surface layer is polished by CMP treatment to flatten the surface layer. The CMP treatment is a well-known technique in which a slurry-like polishing agent is supplied to the pad surface to chemically and mechanically polish the surface of a thin plate-shaped object to be polished such as a semiconductor wafer. Therefore, the description thereof is omitted.

That is, as shown in the step diagram after the CMP treatment of FIG. 5, when the uneven portion of the surface layer of the SiO ₂ film 27 is polished and flattened by the CMP treatment, the surface shape is measured by the AFM measuring device. To do. Here, the CMP process is performed over the entire surface of one semiconductor wafer, but the AFM measuring device does not measure the surface shape over the entire surface of the semiconductor wafer, but the AFM measuring device shown in FIG.
Only the surface shape of the measurement pattern as shown in is measured.
That is, the amount of unevenness is measured by the AFM measuring device on the surface layer of the active region A or the field region F in the measurement pattern shown in FIG. 5 formed in an arbitrary portion such as in the scribe line. In this way, by measuring the surface shape of only the measurement pattern portion after the CMP treatment, the quality control after the polishing step by the CMP treatment of the semiconductor wafer can be performed quickly and accurately. Of course, before and after the CMP process, the amount of unevenness may be measured by an AFM measuring device to perform quality control.

Next, as shown in the peeling process diagram of FIG. 6, the SiN film 24 for protection and the sacrificial SiO ₂ film 23 are peeled by wet etching. Further, after a photoresist is formed on the surface, a portion into which impurities are implanted is etched and opened to perform impurity implantation for determining transistor performance. That is, as shown in the N-type impurity implantation step diagram of FIG. 7A, after forming the photoresist 28, only the portion in the vicinity of the N-channel active region 26 is opened by etching, and the N-channel active region 2 is formed.
N-type impurities are diffused and injected into the portion 6. Next, FIG.
As shown in the (b) P-type impurity implantation step diagram, after the photoresist 28 is formed, only the portion in the vicinity of the P-channel active region 26 is opened by etching, and the P-type impurity is introduced into the P-channel active region 26 portion. Diffusion injection.

After the impurities have been implanted in this way, the photoresist 28 is removed by wet etching, and then the surface of the P channel active region 25 is removed by an oxidizing furnace as shown in the gate film forming process diagram of FIG. The gate SiO ₂ film 2 is formed on the surface of the N-channel active region 26.
9 is deposited. When such a film forming process is completed, the amount of unevenness of the surface layer of the active region A or the field region F in the measurement pattern is measured again by the AFM measuring device.

Here, as shown in FIG. 8, depending on the type of impurities implanted in the P-channel active region 25 and the N-channel active region 26, the amount of the impurities, and the implantation energy of the impurities, the adjacent field regions F are formed. Si
The amount of recession (that is, the amount of scraping) of the O ₂ film 27 is different. That is, the retreat amount u of the SiO ₂ film 27 in the field region F adjacent to the N-channel active region 26 into which the N-type impurity is implanted and the retreat amount of the SiO ₂ film 27 adjacent to the P-channel active region 25 in which the P-type impurity is implanted. Quantity w
Is different.

As a result, the unevenness of the active area A and the field area F becomes uneven, and the gate wiring cannot be processed with high precision. Therefore, in the surface shape shown in FIG. 8, after forming the gate SiO ₂ film 29, the unevenness step value of the surface layer of the measurement pattern is measured again by the AFM measuring device. That is, the surface shape of the device in the manufacturing process of the semiconductor wafer can be confirmed by measuring the unevenness step value of the measurement pattern after implanting the impurities. Of course, the quality control may be performed by measuring the unevenness step value with an AFM measuring device before and after the impurity implantation.

In this way, the measurement patterns are arranged at arbitrary plural points on the semiconductor wafer, and the surface state of the measurement patterns is appropriately before and after the CMP processing step, before and after the impurity implantation step, and before and after the other steps. Is measured by the AFM measuring device, the surface film can be managed in a short time in the CMP process, the impurity implantation process, and the like in order to cope with the miniaturization and the high density of the semiconductor device.

Further, like the circuit patterns of other chips, a wiring pattern or the like can be built in the measurement pattern to a state where the electrical characteristics can be measured.
As a result, by inspecting the electrical characteristics during the manufacturing process or after the manufacturing process by the measurement pattern, it is possible to easily perform the product inspection within the lot of semiconductor devices in the process of completing the product. Therefore, the in-process inspection and the process end inspection can be performed easily and in a short time. In this way, if a measurement pattern is provided in the semiconductor wafer and a circuit pattern similar to that of other chips is created, the measurement pattern can also be used as a process check pattern for semiconductor manufacturing.

Second Embodiment Next, a measurement pattern in the second embodiment will be described. In this embodiment, an example in which a metal film is formed on the surface layer of the measurement pattern and a metal-based CMP process is performed will be described. FIG. 9 is a perspective sectional view of a measurement pattern on which a metal film is formed before a metal-based CMP process,
(A) shows the cross section of a wide measurement pattern, (b) shows the cross section of a narrow measurement pattern. FIG. 10 is a perspective cross-sectional view of the measurement pattern formed with the metal film after the metal-based CMP treatment, and (a) is a cross section of the wide measurement pattern,
(B) shows the cross section of the narrow measurement pattern.

As shown in the sectional view of FIG. 9 before the metal-based CMP treatment, a barrier metal 3 of a metal oxide film is formed on the semiconductor layer.
After forming 2, a metal film 31 such as Cu is formed on the surface to form a measurement pattern. Of course, the other chips in the semiconductor wafer have the same pattern configuration as the measurement pattern. Such a measurement pattern is as shown in FIG.
There are a wide pattern in which the field region F and the active region A are formed wide, and a narrow pattern in which the field region F and the active region A are formed narrow as shown in FIG. 9B. In the case of the wide pattern of FIG. 9A, the metal film 31 is depressed in the field region F and the metal film 31 is raised in the active region A.
In the case of the narrow pattern shown in FIG. 9B, the metal film 31 is raised in the field region F and the active region A, and the metal film 31 is depressed in the base insulating film 33. As described above, the deposition shape of the metal film 31 varies depending on the arrangement of the underlying pattern of the metal film 31 to be deposited.

Therefore, by performing the metal-based CMP treatment, the surface of the metal film 31 has a shape as shown in the sectional view after the metal-based CMP treatment of FIG. That is, in the case of the wide pattern, as shown in FIG. 10A, the residual film dependency of dishing in which most of the metal film 31 such as Cu is removed due to the underlying structure is shown. In the case of the narrow pattern, as shown in FIG. 10B, the residual film dependence of erosion due to the underlying structure is shown. Therefore, after the CMP process, the residual film of the metal film 31 of the measurement pattern formed as shown in FIGS. 10A and 10B due to the underlying structure is measured by the AFM measuring device. In this way, the surface pattern of the semiconductor wafer can be confirmed by measuring the shape of the residual film and the amount of depression of the metal film by using the measurement pattern in the semiconductor wafer by the AFM measuring device.

Further, similar to the circuit patterns of other chips, if wiring patterns and the like are formed in the measurement pattern to a state where the electrical characteristics can be measured, the measurement pattern can be changed during or after the manufacturing process. By performing the electrical characteristic measurement, it is possible to obtain the correlation of the electrical characteristic with respect to the shape of the semiconductor device, so that the in-process inspection can be further simplified. In this way, if the measurement pattern is formed in the semiconductor wafer and the circuit configuration similar to that of other chips is also formed, the measurement pattern can be used as a process check pattern for semiconductor manufacturing.

The embodiment described above is an example for explaining the present invention, and the present invention is not limited to the above-mentioned embodiment, and various modifications can be made within the scope of the invention. is there. That is, in the above-described first and second embodiments, the surface shape of the measurement pattern is measured by the AFM measuring device after the CMP process or after the impurity implantation, but it is preliminarily created in any other manufacturing process of the semiconductor device. By measuring the surface shape of the formed measurement pattern with an AFM measuring device, quality control in the semiconductor device manufacturing process can be easily performed. For example, the above-described measurement pattern can be used also in the film thickness management of the semiconductor device in the etching process, the cleaning process, the CVD process, and the PVD process.

That is, lot control can be performed on the shape and electrical characteristics of the semiconductor wafer by measuring the measurement pattern prepared in advance in the semiconductor wafer in every step in the manufacturing process of the semiconductor device. In particular, in the case of quality control of the surface shape of a semiconductor wafer, if the surface shape of a measurement pattern is measured using a surface shape measuring device such as an AFM measuring device, the quality control of semiconductor devices flowing in a production line, It is possible to easily determine the film thickness condition in the process and perform various evaluations in the process.

[0055]

As described above, according to the semiconductor device of the present invention, the measurement pattern having the same structure as the chip pattern is formed in advance at an arbitrary position on the semiconductor wafer. Thus, after the semiconductor wafer is subjected to CMP processing, the surface shape of the semiconductor wafer of the same lot as the semiconductor wafer can be quality-controlled by measuring the unevenness of only the surface portion of the measurement pattern using an AFM measuring device or the like. . Furthermore, the impurity can be implanted in the same manner at the measurement pattern and the other chips. The surface shape of only the measurement pattern can be measured by the AFM measuring device after the impurity injection, and thus the surface shape of the semiconductor wafer of the same lot can be measured. Can be quality controlled. That is, in the semiconductor device manufacturing process, if the surface shape of only the measurement pattern provided in advance is measured by the AFM measuring device, all the semiconductor wafers in the same lot can be evaluated quickly and accurately. .

That is, according to the semiconductor device of the present invention, by providing a measurement pattern in advance, CMP
Before and after various semiconductor manufacturing processes such as treatment, CVD process, PVD process, cleaning process, and etching process, by measuring only the surface shape of the measurement pattern with a surface shape measuring device such as an AFM measuring device, Quality control can be performed accurately. Therefore, the unevenness step value and the flatness of the semiconductor wafer before and after various processes can be grasped quickly and accurately, which can greatly contribute to the improvement of the productivity of the semiconductor device. Further, by arranging such a measurement pattern on various evaluation TEGs, it is possible to evaluate the performance of the CMP apparatus, the performance of various consumable materials such as abrasives in the CMP apparatus, and the criteria for determining the polishing conditions for the CMP process. It can also be applied.

[Brief description of drawings]

FIG. 1 is a front view showing a part of a semiconductor wafer when a measurement pattern is arranged in a scribe line.

FIG. 2 is a schematic view of an AFM measuring device for explaining the principle of measuring unevenness of a semiconductor wafer.

FIG. 3 is a schematic diagram showing a cross-sectional structure of a measurement pattern on a semiconductor wafer.

FIG. 4 is a perspective sectional view of a measurement pattern before CMP processing.

FIG. 5 is a perspective sectional view of a measurement pattern after CMP processing.

FIG. 6 is a perspective cross-sectional view after removing a polishing-preventing SiN film and a sacrificial oxide film after CMP processing.

FIG. 7 is a perspective cross-sectional view of a measurement pattern showing an impurity implantation step, in which (a) is impurity implantation into an N channel region,
(B) shows the impurity implantation into the P channel region.

FIG. 8 is a perspective sectional view of a measurement pattern in which a gate SiO ₂ film is formed after implanting impurities.

FIG. 9 is a metal-based CM having a measurement pattern in which a metal film is formed.
It is a perspective sectional view before P processing, (a) shows the cross section of a wide measurement pattern, (b) shows the cross section of a narrow measurement pattern.

FIG. 10 is a metal pattern C of a measurement pattern formed with a metal film.
It is a perspective cross-sectional view after MP processing, (a) shows the cross section of a wide measurement pattern, (b) shows the cross section of a narrow measurement pattern.

[Explanation of symbols]

1 ... AFM measuring device, 2 ... XY stage chuck, 3 ...
Semiconductor wafer, 4 ... Probe, 5 ... Cantilever, 5 '...
Mirror, 6 ... Optical microscope, 7 ... Laser oscillator, 8 ... Light receiver, 9 ... Z controller, 10 ... XY controller, 11 ... Computer, 12 ... Display screen, 13 ... XY fine movement mechanism, 14 ... Z
Fine movement mechanism, 15 ... Chip, 16 ... Scribing line, 1
7 ... Measurement pattern, 21 ... Si substrate, 22 ... Trench,
23 ... Sacrificial SiO ₂ film, 24 ... SiN film, 25 ... P-channel active region, 26 ... N-channel active region, 27 ... SiO ₂ film, 28 ... Photoresist, 29 ...
Gate SiO ₂ film, 31 ... Metal film, 32 ... Barrier metal, 33 ... Base insulating film

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 4M106 AA01 AA10 AB20 BA10 CA38                       CB30 DB18 DB30                 5F032 AA35 AA44 AA77 AA84 CA17                       DA24 DA78                 5F033 HH11 MM01 QQ48 VV12 XX01                       XX37

Claims (18)

[Claims] 1. A semiconductor device having an active region and a field region formed of a large number of chips covered with a surface film, wherein surface shape measuring means is provided at an arbitrary position on a semiconductor wafer which is an assembly of the large number of chips. At least one measurement pattern for measuring the surface shape of the surface film is arranged by the semiconductor device. 2. The TEG for evaluating a semiconductor manufacturing process existing in the semiconductor wafer, wherein the measurement pattern is used.
The semiconductor device according to claim 1, wherein the semiconductor device is arranged in a pattern of (Test Element Pattern) or in a pattern of an arbitrary chip in the plurality of chips. 3. The semiconductor device according to claim 1, wherein the measurement pattern is arranged between a plurality of chips existing in the semiconductor wafer. 4. The measurement pattern is a wide pattern in which a space between the active region and the field region is wide,
4. The semiconductor device according to claim 1, wherein the active region and the field region are formed in any one of narrow patterns having a narrow interval. 5. The semiconductor device according to claim 1, wherein the measurement pattern is adjusted to have an appropriate size according to a place where the measurement pattern is arranged. 6. The semiconductor device according to claim 1, wherein the measurement pattern is formed by the same pattern as any one of the patterns of the plurality of chips. 7. The method according to claim 1, wherein the measurement pattern is used for quality evaluation of a surface shape of the semiconductor wafer during or after the manufacturing process of the semiconductor wafer. The semiconductor device described. 8. The semiconductor device according to claim 7, wherein the measurement pattern is used for quality evaluation of a surface shape in a CMP processing step and an impurity implantation step of the semiconductor wafer. 9. The surface shape measuring means is an AFM measuring device, wherein during or after the manufacturing process of the semiconductor wafer,
9. The semiconductor device according to claim 7, wherein the quality of the surface shape of the semiconductor wafer is evaluated by measuring the surface shape of the measurement pattern with the AFM measuring apparatus. 10. A method for evaluating a semiconductor device, comprising an active region and a field region, which is composed of a large number of chips covered with a surface film, wherein a surface of a semiconductor wafer, which is an assembly of the large number of chips, is placed at an arbitrary position. A method for evaluating a semiconductor device, wherein the evaluation of a semiconductor device in which at least one measurement pattern for measuring the surface shape of the surface film is arranged by the shape measuring means is performed by the measurement pattern. 11. The measurement pattern is a TE for evaluating a semiconductor manufacturing process existing in the semiconductor wafer.
The semiconductor device evaluation method according to claim 10, wherein the semiconductor device is arranged in a G (Test Element Pattern) pattern or in a pattern of an arbitrary chip in the plurality of chips. 12. The method for evaluating a semiconductor device according to claim 10, wherein the measurement pattern is arranged between a plurality of chips existing in the semiconductor wafer. 13. The measurement pattern is formed in either a wide pattern in which the interval between the active region and the field region is wide or a narrow pattern in which the interval between the active region and the field region is narrow. 13. The method for evaluating a semiconductor device according to claim 10, wherein: 14. The method for evaluating a semiconductor device according to claim 10, wherein the measurement pattern is adjusted to have an appropriate size according to a place where the measurement pattern is arranged. 15. The semiconductor device evaluation method according to claim 10, wherein the measurement pattern is formed by the same pattern as any one of the patterns of the plurality of chips. 16. The method according to claim 10, wherein the measurement pattern is used for quality evaluation of the surface shape of the semiconductor wafer during or after the manufacturing process of the semiconductor wafer. A method for evaluating a semiconductor device as described above. 17. The measurement pattern is used for quality evaluation of a surface shape in a CMP processing step and an impurity implantation step of the semiconductor wafer.
7. The method for evaluating a semiconductor device according to item 6. 18. The surface shape measuring means is an AFM measuring device, and the surface shape measuring means is an AFM measuring device.
18. The method for evaluating a semiconductor device according to claim 16, wherein the quality of the surface shape of the semiconductor wafer is evaluated by measuring the surface shape of the measurement pattern with the AFM measuring device.