JP2003150460A - Memory initial activation control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory writing initial activation control circuit capable of properly detecting an anomaly of any state of a memory circuit 1. SOLUTION: When a power source is turned on, all pieces of data read from the memory circuit 1 are written again into the memory circuit 1 from a memory input switching circuit 7. At the same time, a parity sending circuit 5 generates parity bits of the pieces of data to be written in the memory circuit 1, a parity reversal control circuit 9 controlled by control of an initial control circuit 4 reverses the parity bits, and the reversed parity bits are written in a parity region of the memory circuit 1. All pieces of data are read from the memory circuit 1, an alarm generating state is provided, all the pieces of the data are written again into the memory circuit 1, normal parity bits are written into the memory circuit 1, and the alarm generating state is terminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique used in a communication device or a control circuit device having a memory circuit, and particularly to a technique for monitoring the normality of the circuit.

[0002]

2. Description of the Related Art Conventionally, in some memories, a parity bit is made redundant in order to ensure data reliability, and it is configured by adding one parity bit to n bits of input data. . In such a memory write initial startup control circuit that performs initialization control when the memory is powered on, when the memory circuit is powered on, the entire data area in the memory is rewritten to "0" or "1". ,
Parity data is generated for each address line so that an error does not occur in the parity check, and this parity data is written in the parity area.

FIG. 3 shows this conventional memory write initial startup control circuit. In the conventional circuit configuration, when power is turned on to the memory circuit 1 or the circuit section mainly including this circuit, the uncertain data at all addresses in the memory circuit 1 are all rewritten by the initialization circuit 8. .

In the rewriting operation, the initialization circuit 8 starts the writing circuit 2 from the moment the power is normally applied to each circuit.
And a control signal is sent to the selection circuit 7 for a certain period of time. And
The write circuit 2 sends a write signal to all addresses of the memory circuit 1, and the selection circuit 7 selects fixed data “0” and sends fixed input data “0” to the memory circuit 1. To do.

At this time, the parity transmission circuit 5 calculates the parity for the fixed input data "0" and writes the result as a parity bit in the parity area of the memory circuit 1.

As a result, in the conventional memory write initial startup control circuit, after a fixed time of initial startup processing time, all the data in the memory become fixed "0", and the parity for all the data is No alarm occurs because it is normal.

When this process is completed, the memory circuit 1 receives write information and write data from the outside and performs a normal write side processing operation. Further, the memory circuit 1 receives read information from the outside and performs a normal read side processing operation.

[0008]

However, the conventional memory write initial startup control circuit writes the fixed input data as the initial startup processing operation, and generates the parity bit based on the written input data. Therefore, if there is an abnormality in which a certain address area shows the same value as the fixed input data (for example, the memory circuit 1
Is rewritten to the fixed input data “0”, and the abnormal portion may become “0”. ),
At the stage when the initial startup processing operation is performed, it is apparently normal, so no abnormality is detected by the parity bit.
A parity error will not be detected until the reading and writing of data is started after shifting to the actual operation mode.

That is, depending on the abnormality of the memory circuit 1,
There was a problem that the abnormality could not be detected despite the abnormality during the initial startup operation. In addition, there was a problem that the location of the abnormality could not be specified because no alarm was issued even if the data abnormality was found.

In view of the above problems, an object of the present invention is to provide a memory write initial start-up control circuit capable of correctly detecting an abnormality in any state of the memory circuit 1.

[0011]

[Means for Solving the Problems]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows the configuration of the memory write initial startup control circuit of the present invention. The memory circuit 1 stores data and parity bits, and the write circuit 2 that controls input data writing to the memory circuit 1. A read circuit 3 for controlling reading of data from the memory circuit 1; an initial control circuit 4 for controlling initial startup of the memory circuit 1; and a parity bit of the input data to generate a parity area in the memory circuit 1. A parity transmission circuit 5 for writing and an alarm detection circuit 6 for outputting a warning when an abnormality is detected by performing a parity check on read data.
, A memory input switching circuit 7 that switches between externally input data and output data from the memory 1 and outputs the data to the memory 1, and a parity bit generated by the parity sending circuit 5 is inverted to a parity area of the memory circuit 1. And a parity inversion control circuit 9 for writing.

Next, the operation of the present invention will be described.

When the power is turned on, first, the initial control circuit 4 controls the read circuit 3 to read the data for all read addresses from the memory circuit 1, and the memory input switching circuit 7 selects the output data from the memory circuit 1. Control to do.

The data read from the memory circuit 1 is sent to the input side of the memory circuit 1 through the memory input switching circuit 7 and controlled by the initial control circuit 4 to write circuit 2.
Is written in the memory circuit 1. At that time, when the parity sending circuit 5 generates a parity bit of the data to be written in the memory circuit 1, the parity inversion control circuit 9 controlled by the control of the initial control circuit 4 inverts the parity bit, and the inverted parity bit is stored in the memory circuit. Write to the parity area of 1.

That is, in this state, when data is read from the memory circuit 1, a parity error occurs at all read addresses and the alarm detection circuit 6 outputs an alarm.

Then, the memory circuit 1 which is initially started up
The data of all the addresses are read from and the alarm detection circuit 6 confirms that an alarm is generated. When this confirmation is completed, new input data is written in all the address data of the memory circuit 1. As the new input data, the memory input switching circuit 7 may select the data from the memory circuit 1 and write the same data, or the memory input switching circuit 7 may select the input data from the outside to generate completely new data. You can write it.

When writing new input data to the memory circuit 1, the parity sending circuit 5 generates a correct parity bit of the input data and writes it in the parity area of the memory circuit 1.

Here, the data of all addresses are read from the memory circuit 1 to confirm that the alarm detection circuit 6 does not generate an alarm.

When the above confirmation is normally completed, the initial startup of the memory circuit 1 is normally completed. On the other hand, if the confirmation is abnormal, it is determined that the memory circuit 1 is abnormal, and measures such as replacement of the memory circuit 1 are taken.

Thereafter, the memory circuit 1 returns to the original write operation and read operation under the control of the outside. In the original operation, according to a write instruction from the outside, the individual data sent to each address is written in the memory circuit 1, and at the same time, the parity sending circuit 5 generates a normal parity bit that does not cause a parity error, and the memory circuit Written to 1. Also in the read operation, individual addresses are read by a read instruction from the outside.

FIG. 3 shows an example of the operation timing of the present invention. (1) power supply startup time, (2) initial startup processing time of the memory circuit 1, (3) externally in an alarm state. The memory circuit read time, (4) external memory write time, (5) external memory read time after alarm release, and (6) external alarm output state are shown, respectively.

[0023]

As described above, according to the present invention,
Even if the memory circuit does not normally generate an alarm, or if the monitoring system malfunctions that are not found to be abnormal until the circuit actually goes into operation, all memory circuits and write operations are performed at the initial startup stage of the circuit. It is possible to judge the normality of the monitoring system circuit including the circuit, the reading circuit, and the alarm detection circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional memory initial startup control circuit.

FIG. 2 is a block diagram showing a memory initial startup control circuit according to the present invention.

FIG. 3 is a time chart showing an operation example of the present invention.

[Explanation of symbols]

1 memory circuit 2 writing circuit 3 readout circuit 4 Initial control circuit 5 Parity transmission circuit 6 Alarm detection circuit 7 Memory switching circuit 8 initialization circuit 9 Parity inversion control circuit

Claims (2)

[Claims] 1. A memory circuit having an error detection code based on data and parity, an initial control circuit for controlling initial startup of the memory circuit, a write circuit for controlling writing, a read circuit for controlling reading, and an external device. Memory input switching circuit that switches the data from the memory circuit and the data from the memory circuit and outputs the data to the memory circuit, the parity circuit that generates the parity bit of the data to be written and writes the parity bit to the memory circuit, and the parity bit that is generated by the parity circuit. A parity inversion control circuit for inverting
An alarm detection circuit that performs a parity check of the data read from the memory circuit, and the initial control circuit is a parity bit generated by the parity transmission circuit by the parity inversion control circuit when the power is turned on. A memory initial start-up control circuit characterized by inverting. 2. The initial control circuit switches from the memory circuit by switching the memory input switching circuit to data from the memory circuit and controlling the parity inversion control circuit when the power is turned on. The data and the inverted parity bit are written in the memory circuit, and then the memory input switching circuit is switched to external data, whereby new data and a correct parity bit are written in the memory. The memory initial startup control circuit according to claim 1.