JP2003133928A - Load drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a load drive circuit which is capable of largely reducing high frequency noise in switching without using passive components such as a large size L and C and without increasing the switching loss. SOLUTION: A power MOSFET 2 and a power source (+B) are connected in series to a motor 1, and a diode 3 is connected in parallel to the motor 1. A gate input capacitor of the MOSFET 2 is charged at first by a small current on a power MOSFET 2 on-command, and then is charged by a large current when the forward voltage of the diode 3 drops. The gate input capacitor of the MOSFET 2 is discharged at first by a large current on a power MOSFET 2 off-command, and then is discharged by a small current when the forward voltage of the diode 3 is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load drive circuit.

[0002]

2. Description of the Related Art As a technique of this kind, JP-A-11-29
In the Japanese Patent No. 9094, a coil and a capacitor are set at the gate terminal of the power MOSFET to suppress abrupt switching of the gate signal line and reduce high frequency noise generated at the drain and source terminals when switching the switching element. is there. This method has a demerit that switching loss becomes large because the turn-on / turn-off time of switching becomes longer than necessary. In addition, these passive elements have temperature characteristics, and predetermined performance can be obtained only under certain limited conditions. Therefore, generally, in order to prevent the conduction noise to the external wiring, a larger coil, an external component such as an aluminum electrolytic capacitor is required, which causes a problem of an increase in the outer shape and cost due to an increase in the circuit scale.

[0003]

The present invention has been made under such a background, and its object is to increase the switching loss without using large passive components such as L and C. , And to provide a load drive circuit capable of significantly reducing high frequency noise during switching.

[0004]

According to the first aspect of the present invention, the turn-off of the diode is monitored, and the diode is slowly charged until the diode exhibits its original function (the forward voltage of the diode disappears). By rapidly charging, it is possible to suppress the AC through current from flowing through the diode at the time of reverse recovery of the diode and to prevent the turn-on of the transistor from becoming long. As a result, high frequency noise at the time of switching turn-on can be reduced while avoiding an increase in switching loss without using large passive components such as L and C.

According to the second aspect of the present invention, the turn-on of the diode is monitored, and the diode is discharged rapidly (while the forward voltage of the diode is generated) while the diode performs the original function of the device, and then slowly discharged. By discharging, the voltage between the two terminals of the diode becomes less than the forward voltage before the turn-on of the diode and the fluctuation of the voltage between the two terminals of the diode can be suppressed and the turn-off of the transistor becomes longer. Can be avoided. As a result, high frequency noise at the time of switching turn-off can be reduced while avoiding an increase in switching loss without using large passive components such as L and C.

According to the third aspect of the present invention, by monitoring the turn-on of the diode, the diode is slowly charged until the diode exhibits the original function of the device (the forward voltage of the diode disappears), and then rapidly charged. In addition, it is possible to suppress the AC through current from flowing through the diode at the time of reverse recovery of the diode and to prevent the turn-on of the transistor from becoming long. Also, by monitoring the turn-on of the diode, it discharges rapidly (until the forward voltage of the diode is generated) while the diode is performing its original function, and then slowly discharges. It is possible to suppress variation in the voltage between both terminals of the diode due to the voltage between both terminals of the diode becoming equal to or lower than the forward voltage before the turn-on, and it is possible to prevent the turn-off of the transistor from becoming long. As a result, it is possible to reduce high-frequency noise during switching turn-on / off while avoiding an increase in switching loss without using large passive components such as L and C.

Further, as described in claim 4, it is preferable that the voltage between both terminals of the diode is monitored and the current is switched when the voltage becomes "0". Further, it may be applied when the load is a motor as described in claim 5.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the load drive circuit in this embodiment. In the present embodiment, it is applied to a drive circuit for an on-vehicle motor.

In FIG. 1, a motor 1 and a power MOSFET 2 are connected in series between a power source (battery) + B and ground. Specifically, one end of the induction motor 1 as a load is connected to the ground side and the other end is the power M.
It is connected to the power source + B via the OSFET2. A diode 3 is connected in parallel with the motor 1. Then, the power MOSFET 2 based on the on / off command (in this example, the PWM signal) of the power MOSFET 2
Power MOSFET2 by charging and discharging the gate input capacitance of
Is operated for switching to drive the motor 1. The details are as follows.

A drive circuit 4 is connected to the gate terminal of the power MOSFET 2. The drive circuit 4 includes a first charging circuit 10, a second charging circuit 20, a first discharging circuit 30, a second discharging circuit 40, and an output switching circuit 50.
Gate terminal of power MOSFET 2 and each circuit 10, 2
Resistors 100, 101, 10 between 0, 30, 40
2, 103 are interposed.

The first charging circuit 10 comprises bipolar transistors 11, 12, 13, 14, 15 and resistors 16, 17.
Consists of. In the first charging circuit 10, when each of the transistors 11 to 15 is turned on, the voltage Vp obtained by boosting the battery voltage + B is supplied to the power MOSF via the resistor 100.
It is applied to the gate terminal of ET2, and the gate input capacitance is charged with a small current (current of several μA level) i1. At this time, the value of the current i1 is determined by the value of the resistor 16. The second charging circuit 20 is composed of bipolar transistors 21, 22, 23 and resistors 24, 25, 26. In the second charging circuit 20, when the transistors 21 to 23 are turned on, a predetermined voltage V1 is applied to the resistor 101.
Is applied to the gate terminal of the power MOSFET 2 via the, and the gate input capacitance is charged with a large current (current of several hundred mA or more) i2. At this time, the value of the current i2 is determined by the value of the resistor 101. The second charging circuit 2
As the voltage applied to the gate terminal via the resistor 101 at 0, the boosted voltage Vp described above may be used instead of the predetermined voltage V1.

The first discharge circuit 30 comprises bipolar transistors 31, 32, 33, resistors 34, 35, 36 and diodes 37, 38. This first discharge circuit 30
When each of the transistors 31 to 33 is turned on, a large current (current of several hundred mA level) i from the gate input capacitance of the power MOSFET 2 to the ground side via the resistor 102.
Discharge is performed at 10. In addition, the second discharge circuit 40
Is a bipolar transistor 41, 42, 43 and a resistor 4
4 and. In the second discharge circuit 40, when the transistors 41 to 43 are turned on, the power MOSFE
The gate input capacitance of T2 is discharged through the resistor 103 to the ground side with a small current (current of several μA) i11.

A PWM signal for PWM-controlling the motor 1 receives a first charging circuit 10 via inverters 60 and 61.
Sent to. The potential between the resistor 17 of the first charging circuit 10 and the inverter 61 is pulled up via the resistor 62. Further, the PWM signal is sent to the second charging circuit 20 via the inverter 70 and the NAND gate 71. Second
The potential between the resistance 26 of the charging circuit 20 and the NAND gate 71 is pulled up via the resistance 72. Further, the PWM signal is transmitted to the NAND gate 80 and the inverter 81.
Is sent to the first discharge circuit 30 via. The potential between the resistor 36 of the first discharge circuit 30 and the inverter 81 is the resistor 8
Pulled up via 2. Further, the PWM signal is sent to the second discharge circuit 40 via the inverter 90. The potential between the transistor 43 of the second discharge circuit 40 and the inverter 90 is pulled up via the resistor 91.

The output switching circuit 50 includes charge / discharge circuits 10 and 2.
It is a circuit for switching 0, 30, 40 to operate. The output switching circuit 50 includes an operational amplifier 51, a resistor 52,
It comprises 53, 54, 55, 56, 57 and a diode 58. The output switching circuit 50 takes in the potential (source voltage Vs) at the source terminal (point α in the figure) of the power MOSFET 2, compares the source voltage Vs with the reference potential, and outputs an output signal based on the magnitude relationship. It outputs to the above-mentioned NAND gates 71 and 80. Specifically, the source voltage Vs is monitored by the output switching circuit 50, and when the source voltage Vs becomes higher than 0 volt and when the source voltage Vs becomes lower than 0 volt, the output is inverted and the charging / discharging circuit. Switch between 10, 20, 30, 40. As a result, charging and discharging of the gate input capacitance of the power MOSFET 2 are switched in two steps, respectively, and the transistor 2 is switching-driven.

Next, the operation of the load driving circuit thus constructed, that is, the switching operation of the power MOSFET 2 will be described. FIG. 2 shows each circuit 10, 20, 30, 40, corresponding to a PWM signal (transistor drive command signal).
It is a time chart which shows operation of 50.

Now, referring to FIG. 3, the inductive load (motor) 1
When PWM control is performed at about 20 kHz, the switching transistor 2 is turned on or off, and the voltage and current of each part are in the following states.

When the transistor 2 in FIG. 3 is turned on from the off state, the gate voltage Vg becomes higher than the threshold voltage Vt, the source potential Vs becomes the power source potential + B, the transistor conduction current Ion flows, and the diode 3 flows to the diode 3. The current Ioff does not flow. On the other hand, when the transistor 2 is turned off from the on state, the gate voltage Vg becomes the grant potential (<Vt), the source potential Vs becomes the forward voltage −Vf of the diode 3, the transistor conduction current Ion does not flow, and A current Ioff flows through the diode 3.

Considering the transient operation, the diode 3 turns off when the transistor 2 turns on, as shown in FIG. At that time, since the diode 3 equivalently operates as a capacitor (see FIG. 3), the reverse recovery time of the diode 3 is about 100 ns.
The C through current Ir flows. When the current is viewed as a load waveform, it becomes as shown in FIGS. 5 and 6, and as shown by A1 and A2 in the figure, the current / voltage change becomes large, which causes high frequency noise in the load wiring.

On the other hand, in FIG. 4, when the transistor 2 is turned off, the diode 3 is turned on, but due to the structure of the bipolar transistor, the switching time is slow and it takes about 1 μs until the current Ioff starts to flow.
Therefore, the source voltage Vs becomes lower than the forward voltage (−Vf) until the diode 3 is turned on, and
In the figure, undershoot occurs as indicated by A3 in the figure, and the voltage fluctuation also causes high frequency noise in the load wiring.

On the other hand, in this embodiment, it is as follows. When the PWM signal becomes a transistor-on command at the timing of t1 in FIG. 2, that is, at the time of turn-on, the transistors 11 to 11 of the first charging circuit 10 in FIG.
15 is turned on and the circuit 10 operates. As a result, the gate input capacitance of the power MOSFET 2 is charged with the small current i1. Charging by this small current i1 is power MOS
This is performed until the FET2 reaches the threshold voltage Vt from the off state. Here, the gate threshold voltage Vt of the power MOSFET 2 is + with respect to the source voltage in the enhancement type.
2-4 volts is a common value.

The gate voltage Vg is the power MOSF.
When the threshold voltage Vt of ET2 is reached (timing of t2 in FIG. 2), at that moment, the source voltage Vs starts to change from the off holding level. That is, normally, in the ON / OFF state, the source voltage Vs in the OFF-holding state is 0 V, but when switching is performed at high speed, the current is circulated through the diode 3, so that the diode 3 is forwarded. The source voltage Vs becomes 0-Vf in consideration of the directional voltage -Vf, so that the voltage rises from -Vf at the time of turn-on, and when the source voltage Vs becomes 0 volt, no current is supplied to the diode 3. (That is, reverse recovery) is detected.

In this way, the voltage between both terminals of the diode 3 is monitored, and when the voltage becomes "0", the reverse recovery of the diode 3 is detected. In this way, the first charging circuit 10 responds to the PWM control command (ON command) by
The gate input capacitance of the transistor 2 is charged with a small current i1 of several μA level until the source voltage Vs becomes 0 V (no forward voltage Vf).

Output switching circuit 50 indicates that Vs = 0.
When it is detected at, the output signal of the circuit 50 is inverted. As a result, the transistor 2 of the second charging circuit 20
The circuits 1 to 23 are turned on and the circuit 20 operates. As a result, the gate input capacitance is charged all at once with the large current i2 (the period from t2 to t3 in FIG. 2), and the power MOSFET 2 is turned on. In this way, the second charging circuit 20
When the source voltage Vs becomes 0 V (no Vf voltage) by the first charging circuit 10, the gate input capacitance of the transistor 2 is charged with a large current i2 of several hundred mA or more (rapidly turned on).

On the other hand, the turn-off control is the reverse of the turn-on control, and the transistors 31 to 33 of the first discharge circuit 30 of FIG. 1 are turned on to activate the circuit 30 and the transistor 41 of the second discharge circuit 40. ~ 43 is turned on and the circuit 40 operates. As a result, at the timing of t10 in FIG. 2, discharge is rapidly performed from the gate input capacitance of the power MOSFET 2 to the threshold voltage Vt with a large current (i10 + i11). In other words, the first and second discharge circuits 30 and 40 respond to a PWM control command (OFF command) until the source voltage Vs becomes 0 V (immediately before the Vf voltage is generated) from the gate input capacitance of the transistor 2 to a level of several hundred mA. Is discharged with a large current (i10 + i11).

When the output switching circuit 50 detects that the threshold voltage Vt is reached and Vs = 0 at the timing of t11 in FIG. 2, the output signal of the circuit 50 is inverted. As a result, the first discharge circuit 30 is in the inoperative state, that is, the transistors 31 to 33 of the circuit 30 are turned off. Thus, the second discharge circuit 40 gradually discharges the gate charge with a small constant current i11 (the period from t11 to t12 in FIG. 2). That is, the second discharge circuit 40
Causes the gate input capacitance of the transistor 2 to discharge with a small current i11 of several μA when the source voltage Vs becomes 0 V (the diode 3 is gradually turned on).

By controlling the driving of the power MOSFET 2 in this way, as shown in FIG. 2, the turn-on / off time is not changed, that is, the switching loss is not increased, and A4 in FIG. As shown in A5, A during reverse recovery of diode 3 at turn-on
It is possible to suppress the voltage / current change due to the C-through current, and to suppress the voltage undershoot and fluctuation due to the L load at the time of turn-off, as indicated by A6 in the figure in FIG.

That is, when the power MOSFET 2 is turned on and off, the voltage and current changes dV / dt and di / dt from 10% to 90% are made the same, and the diode 3 is turned on when the power MOSFET 2 is turned on. Since it is turned off, a current flows in the reverse direction during the reverse recovery time due to the hole accumulation effect of the diode 3, and at that time, an overvoltage (fluctuation) of L · di / dt occurs due to the parasitic L component, and Since the undershoot is the L load of the motor itself and is about 200 μH, the voltage is pulled in the negative direction by the above principle, but in the present embodiment, the current and the voltage change at turn-on / off are significantly reduced. It is possible to reduce high frequency noise caused by the frequency of the change.

The effect of the load drive circuit shown in FIG.
It is possible to reduce the high frequency noise level in the M band by about 10 dBm. After that, when switching from on to off and from off to on, the circuit 1
PW is switched in the order of 0 → 20 → 30, 40 → 40.
In M control, this is repeated at 20 kHz.

In this way, by feeding back the source voltage Vs to the transistor drive circuit 4, the turn-on / off state of the diode 3 is monitored, and it is confirmed that the diode 3 is in a state where it fulfills its original function. It is confirmed whether or not the forward voltage Vf of the diode 3 is generated, and when it is turned on, the transistor 2 is controlled to be rapidly turned on in the state where the Vf voltage is surely lost. In the case of turn-off, the transistor 2 is rapidly turned off until Vf is generated, and then Vf
The transistor gradually discharges with a low current until it occurs. This makes it possible to prevent noise and Vs undershoot.

As described above, this embodiment has the following features. (A) When the gate input capacitance of the power MOSFET 2 is initially charged with the small current i1 based on the ON command of the power MOSFET 2 and the forward voltage at the diode 3 disappears (when reverse recovery is detected), the large current i2 The gate input capacitance of the power MOSFET 2 is charged with. In this way, by monitoring the turn-off of the diode 3,
Charge slowly until the device exhibits its original function, that is, until the forward voltage of diode 3 disappears,
After that, by rapidly charging, it is possible to suppress the AC through current from flowing through the diode 3 at the time of reverse recovery of the diode 3 and to prevent the turn-on of the transistor 2 from becoming long. As a result, high frequency noise at the time of switching turn-on can be reduced while avoiding an increase in switching loss without using large passive components such as L and C. (B) On the other hand, based on the off command of the power MOSFET 2, the power MOSFET is initially supplied with a large current (i10 + i11).
When the gate input capacitance of T2 is discharged and a forward voltage is generated in the diode 3, the power MOSF is supplied with a small current i11.
Discharge from the gate input capacitance of ET2. As described above, while the turn-on of the diode 3 is monitored, the diode 3 discharges rapidly while the diode 3 is performing its original function, that is, until the forward voltage of the diode 3 is generated, and then slowly discharges. As a result, undershoot and fluctuation of the voltage between both terminals of the diode due to the voltage between both terminals of the diode 3 becoming equal to or lower than the forward voltage before the turn-on of the diode 3 can be suppressed, and the turn-off of the transistor can be long. Can be avoided. As a result, high frequency noise at the time of switching turn-off can be reduced while avoiding an increase in switching loss without using large passive components such as L and C.

By means of (a) and (b), it is possible to reduce high frequency noise while avoiding an increase in switching loss during switching turn-on / off.

In the above description, when switching the switch from ON to OFF and from OFF to ON, the circuit is switched in the order of 10 → 20 → 30, 40 → 40 to change the charging current i1. The discharge current is switched from (i10 + i11) to i11. However, the circuit is switched from the circuit 10 → 20 → 30 → 40 in order of the charging current from i1 to i2 and the discharging current from i10 to i11. May be.

Further, in the above description, the power M
The case of performing the two-stage charging operation based on the ON command of the OSFET2 and the two-stage discharging operation based on the OFF command of the power MOSFET 2 has been described.
Only the two-step charging operation based on the ON command of T2 may be performed, or only the two-step discharging operation based on the OFF command of the power MOSFET 2 may be performed.

The power MOSFET 2 has been described in the case of the n-channel, but it may be a p-channel. For more information,
In the case of n-channel power MOSFET, a booster circuit is required for the gate application power supply system, but p-channel power MO
In the case of SFET, the battery voltage + B is sufficient. However, since the signal phase for on / off operation is reversed, it is necessary to change the logic.
The same operation as in the case of can be performed.

Further, in the above-described embodiment, the switch structure is high side drive, but low side drive may be used.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a load drive circuit according to an embodiment.

FIG. 2 is a time chart for explaining the operation.

FIG. 3 is a diagram for explaining an operation.

FIG. 4 is a time chart for explaining the operation.

FIG. 5 is a diagram showing changes in load current and source voltage.

FIG. 6 is a diagram showing changes in load current and source voltage.

FIG. 7 is a diagram showing changes in gate voltage and source voltage.

FIG. 8 is a diagram showing changes in load current and source voltage.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Motor, 2 ... Power MOS transistor, 3 ... Diode, 4 ... Drive circuit, 10 ... 1st charging circuit, 20 ...
2nd charge circuit, 30 ... 1st discharge circuit, 40 ... 2nd discharge circuit, 50 ... Output switching circuit.

Claims (5)

[Claims] 1. A power MOSFET for a load (1)
(2) and a power source (+ B) are connected in series, a diode (3) is connected in parallel to the load (1), and a power MOSFET (2) based on an on / off command of the power MOSFET (2). In the load drive circuit that drives the load (1) by switching the power MOSFET (2) by charging and discharging the gate input capacitance of the power MOSFET (2), based on the ON command of the power MOSFET (2),
The gate input capacitance of the power MOSFET (2) is charged with a small current, and when the forward voltage of the diode (3) disappears, the gate input capacitance of the power MOSFET (2) is charged with a large current. A load drive circuit characterized by the above. 2. A power MOSFET for the load (1)
(2) and a power source (+ B) are connected in series, a diode (3) is connected in parallel to the load (1), and a power MOSFET (2) based on an on / off command of the power MOSFET (2). In a load drive circuit that drives the load (1) by switching the power MOSFET (2) by charging and discharging the gate input capacitance of the power MOSFET (2), based on an off command of the power MOSFET (2),
A large current is discharged from the gate input capacitance of the power MOSFET (2), and when a forward voltage is generated in the diode (3), a small current is discharged from the gate input capacitance of the power MOSFET (2). A load drive circuit characterized by the above. 3. A power MOSFET for the load (1)
(2) and a power source (+ B) are connected in series, a diode (3) is connected in parallel to the load (1), and a power MOSFET (2) based on an on / off command of the power MOSFET (2). In the load drive circuit that drives the load (1) by switching the power MOSFET (2) by charging and discharging the gate input capacitance of the power MOSFET (2), based on the ON command of the power MOSFET (2),
A small current charges the gate input capacitance of the power MOSFET (2), and when the forward voltage at the diode (3) disappears, a large current charges the gate input capacitance of the power MOSFET (2), while Power MOSFET
When the gate input capacitance of the power MOSFET (2) is initially discharged with a large current based on the off command of (2), and a forward voltage is generated in the diode (3), the power MOSFET (2 ) The load drive circuit characterized by discharging from the gate input capacitance. 4. The current is switched when the voltage between both terminals of the diode (3) is monitored and the voltage becomes “0”.
The load drive circuit according to claim 1. 5. The load drive circuit according to claim 1, wherein the load (1) is a motor.