JP2003129297A - Plating process - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plating process that can sufficiently prevent incomplete embedding of a concave part formed on a substrate when forming a copper plated film, or the like, on a semiconductor wafer, or the like. SOLUTION: In a plating device 100, a semiconductor wafer W is held at a tilted state by a holder head 41 of a wafer holder 40. When soaking the tilted wafer into a plating solution 22 stored in a solution tank 21 (soaking step), a voltage comparable to that applied to achieve an appropriate plating current in a later final film-forming step is applied between the surface to be plated of the semiconductor wafer W and a copper plate 14. This inhibits excessive formation of plated film in the soaking step, thereby preventing incomplete embedding of a hole on the semiconductor wafer W.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to an electrolytic plating method used for forming a metal film such as copper.

[0002]

2. Description of the Related Art In recent years, high integration and miniaturization of semiconductor devices have made rapid progress, and steadily shifting from the present sub-half micron to sub-quarter micron. In response to such demands for high integration and miniaturization of semiconductor devices, copper, which has low resistance and excellent electromigration resistance, has been attracting attention as a wiring material, and its practical application is in progress.

Various methods such as a sputter reflow method and a CVD method can be cited as a method for forming a copper wiring film. Among them, the electrolytic plating method has a low cost, a high throughput, and a via method. Since it is possible to obtain relatively good burying properties for recesses such as holes, contact holes, and other wiring trenches, it has been widely adopted at this time.

Here, as a conventional general copper electrolytic plating method, an object to be treated such as a semiconductor wafer is placed in a plating solution stored in a solution tank with its deposition surface facing downward, that is, facing the plating solution. There is known a method (so-called face-down method) of immersing the plate in such a state to perform plating film formation. In this plating method, a semiconductor wafer is immersed in a plating solution, a voltage is applied between a copper plate (functioning as an anode) arranged in a solution tank and the semiconductor wafer to flow a plating current, and copper is removed. It is adapted to be electrochemically deposited on a semiconductor wafer.

At this time, a copper seed layer is usually formed on the semiconductor wafer, and this seed layer serves as a film formation surface and functions as a cathode, and a copper thin film is formed on the seed layer. It In addition, when a semiconductor wafer is dipped in a plating solution, it takes a certain period of time from the start of immersion until the entire seed layer is dipped in the plating solution (for example, copper sulfate solution), during which the copper seed layer is plated. In order to prevent dissolution in the liquid, a constant voltage is often applied between the copper plate and the seed layer.

[0006]

However, as described above, the width of the recess such as the via hole is extremely narrowed with the miniaturization of the semiconductor device. Specifically,
For example, in the device structure corresponding to the design rule of 0.17 μm, it was observed that copper plating in the recess was completed in the step of immersing the semiconductor wafer in the plating solution. Usually, in order to improve the in-plane uniformity while improving the burying property of copper in the concave portion, plating is performed so as to promote bottom-up in the concave portion rather than copper deposition in other field portions. On the other hand, if the filling in the recess has already been completed in the dipping step, voids (bottom voids or the like) may occur in the recess, resulting in defective filling.

Therefore, the present invention has been made in view of the above circumstances, and when plating a copper film or the like on an object to be processed such as a semiconductor wafer, it is possible to sufficiently fill a concave portion formed on the object to be processed. It aims at providing the plating method which can be prevented.

[0008]

In order to achieve the above object, the present inventor has conducted a detailed study on a conventional plating method, and has obtained the following findings. First, in the semiconductor wafer dipping step in the conventional plating method, copper may be 170Å in the recesses such as via holes depending on the conditions.
May be deposited to some extent. When this happens, 0.17-0.
With a via hole size of 18 μm or less, the bottom-up speed increases remarkably, and filling tends to be completed in an extremely short time when a plating current flows during immersion on a semiconductor wafer.

Further, in the conventional plating method, the voltage value applied in the dipping step has been empirically determined to some extent. That is, when a copper sulfate solution is used as the plating solution, the equilibrium voltage at which the copper in the seed layer does not leach into the plating solution is about 0.6 V, and a margin is added to this to provide a minimum equilibrium voltage of 0.8 V. A voltage of the order of magnitude was applied. Furthermore, in order to improve the bottom-up performance of the recesses, plating solutions containing various additives are used, and in the film forming step, which is the main step after immersion, the plating current at which such additives effectively act. The voltage value is obtained so that In general, a voltage several times higher than the applied voltage in the film forming process is applied in the dipping process, and a high current tends to flow when substantially the entire seed layer is dipped and conductive. In this case, it was found that the film forming rate in the dipping step was much higher than that in the film forming step, and the filling of the recess was completed.

As described above, in the prior art, a voltage higher than the voltage for preventing the dissolution of the seed layer may be applied, and the detailed reason is unclear in many parts. One of them is as follows. Can be mentioned. That is, 0.22-0.2
In embedding a 5 μm generation via hole or the like, a higher applied voltage in the immersion step may be effective.

Specifically, in order to prevent an overhang due to electric field concentration at an edge (shoulder) portion which is an opening portion such as a via hole, a pulse plating method in which film formation and etching are repeated is often used. . In this case, in order to prevent the seed layer from being damaged by the etching effect, a protective film called a patch film is generally formed on the seed layer. Therefore, in the dipping step, even if the applied voltage is further increased and the plating proceeds,
It was a preferable treatment from the viewpoint of further strengthening the protective film.

The present inventor has reached the present invention as a result of further research based on these findings. That is, the plating method according to the present invention includes a dipping step of immersing an object to be processed such as a semiconductor wafer in a plating solution in a liquid tank in which a film-forming material source such as a copper plate is placed, and a film-formed surface of the object to be processed is And a film forming step of forming a metal film on the film formation surface by an electrolytic plating method while being immersed in a plating solution. First applied between the film-forming surface as a cathode
A second voltage having a magnitude substantially equal to the voltage of 1 is applied between the film forming material source and the film formation surface.

In such a method, a film forming step is performed after the dipping step, and plating is performed with a plating current (current density) determined by the first voltage applied between the electrodes and the liquid resistance of the plating solution. It At this time, a second voltage that is substantially equal to the first voltage in the film forming step is applied during the immersion step, that is, from the start of the immersion of the object to be treated in the plating solution to the execution of the film forming step. Therefore, it is possible to prevent the film formation surface such as the seed layer formed on the object to be processed from being dissolved in the plating solution. At the same time, when almost the entire film-forming surface as the anode comes into contact with the plating solution and is energized in the dipping step, a current equivalent to the plating current in the film-forming step flows. Therefore, even if the plating film formation proceeds in the dipping step, the film formation rate is prevented from increasing excessively.

The first voltage has a suitable plating current depending on the type of the plating solution used in the film forming step, the uneven shape of the film-formed surface of the object to be processed, the film thickness to be formed, etc. Therefore, it is possible to apply specific numerical values. Therefore, the second voltage in the dipping process can be easily determined by previously obtaining the first voltage determined by the plating current according to these plating conditions.

Alternatively, the plating method according to the present invention comprises an immersion step of immersing an object to be processed such as a semiconductor wafer in a plating solution in a solution tank in which a film forming material source such as a copper plate is arranged, and a step of forming the object to be processed. A film forming step of forming a metal film on the film formation surface by electrolytic plating while the film surface is immersed in a plating solution. In the immersion step, the following formula (1); × Vd ≦ Ve ≦ 1.15 × Vd (1), which is a method of performing voltage control so as to satisfy the relationship expressed by: Here, in the formula (1), Vd represents the first voltage applied between the film forming material source as the anode and the film forming surface as the cathode in the film forming step, and Ve is the immersion voltage. The second voltage applied between the film forming material source and the film formation surface in the step is shown.

As described above, the plating current in the film forming process may vary depending on the type of the plating solution, and the first voltage is expected to vary accordingly. However, in consideration of copper plating, for example, it is estimated that the first voltage suitable for the film forming step is around 1V. in this case,
When the second voltage Ve is lower than the left side of the formula (1), it is not preferable from the viewpoint of surely preventing the seed layer and the like from being dissolved in the plating solution. On the other hand, when the second voltage Ve exceeds the right side of the formula (1), the deposition rate of plating that occurs in the dipping step becomes excessively high, and it becomes difficult to prevent the recesses from being filled.

Further, in the dipping process, the present invention is applied to the case where the semiconductor wafer is gradually dipped in the plating solution in a state of being inclined at a predetermined angle with respect to the surface of the plating solution, particularly in the case of face down method. Is extremely effective.

In the face-down method, in order to prevent air bubbles from being trapped in the recess including the film-forming surface during immersion and to ensure contact between the plating solution and the film-forming surface, It is useful to gradually immerse the semiconductor wafer in the plating solution while inclining it from the horizontal at a predetermined angle. In such a case, the time required from when a part of the semiconductor wafer comes into contact with the plating solution until substantially the entire film-forming surface is immersed is longer than that when the semiconductor wafer is immersed without being tilted, which may cause the conduction. The current flow time may be relatively long. Therefore, in such a case, the dipping process in which an excessive voltage is not applied is very effective.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below. The same elements will be denoted by the same reference symbols, without redundant description. Further, the positional relationship such as up, down, left and right is based on the positional relationship shown in the drawings unless otherwise specified. The dimensional ratios in the drawings are not limited to the illustrated ratios.

1 to 4 are schematic cross-sectional views showing a preferred embodiment of a plating apparatus for effectively carrying out the plating method according to the present invention, each showing a state in which the plating apparatus is in operation. But also. Electrolytic plating apparatus 100
Is for forming a film of copper on the semiconductor wafer W that is the object to be processed, and includes a liquid tank 12 and a disk-shaped copper plate 14 that is a film-forming material source disposed below the liquid tank 12. ing.

A plating solution supply port 18 is provided at the bottom of the liquid tank 12. An external pump 20 is connected to the plating solution supply port 18 so that the plating solution 22 is supplied from the bottom into the solution tank 12 and flows upward. Further, the periphery of the liquid tank 12 is surrounded by an outer tank 24 so that the plating solution 22 overflowed from the liquid tank 12 can be received and the plating solution 22 can be collected in an external tank 26. .

The tank 26 is connected to the suction port of the pump 20 so that the plating solution 22 can be circulated and used. Although illustration is omitted, it is preferable that the tank 26 constitutes an automatic chemical solution control system. That is, the supply source of each component of the plating solution 22 and the component concentration detector are connected to the tank 26, and the supply amount from the supply source is controlled according to the signal from the concentration detector.
It is useful to always keep the composition and concentration of the plating solution 22 sent to the.

Further, the copper plate 14 is disposed substantially coaxially with the bottom of the liquid tank 12 having a substantially cylindrical shape, and an annular gap is formed between the inner wall surface of the liquid tank 12 and the copper plate 14. .
Therefore, the plating solution 22 supplied from the plating solution supply port 18 at the bottom of the solution tank 12 rises (flows up) in the solution tank 12 through this gap.

Furthermore, the plating apparatus 100 includes a liquid tank 1
And a plating solution 2 which is provided outside the semiconductor wafer W and holds the semiconductor wafer W while the semiconductor wafer W is stored in the liquid tank 12.
A wafer holder 40 to be dipped in 2 is provided. The wafer holder 40 includes a holder head 41 that holds the semiconductor wafer W downward and at its edge portion (peripheral portion), a drive arm 43 that vertically drives a rod 42 that supports the holder head 41 from above, and this drive arm 43. And an arm holder 45 for rotatably supporting the shaft around the support shaft 44. As a result, the film formation surface of the semiconductor wafer W held by the holder head 41 is arranged parallel to and facing the upper surface of the copper plate 14.

Further, the holder head 41 is provided with an electric terminal (not shown) in contact with the edge portion of the held semiconductor wafer W, and the negative electrode of the power source 34 is connected to this electric terminal. As will be described later, on the semiconductor wafer W to be copper-plated, a PVD method, a CVD method, or the like is used in advance.
A thin copper seed layer 105 is formed on the barrier metal film, and this seed layer 105 functions as a film formation surface and as a cathode. Further, the positive electrode (cathode) of the power source 34 is connected to the copper plate 14 so that the copper plate 14 functions as an anode. Furthermore, the power supply 34 is connected to the semiconductor wafer W, the power supply 34, and a control device 50 connected to an ammeter 51 and a voltmeter 52 provided in a conductive path connecting the copper plate 14. The control device 50 adjusts the output of the power supply 34, and performs stable control of voltage or current based on the instruction value of the ammeter 51 or the voltmeter 52.

The electroplating apparatus 10 thus constructed
5A to 5C in addition to FIGS. 1 to 4 for the plating method of the present invention for forming a copper film on a semiconductor wafer W by using 0.
And FIG. 6 will be described. 5 (A) to (C),
Changes in the plating current (trend line L1), changes in the plating voltage (trend line L2) when the semiconductor wafer W is plated by the plating method of the present invention, respectively.
9 is a time chart schematically showing an example of whether or not the rod 42 is tilted (trend line L3). In addition, FIG.
It is a schematic diagram which shows the partial cross section of the semiconductor wafer W plated by the plating method of this invention.

In FIGS. 5 (A) to 5 (C), the standard of the horizontal axis is, for example, 1 second for one scale, and axis labels (t0, t5, t10, t15, t20, t for every 5 scales).
25). Further, since the plating apparatus 100 performs face-down type plating film formation, the surface to be plated faces downward during the processing, but for convenience of explanation, FIG. 6 shows that the surface to be plated faces upward. (Same in FIG. 8 described later).

First, the pump 20 is driven to drive the plating solution 22.
Is supplied to the liquid tank 12 and circulated through the outer tank 24 and the tank 26. Next, the semiconductor wafer W is gripped by the holder head 41, and from time t0, the semiconductor wafer W is placed in the plating solution 22.
The rod 42 is driven so as to come to a predetermined position (dry position) above the liquid surface of. Here, the semiconductor wafer W
Is provided with a single-layer insulating layer 102 having holes H (recesses such as connection holes) formed on a conductive base layer 101, and further has a very thin Ta film 103 and 10n of about 15 nm thick.
A barrier metal film made of an extremely thin TaN film 104 of about m is formed, and a thin copper seed layer 105 of about 100 to 150 nm is further formed on the barrier metal film (see FIG. 6).

The plating solution will be described. Cupric sulfate is contained as a main component, and an additive for improving the filling property in the recesses such as the holes H is also added.
There are various types of additives, and examples thereof include so-called accelerators, suppressors, leveling agents, and the like.

The accelerator is a hole H having a minute gap in order to perform plating according to the shape of the surface of the hole H to be plated.
This is to promote bottom-up (embedding) due to the progress of the electrodeposition (reduction / electrodeposition) reaction of Cu ²⁺ ions inside. Generally, it has a lower molecular weight than the inhibitor described later and a relatively high diffusion transfer rate in the plating solution, and since the degree of intramolecular polarization is not as great as that of the inhibitor, it rapidly migrates into the recess. It tends to be easy and functions to promote bottom-up inside the recess.

Examples of such an accelerator include brighteners described in JP-A-2000-219994,
That is, bis (3-sulfopropyl) disulfide or its disodium salt, bis (2-sulfopropyl)
Disulfide or its disodium salt, bis (3-sul-2-hydroxypropyl) disulfide or its disodium salt, bis (4-sulfopropyl) disulfide or its disodium salt, bis (p-sulfophenyl) disulfide or its 2 Sodium salt, 3-
(Benzothiazolyl-2-thio) propylsulfonic acid or its sodium salt, N, N-dimethyl-dithiocarbamic acid- (3-sulfopropyl) -ester or its sodium salt, O-ethyl-diethyl carbonic acid-S- (3-sulfo Propyl) -ester or its potassium salt, thiourea or its derivative, or JP-A-2000-24
Sulfur-based saturated organic compounds described in 8397, that is, dithiobis-alkane-sulfonic acid or a salt thereof, specifically, 4,4-dithiobis-butane-sulfonic acid,
3,3-dithiobis-propane-sulfonic acid, 2,2-
Examples thereof include dithiobis-ethane-sulfonic acid and salts thereof, and these can be used alone or in combination of two or more.

On the other hand, the suppressor is for suppressing the excessive deposition (reduction / deposition) reaction due to the concentration of the plating current at the edge portion forming the minute gap of the hole H. In general, since the molecular weight is higher than that of the above-mentioned accelerator, the diffusion and migration speed in the plating solution is relatively slow, and the degree of intramolecular polarization is larger than that of the accelerator, the edge portion where the electric field is high It is easy to gather around the periphery of the hole and functions to further promote bottom-up inside the hole H by suppressing overhang of the edge portion.

As such an inhibitor, for example, JP-A-2000-219994 or JP-A-2000-24 is used.
8397, namely, polyvinyl alcohol, carboxymethyl cellulose, polyethylene glycol, polypropylene glycol, stearic acid-polyethylene glycol ester, stearyl alcohol-polyethylene glycol ether, nonylphenol-polyethylene glycol ether, octylphenol-polyethylene glycol ether, polyethylene- Propylene glycol, β-naphthol-polyethylene glycol ether and the like, 1,3-dioxolane polymer, polypropylene propanol, oxyl alkylene polymer, a copolymer of ethylene oxide and propylene oxide, or a derivative thereof may be mentioned. Or, two or more kinds can be mixed and used.

On the other hand, the flattening agent effectively functions at the stage of performing the plating film formation on the entire field on the hole H after the bottom-up inside the hole H as described above is completed. This is for ensuring the uniformity of the film surface level after film formation regardless of the shape. That is, if the effect of the accelerator continues even after bottoming up, the electrodeposition rate on the hole H becomes higher than the electrodeposition rate on the portion where the hole H is absent, so that the field in which the hole H is formed rises. There is a tendency. The flattening agent suppresses the effect of the accelerator in order to prevent such microloading of the electrodeposition rate (film formation rate), and realizes uniform electrodeposition (reduction / electrodeposition). , So to speak, functions as a second inhibitor.

As such a leveling agent, for example, a leveler described in JP-A-2000-219994, that is, an organic acid amide and an amine compound, specifically,
Acetamide, propylamide, benzamide, acrylamide, methacrylamide, N, N-dimethylacrylamide, N, N-diethylmethacrylamide,
N, N-diethylacrylamide, N, N-dimethylmethacrylamide, N- (hydroxymethyl) acrylamide, polyacrylic acid amide, polyacrylic acid amide hydrolyzate, thioflavin, safranine, and the like are listed, and these are used alone. Alternatively, two or more kinds may be mixed and used.

Then, the holder head 41 is further lowered to start the dipping process, and immediately after time t3, a voltage control signal is sent from the control device 50 to the power source 34, and a predetermined voltage is applied between the semiconductor wafer W and the copper plate 14. Ve (second voltage; FIG. 5)
In the example of (B), about 2.6 V) is applied. The value of Ve at this time is the voltage Vd (first voltage; FIG. 5) applied in the film forming process starting immediately after time t17 described later.
(About 2.6V in the example of (B)).

Then, when the holder head 41 descends to a predetermined position (time t9 to t10), the rod 42 is driven with the support shaft 44 as a fulcrum so that the rod 42 forms a certain angle (for example, about 3 to 15 °) from the vertical. The arm 43 and the holder head 41 are tilted. As a result, the semiconductor wafer W forms a constant angle with the liquid surface of the plating solution 22 (see FIG. 2). At this time, the voltage Ve is continuously applied by voltage control (see the trend line L2) to prevent the seed layer 105 of the semiconductor wafer W from being dissolved in the plating solution 22. At this time, since the electric terminals at the edge portion of the semiconductor wafer W are not yet immersed in the plating solution 22, a current does not flow, and the plating film is not formed on the seed layer 105.

Further, in this tilted state, the holder head 41
And the semiconductor wafer W is gradually immersed in the plating solution 22 (see FIG. 3). By immersing the semiconductor wafer W in the plating solution 22 in such a state that the semiconductor wafer W is tilted at a predetermined angle with respect to the horizontal, it is possible to prevent bubbles from being taken into the holes H of the semiconductor wafer W. Then, time t16
After a lapse of time, a current flows for a time Tm from the time when substantially the entire seed layer 105 on the semiconductor wafer W and the electric terminals in contact with the edge portion of the semiconductor wafer W are immersed in the plating solution 22. At this time, since the applied voltage Ve has the same magnitude as the voltage Vd in the film forming process, the flowing current value also becomes the same value as the appropriate current in the film forming process (3.3A in the example of FIG. 5A). Degree; see trend line L1). Therefore, it is possible to prevent copper from being excessively electrodeposited (electrodeposited) in the holes H of the semiconductor wafer W.

Next, the drive arm 43 and the holder head 41 are moved by using the support shaft 44 as a fulcrum so that the rod 42 faces the vertical direction, and the inclination is released. As a result, the semiconductor wafer W is held so as to be parallel to the copper plate 14 while being immersed in the plating solution 22, and the immersion process is completed (FIG. 4).
reference). At this time, the voltage application is momentarily stopped to switch from voltage control to current control, a current control signal is sent from the control device 50 to the power supply 34, and a predetermined voltage Vd (second voltage) is applied. Start the membrane process.

The plating current in this film forming process is shown in FIG.
As shown in (A), it is the same value as the current value flowing in the dipping process, and is about 3.3 A in the illustrated example (trend line L
1). As a result, the copper ions in the plating solution 22 stored in the solution tank 12 are reduced on the film formation surface (seed layer 105) of the semiconductor wafer W as the cathode. On this occasion,
Due to the effect of the accelerator and the inhibitor in the plating solution 22, the inside of the hole H is favorably filled with copper (bottom-up fill). Further, after the holes H are filled up by bottom-up, the field portion having excellent film thickness uniformity is formed by the action of the flattening agent. In this way, the wiring layer 106 (metal film) is formed, and the film forming process is completed.

As described above, in the dipping process, the applied voltage Vd that achieves the desired plating current in the film forming process.
By applying a voltage Ve equivalent to the above to prevent an excessive plating current from flowing, it is possible to prevent the hole H from being filled with copper, so that a void is generated inside the hole H of the wiring layer 106. Can be reliably prevented. Therefore, it is possible to effectively suppress the deterioration of the characteristics of the wiring layer 106 due to the defective filling of the holes H and the decrease of the product yield. In particular, it is possible to realize a plating method extremely suitable for manufacturing a next-generation device according to future design rules. it can.

Here, FIGS. 7A to 7C respectively show changes in the plating current (trend line L1) when the semiconductor wafer W is plated by the conventional method.
1), a change in plating voltage (trend line L12), and an example of whether or not the rod is tilted (trend line L13) are time charts, and FIG. 8 shows that plating is performed by the conventional method. It is a schematic diagram which shows the partial cross section of the semiconductor wafer W. The laminated structure of the semiconductor wafer W here is the same as that shown in FIG. 6, and the insulating layer 202 having the holes H formed on the conductive base layer 201, the Ta film 203, and the Ta film 203.
The N film 204 and the seed layer 205 are formed. In this conventional method, the applied voltage (see FIG.
In the example of (B), about 5 V) is set to about twice the applied voltage in the film forming process (about 2.6 V in the example of FIG. 7B).

As a result, a bottom void K may occur in the hole H as shown in FIG. This is because in the dipping process, when almost the entire semiconductor wafer W is dipped and becomes conductive, as shown in FIG. It is presumed that this is because the film formation inside H progresses at once and a state close to an overhang occurs.

On the other hand, in the present invention, by making the second voltage Ve applied in the dipping process equal to the first voltage Vd applied in the film forming process as in the above-described embodiment, It is possible to avoid improper embedding. Further, in the present invention,
Both voltages Ve and Vd are not limited to the same value, and the above equation (1)
The relationship represented by the following may be satisfied, that is, it is preferable that the second voltage Ve be a value within the range of + 15% to −20% of the first voltage Vd. As a result, it is possible to reliably prevent the seed layer 105 from dissolving in the plating solution 22, and to avoid the inconvenience such as the conventional void generation as shown in FIG. 8 even if the holes H are made finer than ever. it can. Further, in the case where the defective filling of the holes H occurs, the uniformity of the finally formed wiring layer surface within the semiconductor wafer W may deteriorate, whereas the present invention causes such a problem. It can be suppressed sufficiently.

Although the preferred embodiment of the present invention has been described above, it goes without saying that the present invention is not limited to the above embodiment. For example, the plating apparatus 100 is a face-down type in which the film formation surface of the semiconductor wafer W faces downward, but the present invention is also applicable to face-up type and other plating apparatuses, and the film forming material is other than copper. It can also be a metal. The present invention also provides 0.17 to 0.18μ.
It is very suitable for the production of next-generation devices of m or less, but may be applied to the production of devices of that size or larger. Furthermore, the voltage Ve may be applied immediately before the lower end of the semiconductor wafer W comes into contact with the plating solution 22. Further, although voltage control may be performed in the film forming step, current control is more preferable from the viewpoint of easily obtaining a stable constant current.

[0046]

As described above, according to the plating method of the present invention, when a copper film or the like is plated on an object to be processed such as a semiconductor wafer, the recesses such as holes formed on the object are processed. Embedding defects can be sufficiently prevented, which can prevent deterioration of the characteristics of the wiring layer and eventually the device (semiconductor device), and effectively suppress the deterioration of product yield.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a preferred embodiment of a plating apparatus for effectively carrying out the plating method according to the present invention, showing a state in which the plating apparatus is operating.

FIG. 2 is a schematic sectional view showing a preferred embodiment of a plating apparatus for effectively carrying out the plating method according to the present invention, showing a state in which the plating apparatus is operating.

FIG. 3 is a schematic cross-sectional view showing a preferred embodiment of a plating apparatus for effectively carrying out the plating method according to the present invention, showing a state in which the plating apparatus is operating.

FIG. 4 is a schematic cross-sectional view showing a preferred embodiment of a plating apparatus for effectively carrying out the plating method according to the present invention, showing a state in which the plating apparatus is operating.

5 (A) to 5 (C) respectively show changes in plating current, changes in plating voltage, and presence / absence of inclination of a rod when a semiconductor wafer is plated by the plating method of the present invention. It is a time chart which shows an example of typically.

FIG. 6 is a schematic view showing a partial cross section of a semiconductor wafer plated by the plating method of the present invention.

7A to 7C are each an example of a change in plating current, a change in plating voltage, and the presence or absence of inclination of a rod when a semiconductor wafer is plated by a conventional method. 2 is a time chart schematically showing.

FIG. 8: Semiconductor wafer W plated by a conventional method
It is a schematic diagram which shows the partial cross section of.

[Explanation of symbols]

12 ... Liquid tank, 14 ... Copper plate (source of film forming material), 21 ... Liquid tank,
22 ... Plating solution, 34 ... Power supply, 40 ... Wafer holder, 4
1 ... Holder head, 42 ... Rod, 43 ... Drive arm,
44 ... Spindle, 45 ... Arm holder, 50 ... Control device, 5
1 ... Ammeter, 52 ... Voltmeter, 100 ... Electroplating device,
101 ... Conductive base layer, 102 ... Insulating layer, 103 ... Ta
Film, 104 ... TaN film, 105 ... Seed layer (deposited surface), 106 ... Wiring layer (metal film), W ... Semiconductor wafer (processed object).

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yumi Suzuki             14-3 Shinizumi, Narita City, Chiba Prefecture Nogedaira Industrial Park               Applied Materials Japan Co., Ltd.             Inside the company (72) Inventor Shinro Owada             14-3 Shinizumi, Narita City, Chiba Prefecture Nogedaira Industrial Park               Applied Materials Japan Co., Ltd.             Inside the company (72) Inventor Masayuki Ashihara             14-3 Shinizumi, Narita City, Chiba Prefecture Nogedaira Industrial Park               Applied Materials Japan Co., Ltd.             Inside the company (72) Inventor Toshiyuki Nakagawa             14-3 Shinizumi, Narita City, Chiba Prefecture Nogedaira Industrial Park               Applied Materials Japan Co., Ltd.             Inside the company F term (reference) 4K024 AA09 BB12 CA05 CB02 GA16                 4M104 BB04 BB17 DD52 FF18 FF22

Claims (4)

[Claims] 1. A dipping step of immersing an object to be treated in a plating solution in a liquid tank in which a film-forming material source is arranged; and a state in which a film-forming surface of the object to be treated is immersed in the plating solution. A film forming step of forming a metal film on the film formation surface by an electrolytic plating method, and in the dipping step, the film forming material source as an anode and the cathode as a cathode in the film forming step. A second voltage having substantially the same magnitude as the first voltage applied between the film formation surface and the film formation surface is applied between the film formation material source and the film formation surface. Plating method. 2. A dipping step of immersing an object to be treated in a plating solution in a liquid tank in which a film-forming material source is arranged, and a state in which a film-forming surface of the object to be treated is immersed in the plating solution. And a film forming step of forming a metal film on the surface to be formed by electrolytic plating. In the dipping step, the following formula (1): 0.8 × Vd ≦ Ve ≦ 1.15 × Vd (1), Vd: a first voltage applied between the film forming material source as an anode and the film forming surface as a cathode in the film forming step, Ve: in the dipping step, A plating method, wherein voltage control is performed so as to satisfy a relationship represented by a second voltage applied between the film forming material source and the film formation surface. 3. The plating method according to claim 1, wherein the film forming material source is composed of a copper plate, and the object to be processed is a semiconductor wafer. 4. The dipping step, wherein the semiconductor wafer is gradually dipped in the plating solution in a state of being inclined at a predetermined angle from the horizontal with respect to the plating solution surface. Plating method.