JP2003124394A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2003124394A JP2003124394A JP2001320169A JP2001320169A JP2003124394A JP 2003124394 A JP2003124394 A JP 2003124394A JP 2001320169 A JP2001320169 A JP 2001320169A JP 2001320169 A JP2001320169 A JP 2001320169A JP 2003124394 A JP2003124394 A JP 2003124394A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- layer
- wiring
- semiconductor device
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は電子機器、通信装置
等に用いられる半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used in electronic equipment, communication devices and the like.
【０００２】[0002]
【従来の技術】半導体装置には、ＱＦＰパッケージ、Ｓ
ＯＰパッケージがあり、最近では、ＣＳＰ（Chip Size
Package）と呼ばれるベアチップのサイズと同等の小型
パッケージがある。これら半導体装置の再配線に関して
は、特開２０００−２３５９７９号公報に記載されたも
のが知られている。2. Description of the Related Art A semiconductor device includes a QFP package, an S
There is an OP package, and recently, CSP (Chip Size
There is a small package equivalent to the size of the bare chip called Package). Regarding the rewiring of these semiconductor devices, the one described in JP-A-2000-235979 is known.
【０００３】図９は従来の半導体装置の断面図を示した
ものであり、図１０は同平面図を示す。この半導体装置
はシリコン板１を備えている。このシリコン板１は図９
の一点鎖線で示すように、上面の四辺部を除く中央部を
回路素子形成領域２とされている。この回路素子形成領
域２内には例えば、この半導体装置がデータ通信用ＩＣ
である場合、高周波増幅器、発振回路、レギュレータ回
路、ベースバンド部等が設けられている。FIG. 9 is a sectional view of a conventional semiconductor device, and FIG. 10 is a plan view of the same. This semiconductor device includes a silicon plate 1. This silicon plate 1 is shown in FIG.
As indicated by the alternate long and short dash line, the central portion excluding the four side portions of the upper surface is the circuit element formation region 2. In the circuit element forming region 2, for example, the semiconductor device is a data communication IC.
In this case, a high frequency amplifier, an oscillator circuit, a regulator circuit, a base band unit, etc. are provided.
【０００４】この回路素子形成領域２の外側には、図９
に示す複数の接続パッド３ａ，３ｂが設けられている。
接続パッド３ａは、シリコン板１の上部に設けられた配
線層４ａの一端部と接続され、この配線層４ａを介して
上記データ通信用回路等と接続されている。接続パッド
３ｂは配線層４ｂの一端部と接続されている。配線層４
ｂはシリコン板１の上面に設けた酸化シリコン等からな
る第一の絶縁層５の上面に形成された接地電位層８と接
続パッド３ｂを介して接続されている。The outside of the circuit element forming region 2 is shown in FIG.
A plurality of connection pads 3a and 3b shown in are provided.
The connection pad 3a is connected to one end of a wiring layer 4a provided on the silicon plate 1, and is connected to the data communication circuit and the like via the wiring layer 4a. The connection pad 3b is connected to one end of the wiring layer 4b. Wiring layer 4
b is connected to the ground potential layer 8 formed on the upper surface of the first insulating layer 5 made of silicon oxide or the like provided on the upper surface of the silicon plate 1 via the connection pad 3b.
【０００５】次に、この接地電位層８は第二の絶縁層７
で覆われており、その上面には再配線層９が設けられて
いる。さらにこの再配線層９の上面に第三の絶縁層１０
が形成され、この第三の絶縁層１０の表面に再配線層９
と接続された柱状電極６ａ，６ｂの端面が露出してい
る。Next, the ground potential layer 8 is the second insulating layer 7
And the rewiring layer 9 is provided on the upper surface thereof. Furthermore, a third insulating layer 10 is formed on the upper surface of the redistribution layer 9.
Is formed, and the rewiring layer 9 is formed on the surface of the third insulating layer 10.
The end faces of the columnar electrodes 6a and 6b connected to the are exposed.
【０００６】以上のようにシリコン板１の回路素子形成
領域２内に設けられた発振回路等と再配線層９がクロス
しても、接地電位層８によりクロストークが発生しない
ようにし、再配線層９の配置に制約を受けないようにし
ている。As described above, even if the rewiring layer 9 crosses the oscillation circuit provided in the circuit element formation region 2 of the silicon plate 1, the ground potential layer 8 prevents crosstalk from occurring, and the rewiring is performed. The arrangement of the layer 9 is not restricted.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら従来、こ
のような半導体装置では、再配線するときの層間におけ
るアイソレーションを確保するために、回路素子形成領
域２上に接地電位層８をベタパターンで設けているの
で、配線層４ａ，４ｂと接地電位層８および再配線層９
と接地電位層８との間で寄生容量が発生する。高周波回
路を構成する場合、この寄生容量による信号の損失で高
周波回路の特性が劣化するという問題があった。However, conventionally, in such a semiconductor device, the ground potential layer 8 is provided in a solid pattern on the circuit element formation region 2 in order to secure isolation between layers at the time of rewiring. The wiring layers 4a and 4b, the ground potential layer 8 and the rewiring layer 9
A parasitic capacitance is generated between the ground potential layer 8 and the ground potential layer 8. In the case of configuring a high frequency circuit, there is a problem that the characteristics of the high frequency circuit are deteriorated by the signal loss due to this parasitic capacitance.
【０００８】本発明は配線層と接地電位層との間の寄生
容量および再配線層と接地電位層との間の寄生容量を抑
制することにより、信号の損失を防ぐことのできる半導
体装置を提供することを目的とする。The present invention provides a semiconductor device capable of preventing signal loss by suppressing parasitic capacitance between a wiring layer and a ground potential layer and parasitic capacitance between a rewiring layer and a ground potential layer. The purpose is to do.
【０００９】[0009]
【課題を解決するための手段】本発明の請求項１に記載
の発明は、回路素子が形成された半導体板と、この半導
体板の上面に形成された少なくとも２つの第一および第
二の接続パッドと、この第一および第二の接続パッドを
覆うように前記半導体板上に形成された第一の絶縁層
と、この第一の絶縁層上に形成されその一端が前記第一
の接続パッドと電気的に接続された第一の配線層と、こ
の第一の配線層を覆うように前記第一の絶縁層上に形成
された第二の絶縁層と、この第二の絶縁層上に形成され
その一端が前記第二の接続パッドと電気的に接続された
第二の配線層と、この第二の配線層を覆うように前記第
二の絶縁層上に形成された封止樹脂とを備え、前記第一
および第二の配線層の所定個所よりそれぞれ導体からな
る第一および第二の導体ポストが前記封止樹脂の表面か
ら露出することにより第一および第二の電極部を形成
し、第一の配線層が少なくとも１つの接続パッドの接地
電位層と接続され前記第一の配線層が格子形状に空孔を
もつように形成し、この格子形状の空孔の対角線の距離
が波長の８分の１以下としたものである。According to a first aspect of the present invention, there is provided a semiconductor plate having a circuit element formed thereon, and at least two first and second connections formed on an upper surface of the semiconductor plate. A pad, a first insulating layer formed on the semiconductor plate so as to cover the first and second connection pads, and one end of the first connection layer formed on the first insulating layer A first wiring layer electrically connected to the second wiring layer, a second insulating layer formed on the first insulating layer so as to cover the first wiring layer, and a second insulating layer on the second insulating layer. A second wiring layer having one end electrically connected to the second connection pad, and a sealing resin formed on the second insulating layer so as to cover the second wiring layer. The first and second wiring layers, each of which is made of a conductor from a predetermined portion of the first and second wiring layers. The first and second electrode portions are formed by exposing the body post from the surface of the sealing resin, and the first wiring layer is connected to the ground potential layer of at least one connection pad. Are formed to have holes in a lattice shape, and the distance of the diagonal line of the holes in the lattice shape is set to 1/8 or less of the wavelength.
【００１０】この構成によれば、第一の配線層を格子形
状に空孔をもつように形成し、格子形状の空孔の対角線
の距離が波長の８分の１以下とすることで、この波長よ
りも低い周波数の定在波は生じないために、第一の配線
層の上下でアイソレーションを確保できる。さらに、第
一の配線層は格子形状に空孔が形成されているために、
ベタパターンに比べ第二の配線層との間に生じる寄生容
量を大幅に低減できる。したがって、半導体板上の回路
の配置に制約を受けず再配線が可能となり、同時に寄生
容量による信号の損失を抑制することができる。According to this structure, the first wiring layer is formed so as to have holes in a lattice shape, and the distance between the diagonal lines of the lattice-shaped holes is 1/8 or less of the wavelength. Since a standing wave having a frequency lower than the wavelength does not occur, isolation can be secured above and below the first wiring layer. Furthermore, since the first wiring layer has holes formed in a lattice shape,
Parasitic capacitance generated between the second wiring layer and the solid pattern can be significantly reduced. Therefore, rewiring is possible without being restricted by the arrangement of circuits on the semiconductor plate, and at the same time, it is possible to suppress signal loss due to parasitic capacitance.
【００１１】さらに、格子形状に空孔を有するパターン
とした場合、接地電位層である第一の配線層をベタパタ
ーンで構成する場合に比べ、接着部分の凹凸が多く、層
間での密着強度の向上が可能となる。Further, in the case where the pattern having holes in the lattice shape is used, compared to the case where the first wiring layer, which is the ground potential layer, is composed of a solid pattern, there are more irregularities in the bonding portion, and the adhesion strength between the layers is improved. It is possible to improve.
【００１２】請求項２に記載の発明は、第一の配線層が
接続パッドの接地電位層と接続され、第一の配線層が丸
形の空孔を多数もつように形成し、この空孔の直径が波
長の８分の１以下としたものである。According to a second aspect of the present invention, the first wiring layer is connected to the ground potential layer of the connection pad, and the first wiring layer is formed so as to have a large number of round holes. Has a diameter equal to or less than 1/8 of the wavelength.
【００１３】この構成によれば、空孔の直径をアイソレ
ーションを確保したい周波数の波長の８分の１以下に構
成したために、これよりも波長の長い周波数の定在波は
発生しない。このため、第一の配線層の上下でアイソレ
ーションが確保でき、半導体板上の回路と第二の配線層
の間でアイソレーションが確保できるため、半導体板上
の回路配置による制約を受けずに、第二の配線層での配
線が可能となる。また、第一の配線層のパターンを丸形
の空孔を多数有する構成としているために、第一の配線
層と半導体板上の回路パターンや、第一の配線層と第二
にの配線層との間に生じる寄生容量を大幅に低減でき、
容量による信号の結合や損失を防ぐことができる。ま
た、格子形状に空孔を設けるパターンを形成する場合に
比べ、丸形の空孔を多数設けることにより、空孔の面積
がより大きくなるために、寄生容量はさらに小さくでき
る。According to this structure, since the diameter of the hole is set to ⅛ or less of the wavelength of the frequency for which the isolation is desired to be secured, the standing wave of the frequency longer than this is not generated. Therefore, the isolation can be secured above and below the first wiring layer, and the isolation can be secured between the circuit on the semiconductor plate and the second wiring layer, so that there is no restriction due to the circuit arrangement on the semiconductor plate. The wiring in the second wiring layer becomes possible. Further, since the pattern of the first wiring layer is configured to have a large number of round holes, the circuit pattern on the first wiring layer and the semiconductor plate, the first wiring layer and the second wiring layer Can significantly reduce the parasitic capacitance generated between
It is possible to prevent signal coupling and loss due to capacitance. Further, as compared with the case of forming a pattern in which holes are formed in a lattice shape, by providing a large number of round holes, the area of the holes becomes larger, so that the parasitic capacitance can be further reduced.
【００１４】さらに、接地電位層をベタパターンで構成
する場合に比べ、接着部分の凹凸が多く、層間での密着
強度の向上が可能となる。Further, as compared with the case where the ground potential layer is composed of a solid pattern, there are more irregularities in the bonded portion, and the adhesion strength between the layers can be improved.
【００１５】請求項３に記載の発明は、第一の配線層が
第二の配線層よりも導電率の低い材料で構成されている
ものである。この構成によれば、第一の配線層と半導体
板、第一の配線層と第二の配線層の容量成分に抵抗成分
が付加される。付加される抵抗成分が大きければ、容量
値は変わらなくとも容量成分としての影響は小さくなる
ために層間での容量の影響は小さくなる。したがって容
量による信号の結合や損失を防ぐことができ、再配線に
よる信号の損失、結合を抑制できる。According to a third aspect of the present invention, the first wiring layer is made of a material having a conductivity lower than that of the second wiring layer. According to this configuration, the resistance component is added to the capacitance components of the first wiring layer and the semiconductor plate, and the first wiring layer and the second wiring layer. If the added resistance component is large, even if the capacitance value does not change, the influence as the capacitance component becomes small, so that the influence of the capacitance between the layers becomes small. Therefore, signal coupling and loss due to capacitance can be prevented, and signal loss and coupling due to rewiring can be suppressed.
【００１６】請求項４に記載の発明は、第一の絶縁層の
厚みが第一の配線層よりも厚くしたものである。この構
成によれば、第一の絶縁層の厚みを大きくすることによ
り半導体板上の回路パターンと第一の配線層に生じる容
量成分を小さくでき、層間の容量による信号の結合や損
失を防ぐことができ、再配線による信号の損失、結合を
抑制できる。According to a fourth aspect of the present invention, the first insulating layer is thicker than the first wiring layer. According to this configuration, by increasing the thickness of the first insulating layer, it is possible to reduce the capacitance component generated in the circuit pattern on the semiconductor plate and the first wiring layer, and prevent signal coupling or loss due to capacitance between layers. Therefore, signal loss and coupling due to rewiring can be suppressed.
【００１７】請求項５に記載の発明は、第二の絶縁層の
厚みが第二の配線層よりも厚くしたものである。この構
成によれば、第一の配線層と第二の配線層に生じる容量
成分を小さくでき、層間の容量による信号の結合や損失
を防ぐことができる。According to a fifth aspect of the present invention, the second insulating layer is thicker than the second wiring layer. With this configuration, it is possible to reduce the capacitance component generated in the first wiring layer and the second wiring layer, and it is possible to prevent signal coupling and loss due to the capacitance between the layers.
【００１８】請求項６に記載の発明は、第一の配線層が
接続パッドの接地電位層と接続され、配線層が波長の８
分の１以下で構成された丸形の空孔を多数有した形状ま
たは対角線の長さが波長の８分の１以下に構成された格
子状の空孔を有した形状とし、この空孔の中央を介して
半導体板上の回路と第二の配線層が接続されたものであ
る。したがって、半導体板上の回路と第二の配線層の接
続を任意の空孔の中央部分で行えるために配線の引き回
しを小さくすることができる。このため、引き回しによ
る寄生容量の発生を抑制でき、信号の結合や損失を防ぐ
ことができる。According to a sixth aspect of the invention, the first wiring layer is connected to the ground potential layer of the connection pad, and the wiring layer has a wavelength of 8 nm.
A shape having a large number of round holes made up of one-half or less, or a shape having lattice-like holes made up of a length of a diagonal of one-eighth or less of the wavelength. The circuit on the semiconductor plate and the second wiring layer are connected via the center. Therefore, the circuit on the semiconductor plate and the second wiring layer can be connected to each other at the central portion of the hole, so that the routing of the wiring can be reduced. Therefore, generation of parasitic capacitance due to routing can be suppressed, and signal coupling and loss can be prevented.
【００１９】[0019]
【発明の実施の形態】（実施の形態１）図１は本発明の
実施の形態１における半導体装置の断面図であり、図２
はその平面図を示したものである。この半導体装置は半
導体板としてのシリコン板１を備えている。シリコン板
１は、図２に示すように平面正方形状であって、一点鎖
線で示すように上面の四辺部を除く中央部を回路素子形
成領域２としている。この回路素子形成領域２内には、
例えばこの半導体装置がデータ通信用ＩＣである場合、
高周波増幅器、発振回路、レギュレータ回路、ベースバ
ンド部等で構成されている。(First Embodiment) FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.
Shows the plan view. This semiconductor device includes a silicon plate 1 as a semiconductor plate. The silicon plate 1 has a square shape in a plane as shown in FIG. 2, and has a circuit element forming region 2 at the central portion excluding the four side portions of the upper surface as shown by a chain line. In this circuit element formation region 2,
For example, when this semiconductor device is a data communication IC,
It is composed of a high-frequency amplifier, an oscillation circuit, a regulator circuit, a baseband unit, and the like.
【００２０】シリコン板１の上面の回路素子形成領域２
の外側には、第一の接続パッド３ａが設けられている。
シリコン板１の上面にはシリコン板を覆うように第一の
絶縁層５が設けられ、さらに、この第一の絶縁層５上に
設けられた第一の配線層１１の上面にはこの第一の配線
層１１を覆うように第二の絶縁層７が形成され、この第
二の絶縁層７上には一端が第二の接続パッド３ｂと電気
的に接続された第二の配線層１２が形成されている。前
記第二の絶縁層７と第二の配線層１２を覆うように封止
樹脂１３を備え、第一および第二の配線層１１，１２の
所定個所にそれぞれ電気導体材料からなる第一および第
二の導体ポスト１４ａ，１４ｂが前記封止樹脂１３の表
面に露出するように設けられて第一および第二の電極部
を形成している。A circuit element forming region 2 on the upper surface of the silicon plate 1.
A first connection pad 3a is provided on the outer side of.
A first insulating layer 5 is provided on the upper surface of the silicon plate 1 so as to cover the silicon plate, and the first wiring layer 11 provided on the first insulating layer 5 has the first insulating layer 5 on the upper surface. The second insulating layer 7 is formed so as to cover the wiring layer 11 and the second wiring layer 12 whose one end is electrically connected to the second connection pad 3b is formed on the second insulating layer 7. Has been formed. A sealing resin 13 is provided so as to cover the second insulating layer 7 and the second wiring layer 12, and the first and second wiring layers 11 and 12 are made of an electric conductor material at predetermined locations. The second conductor posts 14a and 14b are provided so as to be exposed on the surface of the sealing resin 13 to form first and second electrode portions.
【００２１】ここで、第一の配線層１１は格子形状に空
孔をもつパターンに形成された接地電位層であり、格子
形状の空孔の対角線の距離１５は、アイソレーションを
確保したい周波数の波長の８分の１以下に構成されてい
る。Here, the first wiring layer 11 is a ground potential layer formed in a pattern having lattice-shaped holes, and the diagonal distance 15 of the lattice-shaped holes is the frequency at which isolation is desired to be secured. It is configured to be ⅛ or less of the wavelength.
【００２２】このようにこの半導体装置では、接地電位
層である第一の配線層１１のパターンを格子形状に空孔
を有した形状とし、格子形状の空孔の対角線の距離１５
をアイソレーションを確保したい周波数の波長の８分の
１以下に構成したために、この波長よりも波長の長い周
波数の定在波は発生しない。このため、第一の配線層１
１の上下でアイソレーションが確保でき、シリコン板１
の上部の回路素子形成領域２に構成された発振器等の回
路と第二の配線層１２の間でアイソレーションが確保で
きるため、シリコン板１上の回路配置による制約を受け
ずに、第二の配線層１２での配線が可能となる。As described above, in this semiconductor device, the pattern of the first wiring layer 11, which is the ground potential layer, is formed in the shape of a lattice having holes, and the distance 15 between diagonal lines of the lattice-shaped holes is 15.
Is configured to be ⅛ or less of the wavelength of the frequency for which isolation is desired to be secured, so that a standing wave having a frequency longer than this wavelength is not generated. Therefore, the first wiring layer 1
Isolation can be secured above and below 1, silicon plate 1
Since isolation can be ensured between the circuit such as the oscillator formed in the circuit element formation region 2 on the upper part of the second wiring layer 12 and the second wiring layer 12, the second circuit layer 12 is not restricted by the circuit arrangement on the silicon plate 1 and Wiring in the wiring layer 12 becomes possible.
【００２３】また、シリコン板１上の回路素子形成領域
２と第一の配線層１１との間に生じる寄生容量および第
一の配線層１１と第２の配線層１２との間に生じる寄生
容量を大幅に低減でき、容量による信号の結合や損失を
防ぐことができる。さらに、格子形状に空孔を有したパ
ターンとすることで、第一の配線層１１をベタパターン
で構成する場合に比べて、接着部分の凹凸が多く、層間
での密着強度の向上が可能となる。Further, the parasitic capacitance generated between the circuit element forming region 2 on the silicon plate 1 and the first wiring layer 11 and the parasitic capacitance generated between the first wiring layer 11 and the second wiring layer 12. Can be significantly reduced, and signal coupling and loss due to capacitance can be prevented. Further, by forming a pattern having holes in a lattice shape, compared to the case where the first wiring layer 11 is formed of a solid pattern, there are more irregularities in the bonding portion, and it is possible to improve the adhesion strength between layers. Become.
【００２４】（実施の形態２）図３は本発明の実施の形
態２における半導体装置の平面図である。この半導体装
置では、実施の形態１で説明した図１の第一の配線層１
１が丸形の空孔を多数備えた形状に形成されている。空
孔の直径は、アイソレーションを確保したい周波数の波
長の８分の１以下に構成されている。(Second Embodiment) FIG. 3 is a plan view of a semiconductor device according to a second embodiment of the present invention. In this semiconductor device, the first wiring layer 1 of FIG. 1 described in the first embodiment is used.
1 is formed in a shape having a large number of round holes. The diameter of the hole is configured to be ⅛ or less of the wavelength of the frequency for which isolation is desired to be ensured.
【００２５】このように、この半導体装置では、接地電
位層である第一の配線層１１のパターンを丸形の空孔を
多数有した形状とし、空孔の直径１６をアイソレーショ
ンを確保したい周波数の波長の８分の１以下に構成した
ために、これよりも波長の長い周波数の定在波は発生し
ない。このため、第一の配線層１１の上下でアイソレー
ションが確保でき、シリコン板１上の回路配置による制
約を受けずに第二の配線層１２での配線が可能となる。As described above, in this semiconductor device, the pattern of the first wiring layer 11 that is the ground potential layer is formed into a shape having a large number of round holes, and the diameter 16 of the holes is the frequency at which isolation is desired to be ensured. Since it is configured to be ⅛ or less of the wavelength, the standing wave having a frequency longer than this is not generated. Therefore, isolation can be secured above and below the first wiring layer 11, and wiring can be performed on the second wiring layer 12 without being restricted by the circuit arrangement on the silicon plate 1.
【００２６】また、第一の配線層１１のパターンを直径
が波長の８分の１以下の空孔を多数有する構成としてい
るため、格子形状に空孔を有するパターンを構成した場
合に比べ、空孔の面積がより大きくなる。このため、第
一の配線層１１とシリコン板１上の回路パターンや、第
一の配線層１１と第二の配線層１２との間に生じる寄生
容量を格子形状の空孔を有するパターンに比べ低減で
き、信号の結合や損失を防ぐことができる。さらに、丸
形の空孔を有するパターンとした場合、接地電位層であ
る第一の配線層１１をベタパターンで構成する場合に比
べ、接着部分の凹凸が多く層間での密着強度の向上が可
能となる。Further, since the pattern of the first wiring layer 11 has a large number of holes each having a diameter of ⅛ or less of the wavelength, compared to the case where the pattern having holes in a lattice shape is formed, The area of the hole becomes larger. Therefore, as compared with the circuit pattern on the first wiring layer 11 and the silicon plate 1 and the parasitic capacitance generated between the first wiring layer 11 and the second wiring layer 12 as compared with the pattern having the lattice-shaped holes. It can be reduced, and the coupling and loss of signals can be prevented. Further, when the pattern having the round holes is formed, compared to the case where the first wiring layer 11 which is the ground potential layer is formed by the solid pattern, the unevenness of the bonding portion is large and the adhesion strength between the layers can be improved. Becomes
【００２７】（実施の形態３）図４は本発明の実施の形
態３における半導体装置の断面図であり、第二の絶縁層
７と第二の配線層１２を覆うように封止樹脂１３を備
え、第一の配線層１１および第二の配線層１２の所定個
所よりそれぞれ電気導体材料からなる第一の導体ポスト
１４ａおよび第二の導体ポスト１４ｂが前記封止樹脂１
３の表面から露出している。(Third Embodiment) FIG. 4 is a sectional view of a semiconductor device according to a third embodiment of the present invention, in which a sealing resin 13 is provided so as to cover the second insulating layer 7 and the second wiring layer 12. The first conductor post 14a and the second conductor post 14b, which are made of an electric conductor material, are provided at predetermined positions of the first wiring layer 11 and the second wiring layer 12, respectively.
It is exposed from the surface of 3.
【００２８】この半導体装置では、第一の配線層１１が
第二の配線層１２よりも導電率の低い材料で構成されて
いる。第二の配線層１２およびシリコン板１上の回路素
子形成領域２の配線は通常銅等の導電率の高い材料で構
成されるが、この場合、第一の配線層１１はより導電率
の低いクロム、スズ、ストロンチウム、ビスマス、ニク
ロム、ニッケル、白金ロジウム等で構成する。In this semiconductor device, the first wiring layer 11 is made of a material having a conductivity lower than that of the second wiring layer 12. The wiring of the second wiring layer 12 and the circuit element formation region 2 on the silicon plate 1 is usually made of a material having a high conductivity such as copper, but in this case, the first wiring layer 11 has a lower conductivity. It is composed of chromium, tin, strontium, bismuth, nichrome, nickel, platinum rhodium and the like.
【００２９】このように、この半導体装置では、第一の
配線層１１が第二の配線層１２よりも導電率の低い材料
で構成したために、第一の配線層１１と第二の配線層１
２およびシリコン板１のパターンと第一の配線層１１に
生じる容量成分に対して配線層の抵抗成分が付加され
る。付加される抵抗成分が大きければ、容量値は変わら
なくとも容量成分としての影響は小さくなるために、層
間での容量の影響は小さくなるため容量による信号の結
合や損失を防ぐことができる。As described above, in this semiconductor device, since the first wiring layer 11 is made of a material having a lower conductivity than the second wiring layer 12, the first wiring layer 11 and the second wiring layer 1 are formed.
2 and the resistance component of the wiring layer is added to the capacitance component generated in the pattern of the silicon plate 1 and the first wiring layer 11. If the added resistance component is large, the influence as the capacitance component is small even if the capacitance value does not change. Therefore, the influence of the capacitance between the layers becomes small, so that the coupling or loss of signals due to the capacitance can be prevented.
【００３０】また、第一の配線層１１を接地電位層とし
て使用する場合、接地電位層の面積を大きく構成するこ
とで抵抗成分の影響は無視できる。When the first wiring layer 11 is used as the ground potential layer, the influence of the resistance component can be ignored by increasing the area of the ground potential layer.
【００３１】（実施の形態４）図５は本発明の実施の形
態４における半導体装置の断面図である。第一の絶縁層
５の厚みが第一の配線層１１よりも厚く構成されてい
る。容量成分は電極間の厚みに反比例することから、厚
みを大きくすることにより容量成分を小さくできる。し
たがって、シリコン板１のパターンと第一の配線層１１
に生じる容量成分を小さくでき、層間の容量による信号
の結合や損失を防ぐことができる。第一絶縁層５にはポ
リイミド等が使用され、層厚は数μｍで構成している。(Fourth Embodiment) FIG. 5 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention. The first insulating layer 5 is thicker than the first wiring layer 11. Since the capacitance component is inversely proportional to the thickness between the electrodes, it is possible to reduce the capacitance component by increasing the thickness. Therefore, the pattern of the silicon plate 1 and the first wiring layer 11
It is possible to reduce the capacitance component generated in the above, and to prevent signal coupling and loss due to capacitance between layers. Polyimide or the like is used for the first insulating layer 5, and the layer thickness is several μm.
【００３２】（実施の形態５）図６は本発明の実施の形
態５における半導体装置の断面図である。この半導体装
置では、第二の絶縁層７の厚みが第二の配線層１２より
も厚く構成されている。容量成分は電極間の厚みに反比
例することから、厚みを大きくすることにより容量成分
を小さくできる。したがって、シリコン板１のパターン
と第一の配線層１１に生じる容量成分を小さくでき、層
間の容量による信号の結合や損失を防ぐことができ、シ
リコン板１の回路配置に影響されずに再配線をすること
が可能となる。(Fifth Embodiment) FIG. 6 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention. In this semiconductor device, the second insulating layer 7 is thicker than the second wiring layer 12. Since the capacitance component is inversely proportional to the thickness between the electrodes, it is possible to reduce the capacitance component by increasing the thickness. Therefore, the capacitance component generated in the pattern of the silicon plate 1 and the first wiring layer 11 can be reduced, signal coupling and loss due to the capacitance between layers can be prevented, and the rewiring can be performed without being affected by the circuit arrangement of the silicon plate 1. It becomes possible to
【００３３】（実施の形態６）図７は本発明の実施の形
態６における半導体装置の断面図であり、図８はその平
面図である。この半導体装置では、第一の配線層１１が
接続パッド３ａによりシリコン板１上の接地電位層であ
る配線層４ａと接続され、前記第一の配線層１１が直径
１６が波長の８分の１以下で構成された丸形の空孔を多
数有した形状に形成され、この空孔の中央を介してシリ
コン板１上の配線層４ｂと第二の配線層１２が接続パッ
ド３ｂにより接続されたものである。したがって、シリ
コン板１上の回路と第二の配線層１２の接続を任意の空
孔の中央部分に行えるために配線の引き回しを小さくす
ることができる。このため、引き回しによる寄生容量の
発生を抑制でき、信号の結合や損失を防ぐことができ
る。(Sixth Embodiment) FIG. 7 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention, and FIG. 8 is a plan view thereof. In this semiconductor device, the first wiring layer 11 is connected to the wiring layer 4a which is the ground potential layer on the silicon plate 1 by the connection pad 3a, and the first wiring layer 11 has the diameter 16 of 1/8 of the wavelength. The wiring layer 4b on the silicon plate 1 and the second wiring layer 12 are connected to each other by the connection pad 3b through the center of these holes, which are formed to have a large number of round holes. It is a thing. Therefore, since the circuit on the silicon plate 1 and the second wiring layer 12 can be connected to the central portion of an arbitrary hole, the wiring can be reduced. Therefore, generation of parasitic capacitance due to routing can be suppressed, and signal coupling and loss can be prevented.
【００３４】[0034]
【発明の効果】以上のように本発明によれば、回路素子
が形成された半導体板と接地電位層である第一の配線層
の間に第一の絶縁層を設け、第一の配線層と第二の配線
層の間に第二の絶縁層を設け、かつ接地電位層の空孔を
有するパターンの空孔の対角線の距離を波長の８分の１
以下とした構造としているので、接地電位層の上下でア
イソレーションを確保でき、かつ、層間の容量成分の抑
制ができる。したがって、再配線時に配置に制約を受け
ずにアイソレーションの確保と浮遊容量の抑制を実現す
ることができる。As described above, according to the present invention, the first insulating layer is provided between the semiconductor plate on which the circuit element is formed and the first wiring layer which is the ground potential layer. The second insulating layer is provided between the second wiring layer and the second wiring layer, and the distance of the diagonal line of the hole having the hole of the ground potential layer is ⅛ of the wavelength.
Since the structure is as follows, it is possible to secure isolation above and below the ground potential layer and suppress the capacitance component between layers. Therefore, it is possible to secure the isolation and suppress the stray capacitance without being restricted in the layout at the time of rewiring.
【図１】本発明の実施の形態１による半導体装置を示す
断面図FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の実施の形態１による半導体装置を示す
平面図FIG. 2 is a plan view showing the semiconductor device according to the first embodiment of the present invention.
【図３】本発明の実施の形態２による半導体装置を示す
平面図FIG. 3 is a plan view showing a semiconductor device according to a second embodiment of the present invention.
【図４】本発明の実施の形態３による半導体装置を示す
断面図FIG. 4 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.
【図５】本発明の実施の形態４による半導体装置を示す
断面図FIG. 5 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.
【図６】本発明の実施の形態５による半導体装置を示す
断面図FIG. 6 is a sectional view showing a semiconductor device according to a fifth embodiment of the present invention.
【図７】本発明の実施の形態６による半導体装置を示す
断面図FIG. 7 is a sectional view showing a semiconductor device according to a sixth embodiment of the present invention.
【図８】本発明の実施の形態６による半導体装置を示す
平面図FIG. 8 is a plan view showing a semiconductor device according to a sixth embodiment of the present invention.
【図９】従来の半導体装置を示す断面図FIG. 9 is a sectional view showing a conventional semiconductor device.
【図１０】従来の半導体装置を示す平面図FIG. 10 is a plan view showing a conventional semiconductor device.
１ シリコン板 ２ 回路素子形成領域 ３ａ，３ｂ 接続パッド ４ａ，４ｂ 配線層 ５ 第一の絶縁層 ６ａ，６ｂ 電極 ７ 第二の絶縁層 ８ 接地電位層 ９ 再配線層 １０ 第三の絶縁層 １１ 第一の配線層 １２ 第二の配線層 １３ 封止樹脂 １４ａ，１４ｂ 導体ポスト １５ 距離 １６ 直径 1 Silicon plate 2 Circuit element formation area 3a, 3b connection pad 4a, 4b wiring layer 5 First insulating layer 6a, 6b electrodes 7 Second insulating layer 8 Ground potential layer 9 Rewiring layer 10 Third insulating layer 11 First wiring layer 12 Second wiring layer 13 Sealing resin 14a, 14b Conductor post 15 distance 16 diameter
───────────────────────────────────────────────────── フロントページの続き (72)発明者 安保 武雄 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Ｆターム(参考） 5F033 HH07 HH17 MM22 RR22 VV05 VV07 XX24 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Takeo Anbo 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Sangyo Co., Ltd. F term (reference) 5F033 HH07 HH17 MM22 RR22 VV05 VV07 XX24
Claims (6)
半導体板の上面に形成された少なくとも２つの第一およ
び第二の接続パッドと、この第一および第二の接続パッ
ドを覆うように前記半導体板上に形成された第一の絶縁
層と、この第一の絶縁層上に形成されその一端が前記第
一の接続パッドと電気的に接続された第一の配線層と、
この第一の配線層を覆うように前記第一の絶縁層上に形
成された第二の絶縁層と、この第二の絶縁層上に形成さ
れその一端が前記第二の接続パッドと電気的に接続され
た第二の配線層と、この第二の配線層を覆うように前記
第二の絶縁層上に形成された封止樹脂とを備え、前記第
一および第二の配線層の所定個所よりそれぞれ導体から
なる第一および第二の導体ポストが前記封止樹脂の表面
から露出することにより第一および第二の電極部を形成
し、第一の配線層が少なくとも１つの接続パッドの接地
電位層と接続され、前記第一の配線層が格子形状に空孔
をもつように形成し、この格子形状の空孔の対角線の距
離が波長の８分の１以下とした半導体装置。1. A semiconductor plate having a circuit element formed thereon, at least two first and second connection pads formed on an upper surface of the semiconductor plate, and a first plate and a second connection pad so as to cover the first and second connection pads. A first insulating layer formed on the semiconductor plate, and a first wiring layer formed on the first insulating layer and one end of which is electrically connected to the first connection pad,
A second insulating layer formed on the first insulating layer so as to cover the first wiring layer, and one end of the second insulating layer formed on the second insulating layer electrically connects to the second connection pad. A second wiring layer connected to the second wiring layer, and a sealing resin formed on the second insulating layer so as to cover the second wiring layer, and the predetermined wiring pattern of the first and second wiring layers. First and second conductor posts, each of which is made of a conductor, are exposed from the surface of the sealing resin to form first and second electrode portions, and the first wiring layer has at least one connection pad. A semiconductor device connected to a ground potential layer, wherein the first wiring layer is formed so as to have holes in a lattice shape, and a distance of a diagonal line of the lattice-shaped holes is ⅛ or less of a wavelength.
と接続され、この第一の配線層が多数の丸形の空孔をも
つように形成し、この空孔の直径が波長の８分の１以下
とした請求項１に記載の半導体装置。2. The first wiring layer is connected to the ground potential layer of the connection pad, and the first wiring layer is formed so as to have a large number of round holes, and the diameter of these holes is the wavelength. The semiconductor device according to claim 1, wherein the semiconductor device is ⅛ or less.
率の低い材料で構成された請求項１に記載の半導体装
置。3. The semiconductor device according to claim 1, wherein the first wiring layer is made of a material having a conductivity lower than that of the second wiring layer.
も厚くした請求項１に記載の半導体装置。4. The semiconductor device according to claim 1, wherein the first insulating layer is thicker than the first wiring layer.
も厚くした請求項１に記載の半導体装置。5. The semiconductor device according to claim 1, wherein the second insulating layer is thicker than the second wiring layer.
と接続され、配線層が直径が波長の８分の１以下で構成
された丸形の空孔を多数備えた形状または対角線の長さ
が波長の８分の１以下に構成された格子形状の空孔をも
つパターンに形成され、この空孔の中央を介して半導体
板上の回路と第二の配線層が接続された請求項１に記載
の半導体装置。6. The first wiring layer is connected to the ground potential layer of the connection pad, and the wiring layer has a shape or a diagonal line having a large number of round holes each having a diameter of ⅛ or less of the wavelength. A pattern having a lattice-shaped hole having a length equal to or shorter than ⅛ of a wavelength is formed, and the circuit on the semiconductor plate and the second wiring layer are connected through the center of the hole. Item 2. The semiconductor device according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001320169A JP4000815B2 (en) | 2001-10-18 | 2001-10-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001320169A JP4000815B2 (en) | 2001-10-18 | 2001-10-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003124394A true JP2003124394A (en) | 2003-04-25 |
| JP4000815B2 JP4000815B2 (en) | 2007-10-31 |
Family
ID=19137601
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001320169A Expired - Fee Related JP4000815B2 (en) | 2001-10-18 | 2001-10-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4000815B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008218494A (en) * | 2007-02-28 | 2008-09-18 | Casio Comput Co Ltd | Semiconductor device and its manufacturing method |
| JP2010093307A (en) * | 2010-01-29 | 2010-04-22 | Casio Computer Co Ltd | Semiconductor device |
| JP2011249862A (en) * | 2010-05-21 | 2011-12-08 | Nec Tokin Corp | Noise suppression transmission channel and sheet-like structure used for it |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0897557A (en) * | 1994-07-28 | 1996-04-12 | Fujitsu Ltd | Multilayered thin film wiring board |
| JPH09289214A (en) * | 1996-04-24 | 1997-11-04 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacturing method thereof |
| JPH11177247A (en) * | 1997-12-15 | 1999-07-02 | Ngk Spark Plug Co Ltd | Wiring board |
| JP2000507427A (en) * | 1996-03-25 | 2000-06-13 | サムシュング・エレクトロニクス・カンパニー・リミテッド | Bidirectional, non-solid, impedance-controlled reference plane |
| JP2001118957A (en) * | 1999-10-22 | 2001-04-27 | Nec Kyushu Ltd | Semiconductor device |
| JP2001267350A (en) * | 2000-03-21 | 2001-09-28 | Fujitsu Ltd | Semiconductor device and manufacturing method for the same |
| JP2002050877A (en) * | 2000-08-01 | 2002-02-15 | Kyocera Corp | Multilayer wiring board |
-
2001
- 2001-10-18 JP JP2001320169A patent/JP4000815B2/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0897557A (en) * | 1994-07-28 | 1996-04-12 | Fujitsu Ltd | Multilayered thin film wiring board |
| JP2000507427A (en) * | 1996-03-25 | 2000-06-13 | サムシュング・エレクトロニクス・カンパニー・リミテッド | Bidirectional, non-solid, impedance-controlled reference plane |
| JPH09289214A (en) * | 1996-04-24 | 1997-11-04 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacturing method thereof |
| JPH11177247A (en) * | 1997-12-15 | 1999-07-02 | Ngk Spark Plug Co Ltd | Wiring board |
| JP2001118957A (en) * | 1999-10-22 | 2001-04-27 | Nec Kyushu Ltd | Semiconductor device |
| JP2001267350A (en) * | 2000-03-21 | 2001-09-28 | Fujitsu Ltd | Semiconductor device and manufacturing method for the same |
| JP2002050877A (en) * | 2000-08-01 | 2002-02-15 | Kyocera Corp | Multilayer wiring board |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008218494A (en) * | 2007-02-28 | 2008-09-18 | Casio Comput Co Ltd | Semiconductor device and its manufacturing method |
| JP4506767B2 (en) * | 2007-02-28 | 2010-07-21 | カシオ計算機株式会社 | Manufacturing method of semiconductor device |
| JP2010093307A (en) * | 2010-01-29 | 2010-04-22 | Casio Computer Co Ltd | Semiconductor device |
| JP2011249862A (en) * | 2010-05-21 | 2011-12-08 | Nec Tokin Corp | Noise suppression transmission channel and sheet-like structure used for it |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4000815B2 (en) | 2007-10-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100533517B1 (en) | Semiconductor device | |
| US7545036B2 (en) | Semiconductor device that suppresses variations in high frequency characteristics of circuit elements | |
| US9076789B2 (en) | Semiconductor device having a high frequency external connection electrode positioned within a via hole | |
| TW475196B (en) | Apparatus and method for an integrated circuit having high Q reactive components | |
| US7230326B2 (en) | Semiconductor device and wire bonding chip size package therefor | |
| JP2004079579A (en) | Semiconductor device | |
| JP2001217355A (en) | Semiconductor device | |
| TW200522288A (en) | High-frequency device | |
| KR940012587A (en) | Semiconductor integrated circuit device | |
| WO2010050091A1 (en) | Semiconductor device | |
| KR20010079632A (en) | Method for implementing resistance, capacitance and/or inductance in an integrated circuit | |
| JP3443408B2 (en) | Wiring board and semiconductor device using the same | |
| JP3579000B2 (en) | Semiconductor device | |
| TWI235416B (en) | High frequency signal transmission structure | |
| JP6019367B2 (en) | Semiconductor device | |
| JP4000815B2 (en) | Semiconductor device | |
| JP2006049557A (en) | Semiconductor device | |
| TWI675387B (en) | Film capacitor structure and semiconductor device having the same | |
| JP2010093076A (en) | Semiconductor package and semiconductor device | |
| JP2004014645A (en) | Semiconductor device | |
| JP2007081267A (en) | Semiconductor device and manufacturing method therefor | |
| JP4089402B2 (en) | Semiconductor device | |
| JP2882396B2 (en) | Semiconductor device | |
| JP2004241696A (en) | Semiconductor device, its manufacturing method, circuit board, and electronic equipment | |
| JP4547655B2 (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20041005 |
|
| RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20050701 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060531 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060606 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060731 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20070724 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20070806 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100824 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100824 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110824 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110824 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120824 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130824 Year of fee payment: 6 |
|
| LAPS | Cancellation because of no payment of annual fees |