JP2003115047A - Device for generating and displaying highly accurate image - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently present highly accurate images by dispersing the image generating load of individual PCs in a highly accurate image generating/ displaying device obtained by combining two or more inexpensive PCs and display devices of low resolution in a computer graphics application field. SOLUTION: A PC connected to a display device out of PCs constituting an image generating PC cluster 100 is provided with a buffer synchronizing substrate 10B and a PC not connected to the display device is provided with a slave synchronizing substrate 10S. Thus a highly accurate image is generated and displayed by dispersing the load of generated images by using a digital image link 120.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-definition image generation / display apparatus in which the load related to image generation is distributed to a plurality of computers in the field of computer graphics in which images are generated by a computer.

[0002]

2. Description of the Related Art With the remarkable improvement in performance and cost reduction of personal computers, industrial application of PC clusters having a computing performance comparable to that of supercomputers has begun. For high-definition image generation and display devices, it is unavoidable to use a dedicated graphic workstation or large projector due to the demand for image generation capability and high definition, and it is possible to flexibly handle images with excellent image generation capability and high-definition large screens. A high-definition image generation / display device using a PC cluster has also been attempted as a generation / display device.

An example of a conventional high-definition image generation / display apparatus using a PC cluster will be described below with reference to the drawings.

FIG. 8 shows an example of the structure of a high-definition image generating and displaying apparatus using a PC cluster. High-definition display device 1
Reference numeral 11 is composed of a plurality of display areas 112. The display area 112 is an image of 4 columns × 2 stages projected from the rear surface of the high-definition display device 111 by the projector 110 having XGA (1024 × 768 pixels) resolution, and a plurality of display areas are combined and integrated into 4096 × 1536 pixels. It is presented to the subject 113 as a high-definition image.

The projector 110 is an individual PC (Personal Comp) of the PC cluster 100 for image generation.
computer cluster 100 for image generation
Each individual PC generates an image by the communication means such as a LAN and the control means that cooperates as a PC cluster to display the image on the high-definition display device 111. Further, the image generation PC cluster 100 is connected to the external PC clusters 101, 102, etc. by LAN / WAN / Internet, etc., and cooperates while sharing the calculation required for image generation.

In this configuration, the high-definition image presented to the subject 113 is the individual PC in the image generation PC cluster 110.
Because the maximum delay time of the image generation capability due to, the drawing delay for each display area gives the subject 113 a feeling of discomfort or discomfort, various drawing delays are reduced in order to reduce the drawing delay in each display area. Proposals have been made, and one example is Ascala at Princeton University in the United States.
ble Display Wall (http: // w
ww. cs. Princeton. edu / omini
CG (ComputerG) generated in media /)
The complexity of the image is calculated in advance by the Sort First method, and the image that should be originally generated by the PC connected to the projector 110 of each XGA resolution is divided into tiles in the virtual storage area, and another PC cluster is created. There has been proposed a method of preventing the deterioration of the image generation capability of a high-definition image by dividing and drawing with and transmitting by a high-speed LAN.

However, in a high-definition image obtained by this method, optimal load distribution of image generation cannot be expected unless the complexity of the entire drawing object to be drawn is known in advance, so that a complicated three-dimensional image with depth is obtained. In the case of a stereo image or the like, when the subject 113 suddenly moves the viewpoint, in order to generate and display a real-time image, the three-dimensional positional relationship of the drawing object is changed in accordance with the change in the viewpoint direction in the drawing area of the viewpoint movement destination. Since the complexity associated with the drawing of the drawing object is determined again from the calculation result and the optimization of the load distribution frequently occurs in other PC clusters, the result is that the subject cannot be presented in real time. is there.

[0008]

In view of the above problems, the present invention provides an efficient image by providing the image generating PC cluster 100 with means for synchronizing the presented image and the drawn image and buffering the drawn image. An object of the present invention is to provide a high-definition image generating / displaying device capable of generating.

[0009]

In order to achieve the above object, the present invention provides means for efficiently adjusting and buffering the timing between images presented to a subject and images drawn by individual PCs, and a LAN. There is a means for transmitting a drawing image between individual PCs without using a communication means such as the above, and a means for transmitting information for efficiently sharing and complementing the drawing area to be in charge between the individual PCs. The image synchronizing board and its control means provide an efficient image generating PC cluster.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below.
A description will be given with reference to the drawings.

In FIG. 10, a high-definition display device 111 is composed of image regions 112 individually projected by a plurality of projectors 110, and a subject 114 is a viewpoint detecting position sensor 113 and a liquid crystal shutter 115 for observing a three-dimensional stereo image. Thus, the right eye image and the left eye image are alternately observed as shown in FIG. The projector 110 is a CG
Any device that can display an image may be used and the same effect can be obtained even if the device is replaced with a display device such as a CRT or a liquid crystal display.

The liquid crystal shutter 115 includes a display system master vertical sync signal 50, a display system master horizontal sync signal 51, a liquid crystal shutter right eye image sync signal 52, and a liquid crystal shutter left eye image shown in FIG. 5 by a liquid crystal shutter sync signal generator 116. The synchronizing signal 53 is generated and sent to the buffer synchronizing board 10B which outputs the image to the display device of each drawing area by the display device image synchronizing circuit 16 shown in FIG.
As shown in FIG. 5, the right-eye image and the left-eye image of the liquid crystal shutter are alternately switched for each vertical synchronization signal 50, and the parallax image is synchronously displayed by the image generation / display device to be presented to the subject as a three-dimensional stereo image. 20 to 30 seconds per second as a continuous three-dimensional stereo image that the subject does not feel uncomfortable.
A parallax image generation capability of the screen is required.

The subject 113 has a viewpoint position detecting device 114.
The pixel position information in the image display system to which the subject is attached is connected to the display system control master PC 35, and the display system control master PC subjects the individual PCs constituting the screen generation PC cluster 100 to the subject. The gaze pixel position information is transmitted by communication means such as LAN in the cluster.

Each PC sequentially generates a CG image of its area according to the subject's gaze pixel position information, but the image synchronization signal generated by the graphic board incorporated in each PC is as shown in FIG. Master sync signal 50/51
Since there is no synchronization relationship with, and the time required for image generation differs depending on the image to be generated, in order to perform smooth image display that does not give the subject a feeling of discomfort, a delay due to the image generation time difference between individual PCs is required. It is desirable to present the image of the entire high-definition display device 111 while keeping it to the minimum and maintaining the synchronization with the master image synchronization signal.

In the present invention, a means is provided for absorbing the difference in the image generation time and the difference in the image synchronizing signals by the individual PCs by the buffer synchronizing board shown in FIG.
In order to provide a high-definition image generating and displaying apparatus more efficient than the prior art by providing an image data linking means by a digital image interface and means for transmitting image data control information between the substrates even in spite of a sudden change in the image generating load due to Is.

The buffer synchronization board 10B has a plurality of digital image linking means 17R and 17T, 17R being a receiver and 17T being a transceiver.
By configuring the R.17T as a pair, the digital image can be distributed to a plurality of devices. See the Digital Display Work for this digital image link.
ing Group (http: //www.ddw
g. Digital V proposed by org)
Although the explanation will be made by using the interface standard as one embodiment, the same effect can be obtained by using other digital image linking means.

In this digital image linking means, a vertical synchronizing signal 60, a horizontal synchronizing signal 61, and a data valid section signal 62.
2 have a phase synchronization relationship as shown in FIG. 2, and the digital image data is 8-bit RGB serial data due to the phase synchronization relationship between the data carrier clock 63, the data valid section signal 62 and the horizontal synchronization signal 61 shown in FIG. Have been transferred as. The digital image linking means 17R
A counter for a horizontal synchronizing signal 61 which is reset by the vertical synchronizing signal 60 and a counter for a data carrier clock 63 for the digital image link, which is reset at each rising edge of the horizontal synchronizing signal, are attached to the counter and are transmitted by the digital image link. It has means for specifying the pixel position of the incoming image data.

Here, the inter-substrate synchronization control means in the present invention uses a predetermined bit data string synchronized with the inter-substrate synchronization reference clock 70 within the horizontal pixel effective section of the display device reference horizontal synchronization signal 51 shown in FIG. Table 1 and Table 2 show bit data string configurations as one embodiment.

[Table 1]

In the embodiment shown in Table 1, during drawing, L / R designation,
+ N screen designation The status code is designated by 2 bits in total, 4 bits in total, and the left eye in the case where the digital image data transmitted from the PC of the corresponding ID number is in the drawing status and is operating as a three-dimensional stereo image. The image / right-eye image selection information and the identification information as to whether or not the image currently displayed is the n-th image to be displayed are included.

[0020]

[Table 2]

Further, as shown in Table 2, the drawing area information indicates the pixel position information of the rectangular area, and the conversion of the real pixel position conversion table in the X direction and the real pixel position conversion table in the Y direction is performed by 4-bit data. Indicates the address. The values of the actual pixel position conversion table in the X direction and the Y direction can be freely rewritten through a communication means such as LAN in the image generating PC cluster, but as one embodiment, the drawing area is equally divided in the XGA display. Example of conversion table in case of doing
・ Table 4 shows.

[Table 3]

[0022]

[Table 4]

Here, in the inter-board synchronization control circuit 18 of FIG. 1, an ID number of another PC previously connected to the buffer synchronization board 10B by digital image linking means and an ID number unique to the buffer synchronization board 10B are generated. 1 is extracted by extracting a status code and drawing area information from a PC which substitutes for drawing, which will be described later, from the inter-board synchronization control signal sequence shown in FIG. By setting it in the input image selection circuit, it is possible to store the alternative drawn image data in a predetermined input image buffer.

Further, since the drawing area information includes the pixel position information of the rectangular area in which the alternative drawing is performed, it is first determined by the Top-Y coordinate of the alternative drawing area after the drawing start status becomes valid. The image data storage starts when the horizontal sync signal count value becomes equal to or more than the equal value, and the image data starts when the horizontal sync signal count value becomes the Bottom-Y coordinate or more after the drawing start status becomes invalid. The storage is completed and the image data storage completion flag is held in the transfer image selection circuit 13 of FIG.

When the information of the inter-board sync control signal changes, the PC interface 19 of the buffer sync board 10B generates an interrupt to transmit the information to the PC main body, and the PC cluster in the image generation PC cluster It is transmitted to the display system control master PC 35 via a communication means such as a LAN.

Here, as shown in FIG. 9, the digital image output of the graphic board or the circuit 31 of the PC 33 itself equipped with the buffer synchronizing board connected to the projector 110 is also supplied to the digital image linking means of the buffer synchronizing board 10B. Since the display system control master PC 35 is connected, the drawing state information of the image to be drawn in each display area 112 of the high-definition display device is collected.
P with a slave synchronization board mounted as shown in FIGS.
By connecting the digital image link from C34 to an area that is physically distant from the display area in which the subject 113 is gazing with respect to each display area 112 in the high-definition display device, the load related to image generation can be distributed. .

FIG. 14 shows image data of 5,120 × 4,096 pixels used for verifying the effect of load distribution.
This image is divided into 4 parts vertically and horizontally and divided into 16 parts 1, 28
Table 5 shows the time of individual rendering for 0 × 1,024 pixels. Depending on the complexity of the image of each divided region, the rendering time is 5.528 ms to 95.ms.
Since it is distributed up to 570 milliseconds, the maximum delay time in each area becomes the image update rate of the entire display device in the conventional method.

[0028]

[Table 5]

[0029]

[Table 6]

Table 7 shows the results of load distribution by the image buffer synchronizing means according to the present invention regarding the load distribution among the units for generating the image of each area. The rendering time is 43.637-. It is 75.397 milliseconds, and a remarkable improvement effect is recognized also in the maximum delay time that determines the image update rate of the entire display device. further,
As for the left and right image generation as a three-dimensional stereo image, as shown in FIG. 15, in the conventional method, the left and right images of the specific region are generated by one PC, but the region with the largest image generation load is generated. For the left and right images that the unit B substitutes for the left image of the unit A in charge of, and the unit B originally generates the images, the unit C and the unit D with a small layer generation load can generate a substitute image. Therefore, as shown in Table 7, a remarkable improvement in the capability of the image generating and displaying apparatus is recognized as compared with the conventional method.

[0031]

[Table 7]

Further, it is said that the image update rate as a three-dimensional stereo image which does not give the subject a feeling of strangeness is 20 frames per second or more. On the other hand, the image transmission frame rate of the graphic board or the graphic circuit used in the PC is 80 to 120 frames per second at a resolution of XGA (1,024 × 768 pixels) or less, and the image data transmission capability is high. In the present invention, the high-speed image data transmission capability on the PC side is also taken into consideration, and the interrupt generation cycle by the inter-board synchronization control means is equipped with a buffer synchronization board.
By making it possible to control the horizontal sync signal generated by the PC at any number of times, it is possible to generate information in the image generation cluster that determines changes in the image generation load multiple times within the frame generation period of the display device. It is possible to quickly disperse the image generation load even with a sudden change in the image generation load due to movement of the viewpoint.

Further, as shown in FIG. 16, the projector 1
It is also possible to connect a PC 33 having a plurality of buffer synchronization boards to a PC 33 having a buffer synchronization board connected to 10 to provide a tree-shaped cluster configuration and further improve the image generation capability.

[0034]

By using the image buffer synchronizing means according to the present invention and the inter-PC unit synchronizing control means, 3
A CG image typified by a three-dimensional stereo image or the like can be efficiently generated while distributing the image generation load, and a high-definition display device can be configured by combining image display devices with low resolution.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a buffer synchronization board according to a first embodiment of the present invention.

FIG. 2 An example of basic timing of digital image transmission

FIG. 3 shows an example of the detailed timing of FIG.

FIG. 4 is a drawing timing relationship diagram of a display device and individual PCs according to the present invention.

FIG. 5 is a timing chart of stereo image display by a liquid crystal shutter.

FIG. 6 is a control signal diagram of inter-substrate synchronization control in the present invention.

FIG. 7 is a positional relationship diagram of a rectangular drawing area according to the present invention.

FIG. 8 is an example of a conventional high-definition image generation / display device using a PC cluster.

FIG. 9 is a wiring system 1 for a buffer synchronous board according to the present invention.
Example

FIG. 10 is a block diagram of a high-definition image generating and displaying apparatus according to the first embodiment of the present invention.

FIG. 11 is an image data link wiring diagram between the drawing PCs in FIG.

FIG. 12 is a relational diagram of image data secondary links between drawing PCs in FIG.

FIG. 13 is a relational diagram of the image data tertiary link between the drawing PCs in FIG.

[Fig. 14] Image of load balancing study by area division

FIG. 15: Load distribution in 3D stereo image

FIG. 16: Cluster configuration with enhanced load balancing

[Explanation of symbols]

10B Buffer synchronization board 10S in the first embodiment Slave synchronization board 11 in the first embodiment Input image selection circuit 12 Input image buffer 13 Transfer image selection circuit 14L Drawing image buffer L 14R Drawing image buffer R 15 Image output circuit 16 Display device Image synchronization circuit 17T Digital image link transceiver 17R Digital image link receiver 18 Inter-board synchronization control circuit 19 PC interface 30 PC 31 PC graphic board or circuit 32 Digital image output from PC graphic board or circuit 33 Buffer sync board PC with mounted slave 35 PC with mounted slave sync board Display system control master PC 50 Display system master vertical sync signal 51 Display system master horizontal sync signal 52 Liquid crystal shutter right eye image sync signal 53 Liquid crystal shutter Left eye image sync signal 55 Vertical sync signal from PC-n 56 Horizontal sync signal from PC-n 60 Digital image interface Vertical sync signal 61 Digital image interface Horizontal sync signal 62 Digital image interface Data section sync signal 63 Digital image Interface data carrier clock 64 Digital image interface Pixel data 70 Inter-substrate sync signal data carrier clock 71 Inter-substrate sync signal data 100 PC cluster for image generation 101 Large-scale PC cluster 102 Three-dimensional rendering PC cluster 103 External communication network such as LAN and WAN 104 auxiliary drawing PC cluster 110 projector 111 high-definition display device 112 individual display areas of high-definition display device 113 subject 114 subject's viewpoint position detection device 115 Crystal shutter 116 crystal shutter synchronization signal generator 120 present between the buffer synchronization substrate-slave synchronization substrate according to the invention the synchronization signal 121 primary connection digital video signal 122 secondary connecting digital video signal 123 cubic connected digital video signal

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Naoki Hashimoto             Tokyo Engineering, 2-12-1, Ookayama, Meguro-ku, Tokyo             Inside college (72) Inventor Ichiro Kawakami             2-12 Chigasaki Minami, Tsuzuki-ku, Yokohama-shi, Kanagawa             No.2 Measurement Technology Research Institute F term (reference) 5B057 AA20 CC03 CE08 CH02 CH04                       CH14 CH18                 5B069 AA01 BA03 BB11 DD15 KA02                       LA12                 5C082 AA34 BA12 BC03 BD07 MM07                       MM10

Claims (3)

[Claims] 1. Digital image data linking means from a plurality of PCs, and ID numbers, image generation information, image area information, and scene numbers to be replaced of other PCs connected by the data linking means. High-definition display device composed of a plurality of image display devices, means for generating and communicating inter-board synchronization control information, means for accumulating image data from the data link means in an image buffer designated by a scene number to be substituted P for image generation equipped with image buffer synchronization means having means for selectively transferring the image buffer for which the input of the alternative image area from the image data link is completed to the image buffer for drawing based on the reference image synchronization signal
A high-definition image generation and display device including a C cluster and a plurality of image display devices. 2. The high-definition image generation display device according to claim 1, wherein the PC not directly connected to each display device has only the inter-substrate synchronization control signal generation means and the image transfer means. High-definition image display device. 3. The high-definition image generation display device according to claim 1, wherein the image signal of the PC not directly connected to the display device is connected to a plurality of other display devices whose display areas are not close to each other. A high-definition image generating and displaying apparatus having means for secondary connection.