JP2003099386A - Common bus system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a common bus system, capable of recognizing the physical location and identifying information for each device in a circuit, the location and information having relation to each other. SOLUTION: A plurality of devices (card 1 and 2) are connected with a common bus (signal line) in the common bus system 100. When a host computer 30 recognizes (initializing) cards inserted into respective card slots 10 and 20, it outputs to a switching circuit 40 a switching signal, that switches a clock signal output to a terminal A connected to the card slot 10. A card 1 responds only to a request from the host 30 for obtaining ID. The host 30, obtaining the ID, allots a relative address to the card 1, and stores relative address information of the card 1 and switching information for the terminal A (location information of the card slot 10 in the circuit), both information being related to each other. For the card 2, the host 30 executes similar initialization process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared bus system in which a plurality of devices are connected by a shared bus.

[0002]

2. Description of the Related Art Conventionally, as a system in which a plurality of devices are connected by a shared bus, there is a system in which a device is selected by an ID unique to each device. In such a system, as shown in FIG. 3A, a host controlling each device sends a signal to a specific device (for example, device 2) through a shared signal line (bus). By transmitting a signal for selecting this device based on the unique ID (for example, ID2), only this device can be accessed.

As an example of a system in which a plurality of devices are connected by a shared bus, two memory cards (for example, MMC (Multi Media Card)) as shown in FIG. 3B are used.
A card initialization process for the host 30 to access each of the memory cards 1 and 2 in a system having a (registered trademark) slot will be described with reference to the flowchart of FIG. In the example shown in FIG. 4, the ID of the memory card 2
It is assumed that the number is larger than the ID number of the memory card 1.

First, the host 30 uses the card slot 1
The memory cards 1 and 2 inserted in 0 and 20 are set in the idling state (step P1). Then host 30
Transmits an ID acquisition request signal simultaneously to the cards 1 and 2 through the shared signal line (step P
2).

As a response to the ID acquisition request from the host 30, the cards 1 and 2 transmit the respective ID data to the host 30. At this time, the card 1 having the smaller ID number acquires the bus right, transmits the ID data to the end, and enters the identification state. on the other hand,
The ID data transmission of the card 2 having a large ID number is interrupted and enters a standby state (step P3).

The host 30 acquires the ID of the card 1 (step P4) and sets a relative address for the card 1 (step P5). The card 1 to which the relative address is assigned becomes the standby state, and thereafter, the host 3
It does not respond to the ID acquisition request signal from 0.

Next, the host 30 transmits the ID acquisition request signal again to the cards 1 and 2 through the shared signal line (step P6). The card 1 in the standby state does not respond to the ID acquisition request, and this time, the card 2 acquires the bus right and transmits the ID data to the host 30.

The host 30 acquires the ID of the card 2 (step P7) and sets the relative address for the card 2 (step P8). After that, the host 30 selects the card to be accessed by the relative addresses set in the cards 1 and 2 in steps P5 and P8.

As described above, the host 30 identifies each card by the relative address set by the ID acquired from each card.

[0010]

However, when the ID of each device is not known in advance, as in the system for selecting a device by the ID as shown in FIG. 3,
Although the host reads the ID from each device and selects a specific device, there is a problem that it cannot determine which device on the circuit is the selected device.

In a system having a plurality of memory card slots as shown in FIG. 3B, the ID of the memory card inserted in each slot is recognized only after the card is inserted. In this case, the host 30 uses the I
Since each memory card is identified only by the relative address set by D, it cannot be identified in which slot the memory card inserted is being accessed. Therefore, it is impossible to perform an operation such as copying the recorded contents of the card 1 inserted in the card slot 10 to the card 2 inserted in the card slot 20.

An object of the present invention is to provide a shared bus system capable of recognizing the physical position of each device on a circuit and the identification information in association with each other.

[0013]

The invention according to claim 1 is
A shared bus system in which a plurality of devices are connected by a shared bus and a transmission line of a clock signal for operating each of the devices, the device being arranged on its own system circuit when identifying each of the devices. Designating means for designating a device for obtaining identification information from each device, switching means for switching a transmission path of a clock signal on the transmission line to the device side designated by the designating means, and the designated device. From, identification information acquisition means for acquiring the identification information of the device transmitted in synchronization with the clock signal, and the arrangement information of the device on its own system circuit based on the designation by the designating means,
It is characterized by comprising: storage means for storing the identification information of the device acquired by the identification information acquisition means in association with each other.

According to a second aspect of the present invention, in the first aspect of the invention, the target device is accessed through the shared bus based on the identification information and the arrangement information for each device stored in the storage means. It is characterized in that it further comprises access means for performing.

According to a third aspect of the present invention, in the first aspect of the present invention, the switching means further switches the power supply to each device to the device side designated by the designating means to obtain the identification information. The shared bus system according to claim 1, wherein the means acquires the identification information of the device from the device whose power supply is switched by the switching means.

According to the first, second and third aspects of the present invention, the arrangement information of each device on the shared bus system circuit and the identification information can be recognized in association with each other.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. First, the configuration will be described.

FIG. 1 is a block diagram showing an internal configuration of a shared bus system 100 to which the present invention is applied. As shown in FIG. 1, the shared bus system 100 includes card slots 10 and 20 as devices, a host 30, and a switching circuit 40. The card slot 10, the card slot 20, and the host 30 share a shared signal line. Connected by (solid line).

The card slots 10 and 20 are respectively
This is a slot for inserting the memory cards 1 and 2.
Each of the memory cards 1 and 2 inserted in the card slots 10 and 20 has a unique ID.

The host 30 is a CPU (Ce
ntral Processing Unit), a card controller, etc., and a switching signal (two-dot chain line) for generating a clock signal (dotted line) and switching output to the card slots 10 and 20, and a shared signal line (solid line). The signals that can be used to access the cards 1 and 2 are generated.

Further, the host 30 sets the relative address for each card in accordance with the ID obtained from each card in the initialization process of the card inserted in each card slot (see FIG. 2), and The arrangement information on the circuit of each card slot based on the switching signal and the relative address assigned to each card are stored in association with each other. The host 30 has a function as a designating unit, an identification information acquiring unit, a storing unit, and an accessing unit in the claims.

The switching circuit 40 is a switch for switching the output of the signal input from the host 30 to either the A terminal or the B terminal or both terminals according to the switching signal input from the host 30. The switching circuit 40 has a function as a switching unit in the claims.

Next, the operation of this embodiment will be described. The card initialization process executed in the bus sharing system 100 will be described with reference to the flowchart of FIG.

First, the host 30 outputs a switching signal for switching the output of the clock signal to the A terminal only to the switching circuit 40 (step S1), and switching information to the A terminal (on the circuit of the card slot 10). (Arrangement information) is stored. The switching circuit 40 switches the output to the A terminal according to the switching signal input from the host 30. This allows
The clock signal is supplied to the card 1 inserted in the card slot 10 connected to the output A terminal, and the host 3
From 0, only the card 1 becomes ready to respond to the signal supplied to each card through the shared signal line.

Next, the host 30 simultaneously sends an ID to the card 1 and the card 2 via the shared signal line.
An acquisition request signal is transmitted (step S2). Only the card 1 responds to this ID acquisition request signal, and the host 3
0 acquires the ID of the card 1 (step S3). When the ID of the card 1 is acquired, the host 30 assigns a relative address to the card 1 (step S4), stores the relative address information of the card 1 in association with the switching information to the A terminal, and stores the card. The initialization for 1 is completed.

Next, the host 30 outputs a switching signal for switching the output only to the B terminal to the switching circuit 40 for initialization of the card 2 (step S5).
The switching information to the B terminal (arrangement information on the circuit of the card slot 20) is stored. The switching circuit 40 switches the output to the B terminal according to the switching signal input from the host 30. As a result, the clock signal output from the host 30 is supplied to the card 2 inserted in the card slot 20 connected to the output B terminal, and the signal supplied from the host 30 to each card through the shared signal line. Then, only the card 2 can respond.

Next, the host 30 simultaneously sends an ID to the cards 1 and 2 through the shared signal line.
An acquisition request signal is transmitted (step S6). Only the card 2 responds to this ID acquisition request signal, and the host 3
0 acquires the ID of the card 2 (step S7).

When the ID of the card 2 is acquired, the host 30
Assigns a relative address to the card 2 (step S8), and the relative address information of the card 2 is set to the above B.
It is stored in association with the switching information to the terminal, and the initialization for the card 2 is completed.

When the initialization of the card 1 and the card 2 is completed, the switching circuit 40 enables both the output A terminal and the output B terminal (step S9), and this card initialization processing is completed. After that, the host 30 selects the card to be accessed by the relative address set above through the shared signal line, and outputs various command signals.

As described above, according to the shared bus system 100 of the present embodiment, the switching circuit for switching the output of the clock signal from the host 30 to either the card 1 or the card 2 or both the cards. 40, the switching circuit 40 supplies the clock signal only to a target card at the time of card initialization, acquires the ID of the card, and allocates a relative address to the host 30.
Can associate the physical position of each card slot on the circuit with the relative address (ID) of the card inserted in each card slot, and which card slot is inserted into which card. Can be recognized.

The description contents in this embodiment are as follows.
Modifications can be made as appropriate without departing from the spirit of the present invention.
For example, in the present embodiment, in the card initialization, the transmission path of the clock signal is switched to the specified device (card slot) side and the ID (card ID) of the device is acquired. In addition, the transmission path of the command signal to each device may be switched to the designated device side. In addition to switching the transmission paths of clock signals and command signals, power supply to each device may be switched to the designated device side.

[0032]

According to the first, second and third aspects of the present invention, the arrangement information of each device on the shared bus system circuit and the identification information can be recognized in association with each other.

[Brief description of drawings]

FIG. 1 is a block diagram showing an internal configuration of a bus sharing system 100 to which the present invention is applied.

FIG. 2 is a flowchart showing a card initialization process executed in the bus sharing system 100 to which the present invention is applied.

3 is an internal block diagram of a conventional bus sharing system (FIG. 3A) and an internal block diagram of a conventional bus sharing system having a plurality of memory cards (FIG. 3B).

FIG. 4 is a flowchart showing a card initialization process executed in a conventional shared bus system having two memory card slots.

[Explanation of symbols]

1, 2 memory card 10, 20 card slots 30 hosts 40 switching circuit 100 bus sharing system

Claims (3)

[Claims] 1. A shared bus system in which a plurality of devices are connected by a shared bus and transmission lines of various signals for operating each of the devices, and a device on a system circuit for identifying each of the devices. Switching means for switching the device for specifying the device for which the identification information is to be acquired from among the respective devices arranged on the transmission line and the transmission path for one or more signals on the transmission line to the device specified by the specifying device. Means, an identification information acquisition means for acquiring identification information of the device from the device whose signal transmission path is switched by the switching means, and on the own system circuit of the device based on the designation by the designation means. Storage means for storing the arrangement information and the identification information of the device acquired by the identification information acquisition means in association with each other. Shared bus system, characterized. 2. An access unit for accessing a target device through the shared bus based on identification information and arrangement information for each device stored in the storage unit. Shared bus system as described. 3. The switching means further switches the power supply to each device to the device side designated by the designating means, and the identification information obtaining means the device whose power supply is switched by the switching means. The shared bus system according to claim 1, wherein the identification information of the device is acquired from the.