JP2003091328A - Computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use clock signal containing very little unnecessary signal of higher harmonics or the like, and to simply lower the frequency of the clock signal during the operation in a power saving mode. SOLUTION: This computer includes a CPU 1, a plurality of peripheral devices 2, 3, 4 controlled by the CPU 1, a bus 5 for transmitting data between the CPU 1 and the peripheral devices 2, 3, 4 and between the peripheral devices, and a clock signal source 6 for supplying a clock signal to the CPU 1 and the bus 5. The clock signal source 6 is formed by a PLL synthesizer, and during the operation in the power saving mode, the output frequency of the PLL synthesizer is lowered.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer, and more particularly to a computer having a power saving function.

[0002]

2. Description of the Related Art In a battery-powered portable computer such as a notebook type personal computer or the like, in order to prevent the consumption of the battery if the portable computer is not operated for a certain period of time even when the power is on. Some are designed so that the frequency of the clock signal can be lowered to switch to the power save mode. FIG. 5 shows a configuration of a main part of such a computer, and a clock signal source is configured by a combination of a reference oscillator and a multiplier provided in the computer. The reference oscillator 51 oscillates at several MHz,
The oscillation signal is multiplied by the first multiplier 52 to an appropriate frequency. The multiplication ratio of the first multiplier 52 is fixed, and the multiplied signal is used as a clock signal for the bus 53.

The signal multiplied by the first multiplier 52 is further multiplied by the second multiplier 54 to a higher frequency. The second multiplier 54 is provided in the CPU 55, and the multiplied signal is used as the clock signal for the CPU 55 by the core 55a. Then, in the power save mode, switching is performed so that the multiplication ratio of the second multiplier 54 becomes smaller.

[0004]

SUMMARY OF THE INVENTION In the above conventional configuration,
Since the signal multiplied by the multiplier is used as the clock signal, many unnecessary signals are generated over a wide frequency range in addition to the desired frequency signal. These include unnecessary spurious output from the first multiplier and unnecessary spurious output from the second multiplier.
Such unnecessary signals enter various circuits via a bus or the like in a device such as a personal computer and cause the circuits to malfunction. In addition, it was radiated to the outside of the personal computer, causing interference with other electronic devices.

Further, since the multiplier uses the non-linear characteristic of the amplifier to generate harmonics and takes out a harmonic of a required frequency from the harmonics, the structure for switching the frequency is complicated.

Therefore, it is an object of the present invention to be able to use a clock signal in which unnecessary signals such as harmonics are extremely small and to easily lower the frequency of the clock signal in the power save mode.

[0007]

[Means for Solving the Problems] In order to solve the above problems,
In the present invention, a CPU, a plurality of peripheral devices controlled by the CPU, a bus for data transmission between the CPU and the peripheral device and between the peripheral devices, and the C
A clock signal source for supplying a clock signal to the PU and the bus, the clock signal source being constituted by a PLL synthesizer, and the PL in the power save mode.
The output frequency of the L synthesizer was lowered.

The PLL synthesizer outputs two signals having different frequencies, one of which is the CP signal.
The clock signal for U and the other clock signal for the bus.

The PLL synthesizer has a PLL circuit having at least a voltage controlled oscillator, a reference oscillator for supplying a reference signal to the PLL circuit, and a first frequency divider for dividing an oscillation signal output from the voltage controlled oscillator. A frequency divider and a second frequency divider that divides the frequency-divided signal by the first frequency divider, and supplies the frequency-divided signal output from the first frequency divider to the CPU. At the same time, the frequency division signal output from the second frequency divider is supplied to the bus to increase the frequency division ratio of the first frequency divider in the power save mode.

Further, the PLL synthesizer has a PLL circuit having at least a voltage controlled oscillation means and a first frequency divider for dividing an oscillation signal of the voltage controlled oscillation means, and a reference for supplying a reference signal to the PLL circuit. An oscillator and a second frequency divider that divides the oscillation signal, and supplies the oscillation signal to the CPU and the frequency division signal output from the second frequency divider to the bus. However, the frequency division ratio of the first frequency divider is reduced in the power save mode.

Further, the voltage controlled oscillator is composed of two voltage controlled oscillators which are selectively selected and one of which constitutes the PLL circuit. In the power save mode, one of the voltage controlled oscillators is selected. In the normal mode other than the power save mode, the other voltage controlled oscillator is switched to be selected.

Further, the frequency division ratio of the second frequency divider can be changed.

The PLL synthesizer has a first P having at least a voltage controlled oscillator and a first frequency divider.
LL circuit, a second PLL circuit having at least a voltage controlled oscillator, the first PLL circuit and the second PL circuit
L circuit and a reference oscillator that supplies a reference signal to the L circuit,
The oscillation signal output from the voltage controlled oscillator is
The oscillation signal output from the voltage controlled oscillator is supplied to the PU, and the oscillation signal output from the voltage controlled oscillator is supplied to the bus to reduce the division ratio of the first frequency divider in the power save mode.

Further, the voltage controlled oscillator is composed of two voltage controlled oscillators which are alternatively selected and one of which constitutes the first PLL circuit. In the power save mode, one of the voltage controlled oscillators is used. In the normal mode other than the power save mode, the other voltage controlled oscillator is selected.

Further, the second PLL circuit is provided with a second frequency divider for setting the oscillation frequency of the voltage controlled oscillator, and the second frequency divider can be changed.

[0016]

DETAILED DESCRIPTION OF THE INVENTION A computer of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a computer of the present invention, and FIGS. 2 to 4 are circuit diagrams showing a concrete configuration of a clock signal source used in the present invention.

In FIG. 1, the computer has a CPU.
1, peripheral devices 2, 3, such as memory, input device, output device, etc.
4 are configured. Data is transmitted by the bus 5 between the CPU 1 and each of the peripheral devices 2, 3 and 4. Also, the computer uses a clock signal for operating the CPU 1 (referred to as a CPU clock signal) and a bus 5
Requires a clock signal (referred to as a bus clock signal) for transmitting data, and a clock signal source 6 for this purpose is also provided in the computer. At least two signals S1 and S2 are output from the clock signal source 6, one signal S1 is used as a CPU clock signal, and the other signal S2 is used as a bus clock signal. The CPU clock signal has a higher frequency than the bus clock signal.

With the above configuration, when the computer is normally operated, the CPU clock signal and the bus clock signal have a predetermined high frequency, but if they are not operated for a certain period of time, they are used as a power source. In order to prevent the battery from running down, the CPU 1 sends the control signal C to the signal source 6.
TRL is sent to lower the frequency of the clock signal so that the power save mode can be selected. In the present invention, the clock signal source 6 is a P
It is composed of an LL synthesizer.

A PLL synthesizer as the clock signal source 6 will be described below with reference to FIGS. 2 shows the first embodiment, FIG. 3 shows the second embodiment, and FIG. 4 shows the third embodiment.

First, in FIG. 2, the PLL circuit 10 is composed of a closed loop consisting of a phase comparator 10a, a low-pass filter 10b, a voltage controlled oscillator 10c, and a frequency divider 10d. Is supplied. Since the operation of the PLL circuit is well known, detailed description thereof will be omitted, but the oscillation frequency of the voltage controlled oscillator 10c is set by the frequency divider 10d in the PLL circuit 10. Further, the frequency divider 10d may have a fixed frequency division ratio or may be configured to be variable.

The oscillation signal output from the voltage controlled oscillator 10c is divided by the first frequency divider 12. The frequency division ratio of the first frequency divider 12 is configured to be switched between at least two large and small. Switching of the frequency division ratio is performed by a control signal CTRL from the CPU 1. The frequency division signal S1 output from the first frequency divider 12 is used as a CPU clock signal.

The frequency-divided signal output from the first frequency divider 12 is input to the second frequency divider 13. The frequency division ratio of the second frequency divider 13 may be fixed or variable. The frequency-divided signal S2 output from the second frequency divider 13 is used as a bus clock signal. If the second frequency divider 13 is a variable type whose frequency division ratio can be changed, the frequency of the bus clock signal can be changed appropriately.

In the above configuration, when the computer is operated steadily, the first frequency divider 12 operates as CP.
The frequency division ratio is set to a small value by U1, and the first frequency divider 12 outputs the frequency division signal S1 of a predetermined high frequency necessary for the CPU 1 to operate. However, when the computer operation is stopped for a certain period of time, the power save mode is set and the first frequency divider 12 is set to a large frequency division ratio by the control signal CTRL from the CPU 1. Then, the frequency of the frequency-divided signal output from the first frequency divider 12 is lowered. As a result, power consumption in the computer is reduced.

Next, the configuration of FIG. 3 will be described. PL
The L circuit 20 includes a phase comparator 20a and a low pass filter 20.
b, a voltage controlled oscillation means 20c, a switching means 20d, and a first frequency divider 20e, which is a closed loop. The phase comparator 20a is supplied with a reference signal from a reference oscillator 11.
The first frequency divider 20e is composed of a variable frequency divider whose frequency division ratio can be switched. The voltage controlled oscillator 20c is composed of two voltage controlled oscillators 20c1 and 20c2, and the output signal S1 of either of them is selected by the switching means 20d and input to the first frequency divider 20e, and at the same time, the CPU clock signal Used as.

The signal S1 selected by the switching means is input to the second frequency divider 21, and the frequency-divided signal S2 output from the second frequency divider 21 is used as a bus clock signal. The frequency division ratio of the second frequency divider 21 may be fixed or changeable.

In the above configuration, when the computer is operated steadily, the frequency division ratio of the first frequency divider 20e is set to be large by the CPU 1, so that the voltage controlled oscillation means 20c is operated by the CPU 1. It oscillates at the predetermined high frequency required to operate. In this case, the switching means 20d is controlled by the control signal CTRL from the CPU 1.
Selects the oscillation signal of one voltage controlled oscillator 20c1. However, in the power save mode, the control signal CTRL from the CPU 1 switches the first frequency divider 20e to a smaller frequency division ratio. Then, the oscillation frequency of the voltage controlled oscillator 20c is lowered. In this case, the switching means 20d selects the oscillation signal from the other voltage controlled oscillation means 20c2 according to the control signal CTRL.

In the configuration of FIG. 3, the two voltage controlled oscillators 20c1 and 20c2 can be selectively used in correspondence with two high and low oscillation frequencies, so that a stable oscillation signal can be obtained at any frequency.

Next, the configuration of FIG. 4 will be described. The first PLL circuit 30 is configured by a closed loop including a first phase comparator 30a, a first low-pass filter 30b, a voltage controlled oscillation means 30c, a switching means 30d, and a first frequency divider 30e, and has a first phase. A reference signal is supplied from the reference oscillator 11 to the comparator 30a. The first frequency divider 30e is composed of a variable frequency divider whose frequency division ratio can be switched. Further, the voltage controlled oscillator 30c includes two voltage controlled oscillators 30c1,
30c2, one of the output signals S1 is selected by the switching means 30d and input to the first frequency divider 30e, and is used as a CPU clock signal.

The second PLL circuit 40 is composed of a second phase comparator 40a, a second low-pass filter 40b, a voltage controlled oscillator 40c, and a second frequency divider 40d. A reference signal is supplied from the reference oscillator 11 to 40a. The second frequency divider 40e may be composed of a variable frequency divider whose frequency division ratio is fixed or can be switched. The oscillation signal S2 output from the voltage controlled oscillator 40c is used as the bus clock signal.

In the above configuration, when the computer is constantly operated, the frequency division ratio of the first frequency divider 30e is set to be large by the CPU 1, so that the voltage controlled oscillator 30c is operated by the CPU 1. It oscillates at the predetermined high frequency required to operate. In this case, the switching means 30d selects the oscillation signal of one of the voltage controlled oscillators 30c1 by the control signal CTRL from the CPU 1.
However, in the power save mode, the control signal CTRL from the CPU 1 switches the first frequency divider 30e to a smaller frequency division ratio. Then, the voltage controlled oscillator 3
The oscillation frequency of 0c decreases. In this case, the switching means 30
d is the other voltage-controlled oscillator 3 depending on the control signal CTRL.
The oscillation signal from 0c2 is selected.

Also in the configuration of FIG. 4, two voltage controlled oscillators 30c1 and 30c corresponding to two oscillation frequencies, high and low.
Since c2 can be selectively used, a stable oscillation signal can be obtained at any frequency.

[0032]

As described above, in the computer of the present invention, the CPU, the plurality of peripheral devices controlled by the CPU, and the bus for data transmission between the CPU and the peripheral devices and between the peripheral devices are provided. , A clock signal source for supplying a clock signal to the CPU and the bus, the clock signal source is configured by a PLL synthesizer, and the output frequency of the PLL synthesizer is lowered in the power save mode, so that the frequency switching of the clock signal is digital. Easy to do. Also, since the PLL synthesizer is used,
The generation of unwanted signals that may cause interference is reduced, the risk of malfunctioning of the computer is eliminated, and the unwanted signals that are radiated to the outside are reduced, so that interference with other electronic devices can be provided.

Further, the PLL synthesizer outputs two signals having different frequencies, one of which is used as a clock signal for the CPU and the other of which is used as a clock signal for the bus. Therefore, in the power save mode, the two clocks are used. The frequency of the signal or either clock signal can be changed.

The PLL synthesizer includes a PLL circuit having at least a voltage controlled oscillator, a reference oscillator for supplying a reference signal to the PLL circuit, and a first frequency divider for dividing an oscillation signal output from the voltage controlled oscillator. , A second frequency divider that divides the frequency-divided signal by the first frequency divider, and the CPU divides the frequency-divided signal output from the first frequency divider.
To the bus, the frequency division signal output from the second frequency divider is supplied to the bus, and the frequency division ratio of the first frequency divider is increased in the power save mode. Therefore, the CPU clock signal and the bus clock signal And the frequency can be changed at the same time.

The PLL synthesizer has at least a PLL circuit having a voltage controlled oscillator and a first frequency divider for dividing an oscillation signal of the voltage controlled oscillator, and a reference oscillator for supplying a reference signal to the PLL circuit. A second frequency divider for dividing the oscillation signal, the oscillation signal being supplied to the CPU, and the frequency division signal output from the second frequency divider being supplied to the bus; Since the frequency division ratio is set to be small in the power save mode, the frequencies of the CPU clock signal and the bus clock signal can be simultaneously changed by the first frequency divider that sets the clock signal.

Further, the voltage controlled oscillator is composed of two voltage controlled oscillators which are selectively selected and one of which constitutes a PLL circuit. In the power save mode, one voltage controlled oscillator is selected to select the power save mode. Since the other voltage controlled oscillator is switched to be selected in the normal mode other than the time, a stable clock signal can be obtained at any frequency.

Further, since the frequency division ratio of the second frequency divider can be changed, the frequency of the bus clock signal can be appropriately set according to the specifications of the computer.

The PLL synthesizer has a first PL having at least a voltage controlled oscillator and a first frequency divider.
L circuit and a second P having at least a voltage controlled oscillator
It comprises an LL circuit and a reference oscillator for supplying a reference signal to the first PLL circuit and the second PLL circuit. The oscillation signal output from the voltage controlled oscillator is supplied to the CPU and output from the voltage controlled oscillator. Since the oscillation signal is supplied to the bus and the frequency division ratio of the first frequency divider is reduced in the power mode, only the frequency of the clock signal can be switched.

Further, the voltage controlled oscillator is composed of two voltage controlled oscillators which are selectively selected and one of which constitutes the first PLL circuit. In the power save mode, one of the voltage controlled oscillators is selected. Since the other voltage controlled oscillator is switched to be selected in the normal mode other than the power save mode, a stable clock signal can be obtained at any frequency.

Further, the second PLL circuit is provided with a second frequency divider for setting the oscillation frequency of the voltage controlled oscillator,
Since the second frequency divider can be changed, the frequency of the flock signal supplied to the bus can be appropriately set independently of the frequency of the clock signal supplied to the CPU.

[Brief description of drawings]

FIG. 1 is a block diagram of a computer of the present invention.

FIG. 2 is a circuit diagram showing a first configuration of a clock signal source used in the computer of the present invention.

FIG. 3 is a circuit diagram showing a second configuration of the clock signal source used in the computer of the present invention.

FIG. 4 is a circuit diagram showing a third configuration of the clock signal source used in the computer of the present invention.

FIG. 5 is a block diagram of a conventional computer.

[Explanation of symbols]

1 CPU 2, 3, 4 peripheral devices 5 buses 6 clock signal source 10 PLL circuit 10a Phase comparator 10b low pass filter 10c Voltage controlled oscillator 10d divider 11 Reference oscillator 12 First frequency divider 13 Second frequency divider 20 PLL circuit 20a Phase comparator 20b low pass filter 20c voltage controlled oscillating means 20c1, 20c2 voltage controlled oscillator 20d switching means 20e First frequency divider 21 Second frequency divider 30 First PLL circuit 30a First phase comparator 30b First low-pass filter 30c Voltage controlled oscillator 30c1, 30c2 voltage controlled oscillator 30d switching means 30e First frequency divider 40 Second PLL circuit 40a Second phase comparator 40b Second low-pass filter 40c voltage controlled oscillator 40d Second frequency divider

Continued front page    F-term (reference) 5B011 EA04 LL13                 5B079 BA01 BC01 BC06 DD02                 5J106 AA04 CC01 CC19 CC20 CC24                       CC41 CC53 DD08 FF03 GG01                       GG09 HH01 HH10 KK33 KK40

Claims (9)

[Claims] 1. A CPU, a plurality of peripheral devices controlled by the CPU, a bus for data transmission between the CPU and the peripheral devices and between the peripheral devices, and the CPU and the bus. A clock signal source for supplying a clock signal, wherein the clock signal source is a PLL synthesizer,
A computer in which the output frequency of the LL synthesizer is lowered. 2. The PLL synthesizer outputs two signals having different frequencies, one of which is a clock signal for the CPU and the other is a clock signal for the bus. The computer according to 1. 3. The PLL synthesizer includes a PLL circuit having at least a voltage controlled oscillator, a reference oscillator for supplying a reference signal to the PLL circuit, and a first frequency divider for dividing an oscillation signal output from the voltage controlled oscillator. A frequency divider and a second frequency divider that divides the frequency-divided signal by the first frequency divider, and supplies the frequency-divided signal output from the first frequency divider to the CPU. At the same time, the frequency division signal output from the second frequency divider is supplied to the bus, and the frequency division ratio of the first frequency divider is increased in the power save mode. The computer according to 2. 4. The PLL synthesizer includes a PLL circuit having at least a voltage controlled oscillation means and a first frequency divider for dividing an oscillation signal of the voltage controlled oscillation means, and the PL circuit.
A reference oscillator that supplies a reference signal to the L circuit and a second frequency divider that divides the oscillation signal are provided. The oscillation signal is supplied to the CPU and is output from the second frequency divider. 3. The computer according to claim 2, wherein a frequency division signal according to the first frequency divider is supplied to the bus to reduce a frequency division ratio of the first frequency divider in the power save mode. 5. The voltage controlled oscillator is composed of two voltage controlled oscillators which are alternatively selected and one of which constitutes the PLL circuit. One of the voltage controlled oscillators is selected in the power save mode. The computer according to claim 4, wherein the other voltage controlled oscillator is switched to be selected in the normal mode other than the power save mode. 6. The configuration according to claim 3, wherein the frequency division ratio of the second frequency divider can be changed.
The computer described in. 7. A first PLL having at least a voltage controlled oscillator and a first frequency divider in the PLL synthesizer.
Circuit and a second PL having at least a voltage controlled oscillator
The CPU includes an L circuit and a reference oscillator that supplies a reference signal to the first PLL circuit and the second PLL circuit, and outputs the oscillation signal output from the voltage controlled oscillation means to the CPU.
3. The oscillation signal output from the voltage controlled oscillator is supplied to the bus to reduce the frequency division ratio of the first frequency divider in the power save mode. Computer. 8. The voltage-controlled oscillator is composed of two voltage-controlled oscillators which are alternatively selected and one of which constitutes the first PLL circuit. One of the voltage-controlled oscillators is used in the power save mode. 8. The voltage control oscillator is selected and switched to select the other voltage controlled oscillator in the normal mode other than the power save mode.
The computer described in. 9. The second PLL circuit is provided with a second frequency divider for setting an oscillation frequency of the voltage controlled oscillator, and the second frequency divider can be changed. The computer according to claim 7, wherein the computer is a computer.