JP2003076343A - Liquid crystal display device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device and its driving method in which multicolor displaying is conducted with low power consumption during a waiting time and halftone gradation displaying and animation displaying are conducted during a call, and to provide its driving method. SOLUTION: ADM (digital memory) switching circuit 17 is conducted between a pixel electrode 13 and a DM 18. During a normal display interval (during a call), a first switching element 14 is periodically turned on and the circuit 17 is turned off and full color video signals being supplied to a signal line 11 are written into the electrode 13 for the displaying. During a still picture displaying interval (during a waiting time), the element 14 is turned off and the circuit 17 is turned on and multicolor video signals held in the DM 18 are written into the electrode 13 for the displaying. During the above operation, rewriting of the DM 18 is conducted using multicolor video signals having different polarities for every prescribed period and the potential of an opposing electrode 15 is reversed along with the above operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having high image quality and low power consumption, which is used in a mobile phone, an electronic book, and the like, and more particularly to a liquid crystal display device having a digital memory and a driving method thereof.

[0002]

2. Description of the Related Art Conventionally, a liquid crystal display device has been used as a display for a small information terminal such as a mobile phone and an electronic book by taking advantage of its light weight, thin shape and low power consumption. Since such a small-sized information terminal generally adopts a battery drive system, low power consumption is an important issue.

In particular, mobile phones are required to be capable of displaying with low power consumption during the standby time, and a technique for realizing this is, for example, Japanese Patent Laid-Open No. 58-58.
23091 and the like. The image display device disclosed herein includes a digital memory in a pixel,
During standby (hereinafter, still image display period), only the AC drive circuit for AC driving the liquid crystal is operated, and other peripheral drive circuits are stopped to significantly reduce power consumption.

[0004]

By the way, recently, color halftone display and moving image display of the Internet and TV phones have begun even in mobile phones, which not only consumes less power during standby, but also displays color in half during communication. There is a demand for high-quality display. However, in the image display device of JP-A-58-23091, since the pixel voltage is limited to binary values, only binary images can be displayed. Therefore, multi-color display is not possible during standby. In addition, there is a problem that halftone display or moving image display in full color cannot be performed even during a call (hereinafter, a normal display period).

An object of the present invention is to provide a liquid crystal display device capable of performing multi-color display with low power consumption during stand-by, and half-tone display or moving image display in full color during a call, and a driving method thereof. .

[0006]

In order to achieve the above object, the invention of claim 1 is arranged at a plurality of scanning lines and a plurality of signal lines which are arranged so as to intersect with each other, and at each intersection of these two lines. ON / OFF control is performed by a scanning signal supplied to the pixel electrode and the scanning line, and a video signal supplied to the signal line is written to the pixel electrode by electrically connecting between the signal line and the pixel electrode when ON. A first substrate including one switch element, a second substrate including a counter electrode facing the pixel electrode with a predetermined gap, and a first substrate and a second substrate. In the liquid crystal display device including a liquid crystal layer, the first substrate includes a digital memory that holds a video signal supplied to the signal line in a writable / readable state, the pixel electrode, and the digital memory. One Characterized in that it comprises a digital memory switching circuit for controlling connection between input and output terminals.

According to a second aspect of the present invention, in the first aspect, the digital memory switch circuit includes a second switch element connected between the pixel electrode and one input / output terminal of the digital memory. Is characterized by.

According to a third aspect of the invention, in the first aspect, the conduction of the second switch element is controlled by a control signal supplied to one control signal line arranged substantially in parallel with the scanning line. It is characterized by

According to a fourth aspect of the present invention, in the first aspect, the digital memory is composed of two inverter circuits and a third switch element.

In a preferred form, the third switch element is a switch element having a channel opposite to that of the first switch element, and the gate of the third switch element is the same as the gate of the first switch element. Connected to the scan line.

In a preferred form, the pixel electrode is a light reflection type pixel electrode made of a metal thin film.

Further, in order to achieve the above-mentioned object, claim 5
In the first display period, in the first display period, the conduction between the pixel electrode and the digital memory is turned off by the digital memory switch circuit, and the first switch element is turned on in a predetermined cycle to connect to the signal line. Display is performed by writing the supplied first video signal into the pixel electrode, and during the second display period, the pixel electrode and the digital memory are electrically connected to each other by the digital memory switch circuit to connect to the signal line. After holding the supplied second video signal in the digital memory, the first switch element turns off the conduction between the signal line and the pixel electrode, and the second video signal held in the digital memory is held. The driving method of a liquid crystal display device according to claim 1, wherein a display is performed by writing a video signal to the pixel electrode, wherein a predetermined period is used in the second display period. A second video signal having a different polarity is supplied for each time to rewrite the digital memory, and the potential of the counter electrode is inverted to the opposite polarity to the potential of the second video signal in accordance with the rewriting. Characterize.

According to a sixth aspect of the invention, in the second display period of the fifth aspect, the predetermined period for rewriting the digital memory is longer than one frame period.

According to a seventh aspect of the present invention, in the fifth aspect, the inversion of the potential of the counter electrode is performed in a frame in which the digital memory is rewritten from a blanking period one frame before the frame in which the digital memory is rewritten. It is characterized in that it is performed within a period excluding the blanking period.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments in which the liquid crystal display device and the driving method thereof according to the present invention are applied to an active matrix type liquid crystal display device having a digital memory will be described below.

FIG. 3 is a circuit configuration diagram of an active matrix type liquid crystal display device according to this embodiment, and FIG. 4 is a schematic sectional view of FIG.

The liquid crystal display device 100 is composed of a display pixel section 110 in which a plurality of display pixels 10 are formed, a scanning line drive circuit 120 and a signal line drive circuit 130.

In this embodiment, the scanning line drive circuit 120 and the signal line drive circuit 13 are provided on the array substrate 101 (FIG. 4).
0 is a signal line 11, a scanning line 12 and a pixel electrode 13 described later
However, the scanning line driving circuit 120 and the signal line driving circuit 130 may be arranged on an external driving substrate (not shown).

In the display pixel section 110, a plurality of signal lines 11 and a plurality of scanning lines 12 intersecting with the signal lines 11 are arranged on the array substrate 101 in a matrix form with an insulating film (not shown) interposed therebetween. A display pixel 10 is arranged at each intersection.

The display pixel 10 is composed of a pixel electrode 13, a first switch element 14, a counter electrode 15, a liquid crystal layer 16, a digital memory switch circuit 17 (DM switch circuit) and a digital memory (hereinafter DM) 18. There is.

In the display pixel 10, the source of the first switch element 14 is the signal line 11, and the gate is the scanning line 12.
The drains are connected to the pixel electrodes 13, respectively. The pixel electrode 13 is connected to the DM 18 via the DM switch circuit 17, and the DM switch circuit 17
Of the gate is the control signal line 19, and the source is the pixel electrode 13
The drains are connected to the DM 18, respectively. D
The configurations of the M switch circuit 17 and the DM 18 will be described later. Although not shown in FIG. 3, each pixel electrode 13
A storage capacitor is electrically connected in parallel to the.

The pixel electrode 13 is formed on the array substrate 101, and the counter electrode 15 facing the pixel electrode 13 is formed on the counter substrate 102 (FIG. 4). Counter electrode 15
A predetermined counter potential is applied to the external drive substrate by a controller IC arranged on an external drive substrate (not shown). A liquid crystal layer 16 is held between the pixel electrode 13 and the counter electrode 15,
The periphery of the array substrate 101 and the counter substrate 102 is sealed by a sealing material 103. Note that illustration of the alignment film, the polarizing plate, and the like is omitted in FIG.

The scanning line drive circuit 120 is composed of a shift register 121, a buffer circuit (not shown), etc., and a vertical clock signal and a vertical start signal as control signals, a power supply voltage, etc. are supplied from a controller IC (not shown). .

The scanning line driving circuit 120 outputs a scanning signal to set the scanning line 12 to the on level and outputs the scanning signal in the normal display period in which halftone display and moving image display are performed, as in a normal active matrix type liquid crystal display device. During the image display period, all the scanning lines 12 are off level. Further, as will be described later, in the still image display period, a control signal of a predetermined level is supplied to the control signal line 19 to control the conduction of the DM switch circuit 17. In addition, the scanning line drive circuit 1 is connected to the control signal line 19.
The control signal may be directly supplied from a controller IC (not shown) without passing through 20.

The normal display period and the still image display period correspond to the first display period and the second display period in this embodiment, respectively.

The signal line drive circuit 130 is composed of a shift register 131, an ASW (analog switch) 132, etc., and is supplied with a horizontal clock signal and a horizontal start signal as control signals, a power supply voltage, etc. from a controller IC (not shown). A video signal is also supplied from the controller IC through the video bus 133. The controller IC (not shown) supplies a full-color video signal during the normal display period and a multi-color video signal during the still image display period. The full-color video signal and the multi-color video signal correspond to the first video signal and the second video signal in this embodiment, respectively.

In the signal line drive circuit 130, the shift register 131 to the ASW1 is driven based on the control signal.
By outputting the opening / closing signal of 32, the video bus 13
3 and the signal line 11 are brought into conduction, and the video signal supplied to the video bus 133 is sampled on the signal line 11 at a predetermined timing.

Here, the basic operation when driving as a normal active matrix type liquid crystal display device will be briefly described.

When a scanning signal is output from the scanning line driving circuit 120 and each scanning line 12 is turned on sequentially from the top every horizontal scanning period, and a video signal is sampled on the signal line 11 in synchronization with this, the scanning signal is turned on. All the first switch elements 14 connected to the level scanning line 12 are turned on for one horizontal scanning period, and the video signal sampled on the signal line 11 is written to the pixel electrode 13 through the first switch element 14. . This video signal is charged as a signal voltage between the pixel electrode 13 and the counter electrode 15 (and an auxiliary capacitor (not shown)), and the liquid crystal layer 16 responds according to the magnitude of this signal voltage, so that each display pixel 10 The amount of transmitted light is controlled. By carrying out such an operation for all the scanning lines 12 within one frame period, an image of one screen is completed.

Next, the circuit configuration of the DM 18 and each switch element included in the display pixel 10 will be described. Figure 1
4 is a circuit configuration diagram of the display pixel 10, and the same portions as those in FIG. 3 are denoted by the same reference numerals.

The DM switch circuit 17 is composed of a DM switch element 21 inserted between the input / output terminal 22 of the DM 18 and the pixel electrode 13. The gate of the DM switch element 21 is connected to a control signal line 19 arranged substantially parallel to the scanning line 12, and an ON or OFF level control signal is supplied from the scanning line driving circuit 120 to the control signal line 19. By doing so, the conduction of the DM switch element 21 is controlled. Both the DM switch circuit 17 and the first switch element 14 are composed of MOS transistors.
Since the DM switch circuit 17 of the present embodiment is composed of one transistor, it is possible to reduce the arrangement area on the substrate and realize high definition of the screen. The DM switch element constitutes the second switch element in this embodiment.

The DM 18 is a memory circuit that holds the video signal supplied from the signal line 11 via the first switch element 14 in a writable / readable state, and includes two inverter circuits 23 and 24 and a third inverter circuit. Switch element 25
It is composed of. Of these, the third switch element 25
Is a switch element having a channel opposite to that of the first switch element 14, and is a complementary MOS to the first switch element 14.
It is composed of transistors. The gate of the third switch element 25 is connected to the same scanning line 12 as the gate of the first switch element 14. Therefore, when the scanning line 12 is turned on, the first switch element 14 is turned on and the third switch element 25 is turned off, so that the input / output terminal 22 of the DM 18 and the output of the inverter circuit 24 are electrically connected. Is separated. At this time, if the control signal line 19 is at the off level, the full-color video signal sampled on the signal line 11 is written to the pixel electrode 13.
If the control signal line 19 is on level, the signal line 1
The multi-color video signal sampled at 1 is written to the pixel electrode 13 and the input / output terminal 22. further,
When the scanning line 12 is turned off, the first switch element 14 is turned off and the third switch element 25 is turned on, and DM
Since the input / output terminal 22 of 18 and the output of the inverter circuit 24 are electrically connected, the multi-color video signal written in the input / output terminal 22 is held in the DM 18.

Next, the operation of the liquid crystal display device 100 of the present embodiment having the above-described configuration during the normal display period and the still image display period will be described with reference to FIG.
FIG. 2 is a timing chart showing the relationship between the operation of the drive circuit and the signal waveform in each display mode.

First, in the normal display period, the control signal line 19
Is turned off and the function of the DM switch circuit 17 is stopped. During this time, by supplying a control signal and a video signal for full color to the scanning line driving circuit 120 and the signal line driving circuit 130, respectively, and performing driving similarly to a normal active matrix type liquid crystal display device,
Performs high-quality halftone / moving image display in full color.

Next, when switching from the normal display period to the still image display period, in the last one frame (still image writing frame) when the normal display is switched to the still image display,
The control signal line 19 is turned on. Then, while the first switch element 14 is turned on by the scanning signal of the on level, the multi-color video signal is sampled on the signal line 11, and this is sampled by the first switch element 14 and the DM.
The DM 18 is written through the switch element 21. When the scanning line 12 is turned off in this state, the third switch element 25 remains on, so that the multi-color video signal is held in the DM 18.

The multi-color video signal written in the DM 18 can be held as it is for a short time, but if it is held for a long time, the liquid crystal layer 16 is deteriorated due to the DC component, and therefore the AC drive is performed. There is a need. In the present embodiment, in the still image display period, multi-color video signals having different polarities are written (rewritten) at predetermined intervals, and at the same time, the potential of the counter electrode 15 has a polarity opposite to that of the rewritten video signal. AC drive is realized by reversing.

The cycle for rewriting the multi-color video signal may be set to a range in which the deterioration of the liquid crystal layer 16 is not caused by the DC component, and may be set to be longer than at least one frame period. However, when rewriting the multi-color video signal, it is necessary to operate the scanning line driving circuit 120 and the signal line driving circuit 130 for only one frame period, and if the rewriting cycle is short, power consumption increases. Therefore, it is preferable to rewrite every few frames to tens of seconds.

The reversal of the potential of the counter electrode 15 is shown in FIG.
As shown in FIG. 5, it is preferable to perform it within a period excluding the blanking period one frame before the still image writing frame and the blanking period of the still image writing frame (A in the figure). In FIG. 2, the potential is inverted immediately before the start of the blanking period one frame before each still image writing frame.

When the potential of the counter electrode 15 is inverted between the blanking period one frame before the frame for writing and the blanking period for the frame for writing, the potential of the written video signal and the counter electrode 15 are reversed. This is because when the potentials have the same polarity, a meaningless unnecessary image is displayed for a short time. However, when the potential of the counter electrode 15 is reversed within the period other than the above period, the potential of the written video signal and the counter electrode 15 are reversed.
Since the potentials of are opposite in polarity to each other, an unnecessary image is not displayed, and good display quality can be obtained.

Next, when switching from the still image display to the normal display, the control signal line 19 is turned off at the start of the normal display period and the scanning line drive circuit 120 and the signal line drive circuit 130 are respectively supplied with control signals, Supply power supply voltage and full color video signal.

According to the above-described embodiment, during the still image display period, the potential of the pixel electrode 13 is changed by rewriting the multi-color video signal at predetermined intervals and inverting the potential of the counter electrode 15. High power / low power is output alternately, and the potential of the counter electrode 15 is low power /
Will shift between high power supplies. As a result, no voltage is applied to the liquid crystal layer 16 in the display pixel 10 having the same polarity as that of the counter electrode 15 and no voltage is applied to the liquid crystal layer 16 in the display pixel 10 having the opposite polarity, so that multi-color display can be performed. During this period, the display pixel unit 110 operates only because the low-frequency control signal line 19 and the counter electrode 15 and the drive circuit operate only for one frame period at a predetermined cycle, so that low power consumption and multi-color operation are performed. The display can be done.

When the pixel electrode 13 is a light reflection type pixel electrode made of a metal thin film, a backlight is not required, so that power consumption is lower than that of a transmission type structure using a backlight. Can be driven.

[0043]

As described above, according to the liquid crystal display device and the driving method thereof according to the present invention, multi-color display with low power consumption is performed during standby, and full-color halftone display or moving image display is performed during a call. It can be carried out.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a display pixel.

FIG. 2 is a timing chart showing the relationship between the operation of the drive circuit and signal waveforms in each display mode.

FIG. 3 is a circuit configuration diagram of an active matrix type liquid crystal display device according to an embodiment.

4 is a schematic cross-sectional view of FIG.

[Explanation of symbols]

10 ... Display pixel, 11 ... Signal line, 12 ... Scan line, 13 ...
Pixel electrode, 14 ... First switch element, 15 ... Counter electrode, 17 ... DM switch circuit, 18 ... Digital memory (DM), 19 ... Control signal line, 21 ... DM switch element (second switch element), 22 ... Output terminals, 23, 24
... Inverter circuit, 25 ... Third switch element, 100
... liquid crystal display device, 110 ... display pixel portion, 120 ... scanning line drive circuit, 130 ... signal line drive circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 624C (72) Inventor Takashi Maeda 1-9-2 Harara-cho, Fukaya-shi, Saitama F-term in Toshiba Fukaya Plant (Reference) 2H093 NC22 NC28 NC34 ND06 ND17 ND39 5C006 AA21 AC26 AF44 BB16 BC06 BF09 BF27 BF34 EB05 FA47 5C080 AA10 BB05 CC03 DD26 EE30 FF11 JJ02 JJ03 JJ04 KK07 KK47

Claims (7)

[Claims] 1. A plurality of scanning lines and a plurality of signal lines arranged to intersect each other, a pixel electrode arranged at each intersection of these lines, and an on / off control by a scanning signal supplied to the scanning lines. And a first substrate including a first switch element for electrically connecting the signal line and the pixel electrode to write the video signal supplied to the signal line to the pixel electrode when turned on; A second substrate including counter electrodes arranged to face each other with a gap; the first substrate and the second substrate;
In a liquid crystal display device including a liquid crystal layer held between the first substrate and the substrate, the first substrate holds a digital memory that holds a video signal supplied to the signal line in a writable / readable state, And a digital memory switch circuit for controlling conduction between the pixel electrode and one input / output terminal of the digital memory. 2. The digital memory switch circuit comprises:
The liquid crystal display device according to claim 1, comprising a second switch element connected between the pixel electrode and one input / output terminal of the digital memory. 3. The conduction of the second switch element is controlled by a control signal supplied to one control signal line arranged substantially parallel to the scanning line. Liquid crystal display device. 4. The liquid crystal display device according to claim 1, wherein the digital memory includes two inverter circuits and a third switch element. 5. In the first display period, conduction between the pixel electrode and the digital memory is turned off by the digital memory switch circuit, and the first switch element is turned on at a predetermined cycle to change the signal line. First supplied to
The image signal is written in the pixel electrode to perform display, and in the second display period, the pixel electrode and the digital memory are electrically connected by the digital memory switch circuit to be supplied to the signal line. Image signal of the pixel is held in the digital memory, conduction between the signal line and the pixel electrode is turned off by the first switch element, and the second image signal held in the digital memory is stored in the pixel. The method for driving a liquid crystal display device according to claim 1, wherein display is performed by writing in electrodes, wherein the second digital image signal is supplied by supplying a second video signal having a different polarity every predetermined period in the second display period. A liquid crystal display device, characterized in that the memory is rewritten, and the electric potential of the counter electrode is inverted to a polarity opposite to the electric potential of the second video signal in accordance with the rewriting. Driving method. 6. The method of driving a liquid crystal display device according to claim 5, wherein the predetermined cycle for rewriting the digital memory in the second display period is longer than one frame period. 7. The inversion of the potential of the counter electrode is a period excluding a blanking period one frame before a frame in which the digital memory is rewritten and a blanking period in a frame in which the digital memory is rewritten. The method for driving a liquid crystal display device according to claim 5, wherein the method is performed in the interior.