JP2003076331A - Display device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress dispersion in luminance caused by transistors which drive EL elements. SOLUTION: The display device is provided with pixels 10P and 10Q which include EL elements and are provided at the crossing points of scanning lines 112a and data lines 114, a data side output circuit 170 which controls gradation voltages Vd1, Vd2, etc., Vd(n/2) that correspond to the gradation of the pixels corresponding to the crossings of selection scanning lines by gradation currents corresponding to the gradation and outputs the voltages and a data voltage operating circuit 180 which operates data voltages to be applied to common lines 118b so that currents flowing into the EL elements through common lines 118a agree with the gradation currents that control the gradation voltages when odd number row scanning lines 112a are selected and operates data voltages to be applied to the common lines 118a so that currents flowing into the EL elements through the lines 118b agree with the gradation currents that control the gradation voltages when even number row scanning lines 112a are selected.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an organic EL (Electr
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device that performs display using a self-luminous element such as a Luminescent) or an LED (Light Emitting Diode), a drive circuit for the display device, a drive method, and electronic equipment.

[0002]

2. Description of the Related Art In recent years, mobile phones and PDAs (Personal Dig
For electronic devices such as ital Assistance), organic EL and LE
Display devices that perform display by self-luminous elements such as D are being used. The reason for this is that compared to liquid crystal devices used as similar display devices, the contrast ratio is high, the viewing angle dependence is low, the response is fast, and no backlight or front light is required. This is because, along with this, it is evaluated that it is advantageous for thinning (lowering power consumption depending on conditions).

A display device for displaying by a self-luminous element is
When classified according to the driving method, similar to liquid crystal devices, it is roughly classified into an active matrix type in which pixels are driven by using active elements such as transistors, and a passive matrix type in which pixels are driven without using active elements. You can Among them, in the former active matrix type, since display can be controlled for each pixel, a high display capability can be secured even if the resolution is increased, and
Since a small amount of current can be passed through the pixel for a relatively long time, the driving voltage is low, and it is advantageous in reducing power consumption. It is considered to be advantageous compared to the latter passive matrix type. .

[0004]

However, in the display device of the active matrix type among the display devices which perform display by the self-luminous element, the display quality is deteriorated due to the variation in the characteristics of the transistor for each pixel. There was a problem such as doing. That is, if the characteristics of the transistor vary, the amount of current flowing through the light emitting element also varies, and as a result, the brightness of pixels that should be identical to each other differs from pixel to pixel, resulting in deterioration of display quality. In order to solve the above problems, an object of the present invention is to provide a display device and an electronic device capable of preventing the deterioration of display quality due to the variation in the characteristics of transistors.

[0005]

In order to achieve the above object, the display device according to the present invention corresponds to different scanning lines at the intersection of the scanning line and the data line, and each scanning line corresponds to the corresponding scanning line. A first switch that is closed or opened according to a scanning signal supplied to the line; a capacitor that holds a data voltage applied to the data line when the first switch is closed; The transistor that uses the held data voltage as a gate voltage, the light emitting element that is connected to one of the source and the drain of the transistor, and the other of the source and the drain of the transistor are shared if the first switch is closed. A pixel having a second switch connected to a line and a second switch connected to a power supply line of a power supply voltage during a period in which the first switch is opened; None, when the first switch is closed, there is no difference between the shared line for passing a current through the light emitting element and the grayscale current corresponding to the grayscale of the pixel and the current flowing through the shared line. And a data voltage operating circuit for operating the data voltage applied to the data line. According to this configuration, when the first switch is closed, the data voltage applied to the data line is held by the capacitance, and the other of the source and the drain of the transistor is connected to the common line by the second switch. Therefore, a current corresponding to the data voltage flows to the light emitting element via the shared line by the transistor. Here, since the data voltage operation circuit operates the data voltage applied to the data line in the direction of eliminating the difference between the gradation current according to the gradation of the pixel and the current flowing through the light emitting element via the shared line, The current flowing through the light emitting element accurately matches the gradation current. During the period in which the first switch is opened, the other of the source and the drain of the transistor is connected to the power supply line of the power supply voltage by the second switch, so that the data voltage held in the capacitor, specifically,
The current according to the data voltage in which the current flowing through the EL element substantially matches the gradation current continues to flow through the light emitting element. Therefore, even if the characteristics of the transistors vary, the currents flowing in the light emitting elements are aligned with each other at the same brightness,
It is possible to prevent the deterioration of the display quality due to the difference in the luminance of the pixels that should be the same. Further, since the data line and the common line can be shared over a plurality of pixels provided corresponding to the intersections of the scanning lines and the data lines, the configuration can be simplified. Note that the capacitance here is a concept including a storage capacitance whose one end is connected to a gate of a transistor and a parasitic capacitance of the gate.

In this structure, the number of pixels provided corresponding to the intersection of the scanning line and the data line is 2, and when the scanning line corresponding to one of the two pixels is selected, the other one is selected. It is preferable that the data line for the pixel is switched as the shared line for the one pixel and the shared line for the other pixel is switched as the data line for the one pixel.
According to this aspect, in the two pixels provided corresponding to the intersection, the data line and the common line are shared, and the data line and the common line are reversibly switched as the common line and the data line, respectively.

Further, the display device according to the present invention corresponds to different scanning lines at the intersections of the scanning lines and the data lines, each of which is closed or closed according to the scanning signal supplied to the corresponding scanning line. A first switch that is opened and closed, a capacitor that holds a data voltage applied to the data line when the first switch is closed, and a transistor that uses the data voltage held by the capacitor as a gate voltage A pixel including a light emitting element connected to one of a source and a drain of the transistor, a shared line for supplying a current to the light emitting element when the first switch is closed, and a source of the transistor. Alternatively, the other of the drains is connected to the shared line when the first switch is closed and connected to the shared line while the first switch is open and closed. At the same time, when the second switch that connects the common line to the power supply line of the power supply voltage and the first switch are closed, a grayscale current corresponding to the grayscale of the pixel and the common line flow to the common line. It is characterized by including a data voltage operating circuit for operating the data voltage applied to the data line in the direction of eliminating the difference from the current. With this configuration as well, the current flowing through the light emitting element substantially matches the gradation current with high accuracy, so that the deterioration of display quality due to the difference in the luminance of the pixels that should be the same can be prevented. Further, the shared line has a function of supplying a current to the EL element when the data voltage is operated and a function of a power supply line for keeping the current flowing to the EL element during the period when the first switch is opened. Therefore, it is possible to simplify the configuration.

Further, since the electronic apparatus according to the present invention has the above-mentioned display device, it is possible to make the luminance uniform and to improve the display quality. Examples of such electronic devices include personal computers, digital still cameras, mobile phones, and the like.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment> First, a display device according to a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of this display device. As shown in this figure, in the display device 100, the scanning lines 112a and the auxiliary scanning lines 112b are paired with each other to form m lines,
While extending in the row (X) direction, the data lines 114 and the common lines 116 form a pair and extend in n lines and in the column (Y) direction, respectively (m and n are integers of 2 or more). Is).

Next, the scanning line drive circuit 160 is an m-stage shift register for sequentially transferring the pulsed signal DY in accordance with a clock signal YCK having a cycle of one horizontal scanning period (1H). Specifically, the scanning line driving circuit 160
3 sequentially shifts the signal DY supplied at the beginning of one vertical scanning period (1F) at each rising edge of the clock signal YCK as shown in FIG.
The shift signals of the m stages are 1, 2, 3, ..., M, respectively.
The scanning signal Y is applied to each of the scanning lines 112a in the row.
It is supplied as 1, Y2, Y3, ..., Ym. For this reason,
For the scanning signals Y1, Y2, Y3, ..., Ym, the signal DY is L
Only when the clock signal YCK rises for the first time after reaching the level, the level becomes the L level for one horizontal scanning period in order. Here, generally, the scanning signal Y supplied to the scanning line 112a of the i-th row (i is an integer satisfying 1 ≦ i ≦ m)
When i becomes L level, it indicates that the scanning line 112a is selected.

Then, an inverter 162 is provided in each row of the scanning lines 112a. Generally, the inverter 162 of the i-th row is an inverted scan signal / inverted from the scan signal Yi.
Yi is supplied to the auxiliary scanning line 112b on the i-th row (/ indicates inversion).

On the other hand, the data side output circuit 170 sequentially samples the gradation data Dpix of the pixels located on the selected scanning line and outputs the gradation voltage corresponding to the gradation data Dpix for each column. Here, the gradation data Dpix is
Data that indicates the gradation of a pixel with a digital value,
It is supplied from a host device (not shown) in the order described below. Further, for convenience of description, the gradation voltages output corresponding to the 1, 2, 3, ..., N columns are respectively Vd1, Vd2, and Vd.
It is written as 3, ..., Vdn. Further, the data voltage operation circuit 180 is provided for each column. Here, in general, the data voltage operation circuit 180 of the j-th column is
And the data voltage Xaj applied to the data line 114 in the j-th column is operated according to the current flowing in the shared line 116 in the j-th column. The details of the data side output circuit 170 and the data voltage operation circuit 180 will be described later.

On the other hand, the scanning line 112a (complementary scanning line 112
Pixels 10 are arranged corresponding to the intersection of b) and the data line 114 (common line 116). Therefore, the resolution of the display device 100 is m dots vertically × n dots horizontally. However, the present invention is not limited to this resolution.

<Pixel> Next, details of the pixel 10 described above will be described. FIG. 2 generally shows the scan line 11 of the i-th row.
FIG. 6 is a circuit diagram showing a configuration of a pixel 10 corresponding to an intersection of 2a and a data line 114 of a jth column. As shown in this figure, in one pixel 10, P-channel type thin film transistors (Thin Film Transistor, hereinafter abbreviated as “TFT”) 122, 124, 126, 128 and an EL element 130.
And are provided. Of these, the TFT 122 is interposed between the data line 114 of the j-th column and the gate G of the TFT 124. The gate of the TFT 122 is connected to the scanning line 112a on the i-th row. Therefore, TFT1
22 functions as a switch that is turned on when the scanning signal Yi becomes L level. Further, the capacitor 50 is parasitic on the gate G of the TFT 124.

Subsequently, the gate is the scanning line 112a of the i-th row.
The TFT 126 connected to is connected between the shared line 116 of the j-th column and the source S of the TFT 124. Further, the gate whose gate is connected to the auxiliary scanning line 112b of the i-th row is T
The FT 128 is a power supply line of the power supply voltage Vcc and the TFT 124.
The source S is inserted. Here, since the scanning signal Yi and the inverted scanning signal / Yi are in a logically inverted relationship with each other, the TFTs 126 and 128 are exclusively turned on and off. That is, the TFTs 126 and 12
If the scanning signal Yi is at L level, the signal 8 is turned on and off respectively, and the source S of the TFT 124 is connected to the common line 116.
On the other hand, when the scanning signal Yi is at the H level, it turns off and on, respectively, and functions as a switch that connects the source S of the TFT 124 to the power supply line of the voltage Vcc.

The drain D of the TFT 124 is the EL element 1
It is connected to 30 anodes. Here, the EL element 130
Is a structure in which a light emitting (EL) layer is sandwiched between a pixel electrode which is an anode and a cathode, and light is emitted with a brightness according to an electric current.
Since the details are not directly related to this case, the description is omitted. The cathode of the EL element 130 is common to all the pixels 10 and is grounded to the ground line (feed line) of the reference voltage Gnd. In this embodiment,
The power supply line of the voltage Vcc and the ground line of the voltage Gnd are commonly provided over all the pixels 10, but are omitted for the sake of simplicity of the drawing.

In this pixel 10, when the scanning signal Yi becomes L level, the TFT 122 is turned on, so that the charge corresponding to the data voltage Xaj is accumulated in the capacitor 50 and
The gate voltage of the TFT 124 is the same as the data line 114 of the jth column.
Becomes the data voltage Xaj applied to. In addition, TFT1
26 is turned on and TFT 128 is turned off.
The voltage of the common line 126 is applied to the source S of No. 4.
Therefore, when the scanning signal Yi is at the L level, the EL element 130 receives a current corresponding to the data voltage Xaj in the TFT1.
24 will flow. On the other hand, if the scanning signal Yi is at the H level, the TFT 122 turns off, but the TFT
The gate voltage of 124 is held by the capacitor 50 at the data voltage Xaj immediately before the TFT 122 is turned off.
Further, since the TFT 126 is turned off and the TFT 128 is turned on, the drain of the TFT 124 becomes the voltage Vcc. Therefore, even if the scanning signal Yi becomes H level, a current according to the held data voltage Xaj continues to flow through the TFT 124 in the EL element 130.

Strictly speaking, regarding the gate voltage of the TFT 124, the voltage drop in the TFT 122 is
Regarding the drain voltage of the FT 124, the voltage drop in the TFT 126 or 128 must be taken into consideration, but in the present embodiment, the influence of these voltage drops is ignored. Further, in the present embodiment, the capacitance parasitic to the TFT 124 is used as the capacitance 50.
A capacitor may be provided between the gate G of T124 and the constant potential line (for example, the ground line of the voltage Gnd) and the capacitor may be used as the capacitance 50.

<Data Side Output Circuit> Next, details of the data side output circuit 170 will be described. Figure 4
3 is a block diagram showing a configuration of a data side output circuit 170. FIG. As shown in this figure, the data side output circuit 170
Has a shift register 1710 having the same number of stages as the number n of data lines 114, a register (Reg) 1720, a latch circuit (L) 1730, and a D / A converter 1740. Of these, the latter three are , Shift register 1710 is provided corresponding to each stage.

First, the shift register 1710 sequentially shifts the pulse-shaped signal DX output at the timing of starting the supply of the grayscale data Dpix for one row at each rising edge of the clock signal XsCK to obtain the sampling control signal Xs1, Output as Xs2, Xs3, ..., Xsn.
Then, generally, the register (Reg) 1720 of the j-th column
Is the gradation data D supplied via the data bus 172.
pix is sampled at the rising edge of the sampling control signal Xsj output from the j-th stage of the shift register 1710 and held. Further, in general, the latch circuit (L) 1730 on the j-th column is similar to the register 172 on the j-th column.
The gradation data Dpix held by 0 is latched and output at the rising edge of the latch pulse LP supplied at the start of the horizontal scanning period. Then, generally, the j-th column D / A converter 1740 outputs the grayscale data Dpix, which is also latched by the j-th column latch circuit 1730, as an analog grayscale voltage Vdj.

In this embodiment, the gradation voltage Vdj is
It is defined as the following formula. Vdj = Ra · Id + Vcc (1) In this equation (1), Ra is the D / A converter 1740.
Is a resistance value connected to the output terminal of the EL device, and Id is EL at the brightness of the gradation indicated by the gradation data Dpix.
It is the value of the gradation current required for the element 130 to emit light. The voltage Vcc is the same as that of the TFT 12 as described above.
8 is a power supply voltage applied to the EL element 130 when 8 (see FIG. 2) is turned on. That is, the gradation voltage Vdj is
It will be defined by a function of the current value Id.

Next, FIG. 5 is a timing chart for explaining the operation of the data side output circuit 170. As shown in this figure, when the signal DX rises to the H level prior to the timing when the latch pulse LP is output and the scanning signal Yi transits to the L level, the i-th row is 1, 2, 3 ,. The gradation data Dpix corresponding to the pixels in the nth column are sequentially supplied.

Of these, when the sampling control signal Xs1 output from the shift register 1710 rises to the H level at the timing when the gradation data Dpix corresponding to the pixel in the i-th row and the 1-th column is supplied, the gradation data is changed.
Register 1720 in the first column (in FIG. 5, “1: Re
g ”). Next, when the sampling control signal Xs2 rises to the H level at the timing when the grayscale data Dpix corresponding to the pixel in the i-th row and the 2nd column is supplied, the grayscale data is stored in the register 1720 in the second column (in FIG. 5). “2: Reg”). Similarly, 3, 4,
The gradation data Dpix corresponding to the pixels in the nth column are sampled by the registers 1720 in the third, fourth, ..., Nth columns, respectively.

Subsequently, when the latch pulse LP is output, the grayscale data Dpix sampled by the registers 1720 of the respective columns are latched all at once by the latch circuits 1730 corresponding to the respective columns. The gradation data Dpix latched in the 1st, 2nd, 3rd, ...
The gradation voltages Vd1 and Vd are converted by the A converter 1740 and are converted.
2, Vd3, ..., Vdn are output all at once. By the way, the data-side output circuit 17 described here
0 is an example, and the gradation voltages Vd1, Vd2, Vd
Any configuration may be used as long as it is possible to output 3, ..., Vdn all at once. For example, not the digital data such as the gradation data Dpix, but the gradation voltages Vd1 and Vd
2, Vd3, ..., Vdn are sequentially taken in as analog voltages, and the gradation voltage Vd corresponding to the 1, 2, 3 ,.
, Vdn, Vd3, ..., Vdn may be output all at once.

The scanning signal Yi becomes L level in synchronization with the output operation of the gradation voltage, that is, in synchronization with the output of the latch pulse LP, and the scanning line 112 of the i-th row.
a will be selected. Also here, i
While paying attention to the scanning line 112a in the row, the output operation of the grayscale voltage corresponding to the pixels located in the row has been described.
Actually, such an output operation is performed by the scanning line driving circuit 16
According to the selection by 0, the first line, the second line,
The scanning lines 112a on the third line, ..., And the m-th line are sequentially executed.

<Data Voltage Manipulation Circuit> Next, details of the data voltage manipulation circuit 180 will be described. Here, FIG.
Is a data voltage operating circuit 18 that generally corresponds to the j-th column.
It is a circuit diagram which shows the structure of 0. First, shared line 1 in column j
16 is a variable resistor 180 whose resistance value is adjusted to Ra.
2 is connected to one end of the resistor 1802, and the other end of the resistor 1802 is connected to the gradation voltage V by the D / A converter 1740 in the jth column.
dj is applied. Here, for convenience of description, the voltage of the common line 116 is described as Vdet.

Next, the shared line 116 is connected to the comparator 18
04 is connected to the negative input terminal, while its positive input terminal is connected to the power supply line of voltage Vcc. Comparator 18
04 is the voltage Vdet at the negative input end and the voltage Vc at the positive input end
If the voltage Vdet exceeds the voltage Vcc, the L level signal is output while the voltage Vdet is compared to the voltage Vd.
If it is cc or less, an H level signal is output. The output terminal of the comparator 1804 is connected to the gate of the N-channel type TFT 1810 via the resistor 1806, while the gate of the TFT 1810 is grounded via the capacitor 1808. Therefore, the comparator 1804
The output signal of the resistor 1806 and the capacitor 1808
The smoothing voltage Vg is applied to the gate of the N-channel TFT 1810 while being smoothed by the integrating circuit consisting of.

The source of the TFT 1810 is connected to the power supply line of the voltage Va, while the drain of the TFT 1810 is connected to the data line 114 of the j-th column and also to the power supply line of the voltage Vb via the resistor 1812. ing. The voltage Va
> Voltage Vb.

<Display Operation> Next, the display operation of the display device 100 will be described. As described above, the scanning line driving circuit 160 causes the scanning signals Y1, Y2, Y3, ..., Y.
m is sequentially and exclusively set to the L level every one horizontal scanning period (1H) (see FIG. 3). Here, in general, when the scanning signal Yi of the i-th row becomes the L level, the data-side output circuit 17
Grayscale data Dpix that indicates the brightness of the pixel located in the i-th row 1, the i-th row 2, the i-th row 3, ...
Are respectively converted to voltages Vd1, Vd2, Vd3,
.., Vdn are output as described above.
Therefore, here, focusing on the pixel on the i-th row and the j-th column, the operation in the state in which the scanning line in the i-th row is selected and the operation in the non-selected state after the selection will be described separately. .

<Selection state> FIG. 7 shows the scanning line 11 of the i-th row.
FIG. 7 is a diagram for explaining an operation in the pixel 10 in the i-th row and the j-th column in the state where 2a is selected. First, when the scanning line 112a of the i-th row is selected, the scanning signal Yi becomes L level, so the TFTs 122 and 126 are turned on, and
Since the inversion scanning signal / Yi becomes H level, the TFT 12
8 turns off. Therefore, a current corresponding to the data voltage Xaj immediately after the start of selection is applied to the EL element 130 in the i-th row and the j-th column.
Resistor 1802 → shared line 116 → TFT 126 → TFT 1
24 → (EL element 130) → ground line.

While the scanning signal Yi is at the L level, the other end of the resistor 1802 in the data voltage operation circuit 180 in the jth column corresponds to the pixel in the ith row and the jth column and is represented by the equation (1). The gradation voltage Vdj (= Ra · Id + Vcc) is applied by the data side output circuit 170. The current value Id that defines the gradation voltage Vdj is, as described above, a current value required for the EL element 130 to emit light at the brightness of the gradation indicated by the gradation data Dpix. That is, the gradation current Vdj is a voltage conversion of the target value of the current to be passed through the EL element 130. On the other hand, when a current flows through the EL element 130 via the above path, a voltage represented by the product of the current value and the resistance value Ra is generated across the resistor 1802.
The voltage Vdet at one end of 6 has a value obtained by subtracting the voltage drop of the resistor 1802 from the gradation voltage Vdj.

Therefore, if the current value actually flowing through the EL element 130 matches the target current value Id,
The voltage Vdet should be the voltage Vcc.
However, since the data voltage Xaj immediately after the start of selection hardly reflects the gradation voltage Vdj, the voltage Vdet often does not match the voltage Vcc. Therefore, in the present embodiment, during the period in which the scanning signal Yi is at the L level, the voltage Vd
The data voltage Xaj is manipulated so that et becomes the voltage Vcc, and control for matching the value of the current actually flowing through the EL element 130 with Id is executed.

Specifically, when the current value actually flowing through the EL element 130 is smaller than the target current value Id, the voltage Vdet
Becomes higher than the voltage Vcc. For this reason, the period during which the output signal of the comparator 1804 is at the L level becomes long, and the voltage Vg becomes relatively low.
Since the on resistance of the resistor increases, the on resistance and the resistance 181
The data voltage Xaj obtained by dividing the voltage (Va-Vb) by 2 decreases from the state immediately after the start of selection. That is, when the current value flowing through the EL element 130 is smaller than the target current value Id, control is performed in the direction of increasing the current value flowing through the EL element 130.

On the contrary, when the current value flowing through the EL element 130 is larger than the target current value Id, the voltage Vdet becomes equal to the voltage Vd.
It becomes lower than cc. For this reason, the voltage Vg becomes relatively high and the ON resistance of the TFT 1810 decreases,
The data voltage Xaj rises from the state immediately after the start of selection. That is, when the current value flowing through the EL element 130 is larger than the target current value Id, control is performed in the direction of decreasing the current value flowing through the EL element 130.

After all, the current flowing through the EL element 130 is stabilized at the point where the control in the above two directions is balanced, that is, at the point where the voltage Vdet becomes the voltage Vcc, and as a result, the target current value Id is obtained. Will match. Therefore, in the present embodiment, even if the current value flowing in the EL element 130 is different from the target current value Id immediately after the selection of the i-th row scanning line 112a is started, the target current value is reached immediately before the selection is completed. It will match Id.

When the voltage Vdet matches the voltage Vcc, the period in which the output signal from the comparator 1804 is at the L level and the period in which the output signal is at the H level are unit periods (for example, sufficiently shorter than one horizontal scanning period). If we consider it based on the period, it will be 50% each. The voltage (Va-Vb) is divided by the resistance of the TFT 1810 and the resistance 1812 when the smoothed voltage Vg of the output voltage is used as the gate voltage, and this divided voltage is used as the data voltage on the data line 114. Is applied. Therefore, the divided voltage is the gate voltage of the TFT 124 that makes the current value flowing through the EL element 130 match the target value Id, and is the data voltage.

<Non-selected state> Next, the scanning line 11 of the i-th row
The operation in the non-selected state after 2a is selected will be described. FIG. 8 is a diagram for explaining the operation in the pixel 10 in the i-th row and the j-th column when the scanning line 112a in the i-th row is not selected.

With the transition from the selected state to the non-selected state, the scanning signal Yi transits from the L level to the H level. Therefore, the TFT 122 is turned off, but the TFT 12
The gate voltage of 4 is set to the data voltage Xaj immediately before the end of the selection of the scanning line 112a in the i-th row, specifically, to the data voltage Xaj that causes the current value flowing through the EL element 130 to be the target current value Id. Is held.

Further, the TFT 126 is turned off with the transition of the scanning signal Yi to the H level, and the inverted scanning signal / Yi is transitioned to the L level, so that the TFT 128 is turned on. As a result, the source S of the TFT 124 is turned on. The connection destination is j
The shared line 116 in the column is switched to the power supply line having the voltage Vcc. However, the voltage applied to the common line 116 is
The voltage applied to the source S of the TFT 124 is Vcc even when the connection destination is switched, because the voltage is controlled to match the voltage Vcc until just before the selection of the i-th row scanning line 112a is completed. Does not change.

Therefore, the path of the current flowing through the EL element 130 in the i-th row and the j-th column is the feed line of the voltage Vcc → the TFT 12
8 → TFT 124 → (EL element 130) → ground line, but the gate voltage of the TFT 124,
Also, none of the source-drain voltage changes at all immediately before the scan signal Yi transits to the H level. Therefore, the EL element 130 changes from the selected state to the non-selected state, and after one vertical scanning period has elapsed, until the selected state is restored again, the EL element 130 has a luminance at a current corresponding to the data voltage Xaj held by the capacitor 50. That is, light emission is continued at the brightness of the gradation designated by the gradation data Dpix.

Although the pixel 110 in the i-th row and the j-th column is generally described here, the scanning signal Yi is L.
During the level period, similar control operations are simultaneously executed for the other columns. Further, focusing on the period in which the scanning signal Yi is at the L level, the scanning signals Y1, Y2, Y
, ..., Ym are, as described above, one horizontal scanning period (1
H), the L level is sequentially and exclusively set (see FIG. 3), so that the control operation is sequentially performed for each row.

As described above, the display device 1 according to the present embodiment
In 00, even if the current value flowing through the EL element 130 is different from the target current value Id immediately after the selection is started, it is controlled so as to match the target current value Id by the time immediately before the selection is completed, and after the selection is completed. Also is maintained at the current value Id.
Therefore, even if the characteristics of the TFTs 124 vary from pixel to pixel, and even if all the pixels have the same gradation, the current flowing through each EL element 130 is changed to a current value corresponding to the gradation. Since it can be almost equalized to Id, the brightness in the display surface is made uniform, and as a result, high-quality display is possible.

Further, in the present embodiment, if the current value flowing through the EL element 130 at the time of selection is Id, the shared line 116 is controlled so as to match the voltage Vcc, so that it is not selected from the time of selection. When transitioning from time to time,
The source S of the TFT 124 is maintained at the voltage Vcc. The reason for adopting such a configuration is as follows. That is, when the TFT 124 that controls the current flowing through the EL element 124 is formed by a polysilicon process, even if the gate voltage is constant, if the source / drain voltage is different, the flowing current will also be different.
This is to prevent this.

<Comparison with Existing Technique> Here, three types of existing techniques will be described for comparison with the present embodiment.

First, the first technique will be described. Figure 2
FIG. 6 is a circuit diagram showing a main part of a display device to which the first technique is applied, particularly a pixel configuration. As shown in this figure, the pixel 10 is provided corresponding to the intersection of the scanning line 112 and the data line 114, and the switching TFT 11 is provided.
And a TFT 13 for driving the EL element 130. In this structure, when the TFT 11 is turned on, TF
The parasitic capacitance (or storage capacitance) 5 is applied to the gate G of T13.
By 0, the voltage of the data line 114 at the time of the ON state is held. Furthermore, a current I corresponding to the gate voltage is discharged from the TFT 13.

Therefore, by selecting the scanning lines one by one,
When a selection signal for turning on the TFT 11 is supplied to the selected scanning line 112a and a voltage according to the brightness is applied to the data line 114, the voltage is changed to the TFT 11
Since the parasitic capacitance 50 holds even after turning off, the current according to the holding voltage continues to flow in the EL element 130. Therefore, the EL element 130 continues to emit light with the brightness according to the voltage of the data line 114 when the scanning line 112 is not selected.

However, in the first technique, the TFT1
The characteristic of No. 3 directly affects the current flowing through the EL element 130. That is, if the characteristics of the TFT 13 vary, the amount of current flowing through the EL element 130 also varies from pixel to pixel. As a result, it is not possible to maintain the uniformity of brightness within the display surface, and the quality of the display screen is likely to deteriorate. There are drawbacks.

In order to eliminate this drawback, the second
And a third technique is known. FIG. 19 is a circuit diagram showing a configuration of a main part of a display device to which the second technique related to the former is applied. In the configuration shown in this figure, first, with the TFT 27 turned off, the TFT 21 is turned on by the selection signal of the scanning line 112, and further the TFT 25 is turned on. As a result, the capacitance 54 is generated by the current discharged from the TFT 23.
Is charged, the gate voltage of the TFT 23 rises. When the gate potential of the TFT 23 rises, the current discharged from the TFT decreases and stops, so that the threshold voltage is set in the capacitor 54. Second,
After turning off the TFT 27, the data voltage of the data line 114 is changed according to the brightness. As a result, the changed voltage is added to the threshold voltage via the capacitor 52. Thirdly, the TFT 27 is turned on again, and a current corresponding to the gate voltage obtained by adding the change voltage to the threshold voltage is changed to
Flow to the TFT 23. As a result, the driving TFT 2
It is compensated that the threshold voltage of 3 varies from pixel to pixel.

As described above, according to the second technique, it is possible to surely compensate for the characteristic variation of the TFT 23.
However, in the second technique, the variation in the capacitance of the capacitors 52 and 54 affects the uniformity of brightness.

Next, FIG. 28 is a circuit diagram showing a main structure of a display device to which the third technique is applied. In the third technique, the data line 114 includes the pixel 10 in the selected row.
The current Is according to the brightness of the current flows by a constant current source (not shown). In this configuration, when the TFT 31 is turned on by the selection signal via the scanning line 112a and the TFT 33 is turned on by the selection signal via the erasing line 112e, the current mirror circuit composed of the TFTs 35 and 37 causes the TFT 31 to pass through the TFT 35. The current Ie flowing through the EL element 130 and the TFTs 37, 3
The current Is flowing through the data line 114 via 1 becomes substantially equal. On the other hand, in the capacitor 58, charges corresponding to the common gate voltage of the TFTs 35 and 37 are accumulated, so that the TFT 3
Even if the transistors 1 and 37 are turned off, the current Ie continues to flow through the EL element 130 due to the gate voltage held by the capacitor 58.

Here, when the current Is flowing through the data line 114 at the time of selection is controlled so as to be the same in the panel, even if the threshold voltage characteristic of the driving TFT 35 varies from pixel to pixel, the EL element 130. Current I flowing through
e can be the same across each pixel. Therefore, the uniformity of brightness can be achieved. Note that the erase line 1 is supplied during a period in which a selection signal is not supplied to the scan line 112a.
When the selection signal is supplied to 12e, the charge accumulated in the capacitor 58 is cleared by turning on the TFT 33. Therefore, the driving TFT 35 is turned off and the current flowing through the EL element 130 is cut off, so that the pixel 10 is forcibly turned off (erased).

However, in the configuration shown in FIG. 28, it is a prerequisite for the current mirror circuit that the TFTs 35 and 37 formed close to each other have the same characteristics. Therefore, if this premise is broken, that is, the TFTs 35 and 3 formed close to each other in the same pixel 10.
If the characteristics of No. 7 are varied, the current Is does not match the current Ie actually flowing in the EL element 130. Therefore, even if the current Is is controlled to be the same, the brightness uniformity is Can't keep up.

On the other hand, in this embodiment, the shared line 1
Since the data voltage is manipulated so that the current actually flowing in the EL element 130 via 16 matches the target current value Id, the characteristic variations of the elements (capacitance and TFT) in different pixels are of course the same pixel. Even if there are variations in the characteristics of the elements within the display, it is possible to ensure the uniformity of brightness within the display surface.

However, in the present embodiment, although variations in element characteristics between different pixels and variations in element characteristics within the same pixel can be ignored, if the value of the resistor 1802 (see FIG. 6) varies from column to column. When all the pixels have the same gray scale, the current value flowing through the EL element 130 may vary from column to column. In order to prevent this situation from occurring, in the above-described embodiment, the resistance 1802 is variable and the resistance value Ra is set for each column.
It adopted a configuration that can be adjusted to. The variable type is a concept including setting of a resistance value by trimming of a laser or the like, setting of an electronic resistance, and the like. If the variation in the resistance value of the resistor 1802 is sufficiently small,
It may be a fixed resistor.

Further, in the present embodiment, the auxiliary scanning line 11
The reason why the configuration in which 2b is provided for each row and the reverse scanning signal is supplied to the auxiliary scanning line 112b is that the TF in the pixel 10 is
This is to unify the channel types of T122, 124, 126, and 128 to simplify the manufacturing process. In other words, in the present embodiment, the source S of the TFT 124 must be switched to either the common line 116 or the power supply line of the voltage Vcc, but if the channel types of the TFTs 126 and 128 are unified, both gates are respectively provided. Since it becomes necessary to supply an exclusive logic signal, the auxiliary scanning line 112
b is separately provided for each row to supply the reverse scanning signal. Here, for example, if the complexity of the manufacturing process can be ignored, the TFT 1 in FIG.
28 is an N channel type, and its gate is the scanning line 112a.
Connected to the auxiliary scanning line 112b and the inverter 16
2 (see FIG. 1) can be omitted.

<Application of First Embodiment> In the above-mentioned configuration, one set of m pixels corresponding to one column corresponds to one set of the data line 114 and the common line 116. Of these, the pixels located in the selected row. In this configuration, the data voltage applied to the data line 114 is manipulated so that the value of the current flowing through the shared line 116 in the EL element 130 matches the target value. However, in this configuration, since the data voltage operation circuit 180 is provided corresponding to each column, the configuration is complicated and the column pitch is narrowed, which hinders high definition display. Therefore, the following two examples will be described as application examples of the first embodiment for reducing the data voltage operation circuit 180 and the like.

<Application Example A of First Embodiment> First, an application in which two columns of pixels are made to correspond to one set of data line and common line, and the function of the data line and the function of the common line are alternately switched. Example A will be described.

FIG. 9 shows a display device 10 according to this application example A.
It is a block diagram which shows the structure of 0. In this figure, dual-purpose lines 118a and 118b have the functions of the data line 114 and the common line 116 in the configuration shown in FIG. 1, respectively. Specifically, dual-purpose wires 118a, 1
When one of 18b functions as the data line 114, the other functions as the common line 116, and conversely, when one functions as the common line 116, the other functions as the data line 114.

One set of the dual-purpose wires 118a and 118b is
Since the data voltage operation circuits 184 according to the application example A are provided corresponding to the pixels of two columns, one data voltage operation circuit 184 is provided for every two columns. Therefore, the number of the data voltage operation circuits 184 is half (n / n) as compared with the configuration shown in FIG.
2) (when n is an even number). Further, although not shown, the number of stages of the shift register 1710 in the data side output circuit 170, the register 1720, the latch circuit 1
The number of 730 and the number of D / A converters 1740 are also half (n / 2). In addition, the dual-purpose line 118
j for generally describing the column positions of a and 118b is
In the application example A, it is an integer that satisfies 1 ≦ j ≦ (n / 2).

On the other hand, the scanning line 112a and the auxiliary scanning line 11
The number of 2b is twice (2m) as compared with the configuration shown in FIG. Therefore, the scanning line drive circuit 16
Number of shift register stages forming 0 and inverter 1
The number of 62 is also doubled (2 m). In the application example A, i for generally explaining the row position of the scanning line 112a is an integer that satisfies 1 ≦ i ≦ (2m).

Here, the two pixels 10P and 10Q are adjacent to each other in the row (X) direction at the intersection of the two scanning lines 112a (complementary scanning lines 112b) and the pair of dual-purpose lines 118a and 118b. And place it. Therefore, the pixels are arranged in one row for the two scanning lines 112a and arranged in two columns for one set of the shared lines 118a and 118b, so that the resolution of the display device is The same vertical m dots × horizontal n dots as in the configuration shown in FIG.

<Pixel Configuration> Next, the pixels 10P, 10Q
Will be described in detail. FIG. 10 shows the continuous i-th row,
Pixel 1 corresponding to the intersection of the scanning line 112a in the (i + 1) th row and the dual-purpose lines 118a and 118b forming a pair in the jth column
It is a circuit diagram which shows the structure of 0P and 10Q.

As shown in this figure, pixels 10P, 1
Of 0Q, the former pixel 10P corresponds to the scanning line 112a of the i-th row in which selection is performed first. That is, in the pixel 10P, the gates of the TFTs 122 and 126 are
Each of them is connected to the scanning line 112a of the i-th row, and the TFT1
The gate of 28 is connected to the auxiliary scanning line 112b of the i-th row. In the pixel 10P, the TFT 122 is
The dual-purpose line 118b is inserted between the dual-purpose line 118b and the gate of the TFT 124, while the TFT 126 includes the dual-purpose line 118a and the TFT1.
It is inserted between 24 sources. Next, the latter pixel 10Q corresponds to the scanning line 112a of the (i + 1) th row selected next to the i-th row. That is, the pixel 10Q
, The gates of the TFTs 122 and 126 are connected to the scanning line 112a on the (i + 1) th row,
The gate of 28 is connected to the auxiliary scanning line 112b of the (i + 1) th row. Further, in the pixel 10Q, the TFT1
22 is inserted between the dual-purpose line 118a and the gate of the TFT 124, while the TFT 126 is inserted between the dual-purpose line 118b and the source of the TFT 124.

Here, for the sake of convenience, if i is an odd number (1, 3, 5, ...) To generally describe the row position of the scanning line 112a in the application example A, the pixel 10P has an odd i.
The pixel 10Q has an odd number i corresponding to the scanning line 112a in the row.
Will correspond to the even-numbered (i + 1) -th row scanning line 112a. Note that the pixel 10P corresponding to the i-th scanning line 112a and the pixel 10Q corresponding to the (i + 1) -th scanning line 112a are the same (i +
It will be located on the 1) / 2nd line. In addition, the pixels 10P, 10P corresponding to the dual-purpose line 118a (118b) in the j-th column
In terms of pixel array, Q is the (2j−1) th column,
It will be located in the (2j) th column.

<Operation of Data Side Output Circuit> This application example A
In the configuration of the data-side output circuit 170, the number of stages of the shift register 1710 and the register 1 are as described above.
720, the latch circuit 1730, and the D / A converter 174.
The configuration is the same as that shown in FIG. 4, except that the number of 0s is half (n / 2). However, the gradation data D
The order in which the pixs are supplied is different from the order shown in FIG. That is, as shown in FIG. 11, immediately before the scan signal Yi supplied to the i-th scan line 112a transitions to the L level, and the sampling signals Xs1, Xs2,
At the timing when each of Xs3, ..., Xs (n / 2) becomes the H level, the pixel 10P corresponding to the scanning line 112a in the i-th row, that is, the pixel array (i + 1).
/ 2 rows have odd columns of 1, 3, 5, ..., (n-1)
The gradation data Dpix of the pixels 10P in the column are sequentially supplied. Immediately before the scanning signal Y (i + 1) supplied to the scanning line 112a on the subsequent (i + 1) th row is changed to the L level, the sampling signals Xs1, Xs2, Xs3, ..., X are sampled.
At the timing when s (n / 2) becomes H level, the pixel 10Q corresponding to the scanning line 112a of the (i + 1) th row, that is, (i + 1) / 2 in the pixel array.
Of the rows, the pixels 10 in the even columns 2, 4, 6, ..., N columns
Q gradation data Dpix is sequentially supplied.

That is, in the application example A, in terms of the pixel arrangement, the gradation data Dpix of the pixels for one row is supplied for two horizontal scanning periods required for selecting the two scanning lines 112a. Specifically, in the first half horizontal scanning period, the grayscale data Dpix of the pixels 10P in the odd columns is supplied, and in the second horizontal scanning period of the second half, the grayscale data Dpix of the pixels 10Q in the even columns is supplied. Therefore, the grayscale voltages Vd1 and Vd output from the data side output circuit 170 according to the application example A are applied.
2, Vd3, ..., Vd (n / 2), the scanning signal Yi is L
In the first half horizontal scanning period of reaching the level, in terms of the pixel array, the gradation of the pixel 10P in the (i + 1) / 2 row 1, 3, 5, ..., (n-1) column is set to the scanning signal Y (i + 1). ) Becomes the L level, the same (i + 1)
/ 2 rows of 2, 4, 6, ...
These are expressed by the above equation (1).

<Data Voltage Manipulation Circuit> Next, the data voltage manipulation circuit 184 in the application example A will be described. FIG. 12 is a circuit diagram showing the configuration of the data voltage operation circuit 184. The configuration shown in this figure differs from the configuration shown in FIG. 6 in that changeover switches 1842 and 1844 are provided. This changeover switch 1842, 18
When the odd-numbered row selection signal P / Q is at the H level, each of the positions 44 takes the position shown by the solid line in the figure, while when the odd-numbered row selection signal P / Q is at the L level, it is indicated by the broken line in the figure. Take the position shown. Here, the odd-row selection signal P / Q is a signal that becomes H level when the odd-numbered scanning line 112a is selected and becomes L-level when the even-numbered scanning line 112a is selected. It should be noted that the odd-numbered row selection signal P / Q is the clock signal YCK
The frequency-divided signal may be output, and the output signal may be generated by a frequency divider circuit that resets the output signal to the H level when the scanning signal Y1 is at the L level.

<Operation of Application Example A> In the application example A having such a configuration, in the first half horizontal scanning period when the scanning signal Yi of the odd-numbered row becomes L level, the pixel array (i
Control is performed so that the current flowing through the EL element 130 matches the target value over the pixels 10P located in odd columns of the +1) / 2 rows. Specifically, for example, the j-th data voltage operation circuit 184 is referred to as (i + 1) / 2 in the pixel array.
The gradation voltage V of the pixel 10P located in the row and (2j-1) column
The voltage V obtained by subtracting the voltage drop indicated by the product of the resistance value Ra of the resistor 1802 and the current value flowing in the dual-purpose line 118a from dj.
The data voltage is manipulated so that det matches the voltage Vcc and applied to the dual-purpose line 118b.

Next, the scanning signal Y (i + 1) of the even-numbered row is L
In the 1st horizontal scanning period of the second half when the level becomes the level, the pixel 1 located in the even column of (i + 1) / 2
Control is performed so that the current flowing through the EL element 130 matches the target value over 0Q. Specifically, for example, the jth data voltage operation circuit 184 is referred to as (i +
1) / 2th row · (2j) th column located from the gradation voltage Vdj of the pixel 10Q to the resistance value Ra of the resistor 1802 and the shared line 118
The data voltage is manipulated and applied to the dual-purpose line 118b so that the voltage Vdet obtained by subtracting the voltage drop represented by the product of the current value flowing through b matches the voltage Vcc.

In such an application example A, if display of vertical m dots × horizontal n dots is performed as in the configuration shown in FIG.
Although the number of stages of shift registers in the scanning line drive circuit 160 and the number of inverters 162 are doubled, the number of stages of shift registers 1710 in the data side output circuit 170 and the number of registers 1720, latch circuits 1730, and D / A converters 1740 are increased. , Half each,
As a result, the number of the data voltage operating circuits 184 can be reduced to half, so that the configuration can be simplified as a whole circuit. In addition, a configuration (shift register 1710, register 172) that needs to be provided for one column of pixels
0, the latch circuit 1730, the D / A converter 1740, and the data voltage operation circuit 180) need only be provided corresponding to the pixels of two columns in the application example A, so the column pitch of the pixels can be narrowed accordingly. It is also possible to realize higher definition of the display.

<Application Example B of First Embodiment> Next, three columns of pixels are made to correspond to one set of data line and common line.
An application example B in which the function of the data line and the function of the shared line are not interchanged as in the application example A will be described. FIG. 13 is a block diagram showing the configuration of the display device 100 according to the application example B.

As shown in this figure, in the application example B, the data line 114 and the common line 116 are provided corresponding to the pixels of three columns. On the other hand, the number of scanning lines 112a and auxiliary scanning lines 112b is three times (3m) as compared with the configuration shown in FIG. Furthermore, three scan lines 1
12a (complementary scanning line 112b) and one data line 114
Corresponding to the intersection with (shared line 116), three pixels 10
R, 10G, and 10B are arranged adjacent to each other in the row (X) direction. Here, the pixels 10R, 10G, and 10B are set to emit red (R), green (G), and blue (B), respectively.
The L layer is selected, and these three pixels form one square dot. Therefore, in the application example B, the resolution of the display device is m vertical dots × n horizontal dots, which is the same as the configuration shown in FIG. 1. However, in the configuration shown in FIG. Example B
It should be noted that the display is in color and the number of pixels in the horizontal direction is tripled. Note that j for generally explaining the column position of the data line 114 (or the common line 116)
Is an integer satisfying 1 ≦ j ≦ n even in the application example A, as in the configuration shown in FIG. 1. Further, in the application example B, i for generally explaining the row position of the scanning line 112a is an integer that satisfies 1 ≦ i ≦ (3m).

<Pixel Configuration> Next, details of the pixels 10R, 10G, and 10B forming the same dot will be described. Here, in FIG. 14, the pixels 10R, 10G, 1 corresponding to the intersections of the continuous i-th row, (i + 1) -th row, (i + 2) -th row scanning line 112a and the j-th column data line 114.
It is a circuit diagram which shows the structure of 0B.

As shown in this figure, pixels 10R, 1
Of the pixels 0G and 10B, the pixel 10R corresponds to the i-th scanning line 112a that is selected first. That is, in the pixel 10R, the gates of the TFTs 122 and 126 are connected to the scanning line 112a on the i-th row, respectively.
The gate of No. 8 is connected to the auxiliary scanning line 112b of the i-th row. Subsequently, the pixel 10G corresponds to the scanning line 112a of the (i + 1) th row selected next to the i-th row. That is, in the pixel 10G, the gates of the TFTs 122 and 126 are connected to the scanning line 112a on the (i + 1) th row, and the gate of the TFT 128 is connected to the auxiliary scanning line 112b on the (i + 1) th row. And the pixel 10B
Corresponds to the scanning line 112a of the (i + 2) th row selected next to the (i + 1) th row. That is, in the pixel 10B, the gates of the TFTs 122 and 126 are respectively (i
The TFT 128 is connected to the scanning line 112a of the (+2) th row.
Is connected to the auxiliary scanning line 112b of the (i + 2) th row.

In each of the pixels 10R, 10G, and 10B, the TFT 122 is a TFT associated with its own pixel.
On the other hand, the TFT 126 is inserted between the gate of 124 and the data line 114 of the j-th column, and the TFT 126 is a TFT for its own pixel.
It is inserted between the source of 124 and the shared line 116 of the j-th column. Here, in application example B, if i is an integer such that the remainder becomes 1 when divided by 3, the scanning line 112a of the continuous i-th row, (i + 1) -th row, and (i + 2) -th row
And the pixel 1 corresponding to the intersection with the data line 114 of the jth column
One dot composed of 0R, 10G, and 10B is located in the (i + 2) / 3th row of the display array and the jth column.

In the application example B, in terms of the pixel array, the gradation data Dpix of dots for one row is supplied for three horizontal scanning periods required for selecting the three scanning lines 112a. Specifically, the gradation data Dpix of the pixel 10R in the first horizontal scanning period, the gradation data Dpix of the pixel 10G in the second horizontal scanning period, and the floor of the pixel 10B in the third horizontal scanning period. Key data D
Each pix is supplied. Therefore, the gradation voltage Vd output from the data-side output circuit 170 according to the application example B
1, Vd2, Vd3, ..., Vdn, the scanning signal Yi is L
In one horizontal scanning period in which the level becomes 1 level, the gradation of the pixel 10R in the dots located in each column of (i + 2) / 3 rows is changed to the same row in one horizontal scanning period in which the scanning signal Y (i + 1) becomes L level. Of the dots located in each column, the gray scale of the pixel 10G among the dots located in each column of the same row in one horizontal scanning period when the scanning signal Y (i + 2) becomes L level. , Respectively, as shown in the above formula (1).

After all, in the application example B, in the first horizontal scanning period when the scanning signal Yi becomes L level, the current flowing through the EL element 130 of the pixel 10R in (i + 2) / 3 rows in the pixel array. Is controlled to match the target value. Specifically, for example, the j-th data voltage operating circuit 1
Reference numeral 80 denotes the gradation voltage Vd corresponding to the pixel 10R among the dots located at (i + 3) / 2 rows and j columns in the pixel array.
The voltage Vdet obtained by subtracting the voltage drop of the resistor 1802 from j
, The data voltage is manipulated to match the voltage Vcc and applied to the data line 114 of the j-th column. Similarly, in the second one horizontal scanning period in which the scanning signal Y (i + 1) is at the L level, the current flowing through the EL element 130 of the pixel 10G in the pixel array (i + 2) / 3 rows becomes the target value. Matching control is performed, and then the scanning signal Y (i + 2) is changed to L
In the third horizontal scanning period which becomes the level, in the pixel arrangement, in the (i + 2) / 3 rows, control is performed so that the current flowing through the EL element 130 of the pixel 10B matches the target value.

According to the application example B, not only color display is possible, but the number of pixels is three times as large as that of the configuration shown in FIG. Number of stages of shift register 1710 in output circuit 170, register 1720, latch circuit 1730, D /
The numbers of the A converter 1740 and the data voltage operation circuit 180 are the same as those shown in FIG. In other words, in the application example B, if the pixels 10R, 10G, and 10B are treated as independent pixels of the same color without performing color display, the number of stages and the number of these are compared with the configuration shown in FIG. Even if it is considered that the number of shift registers and the number of inverters 162 in the scanning line driving circuit 160 is tripled in the scanning line driving circuit 160, the configuration can be simplified as a whole. Is possible.

In the application example B, pixel selection is
Although the order of the pixels 10R, 10G, and 10B is set, it goes without saying that the order may be other than this. Further, since the application example B is applied to the color display device, one data voltage drive circuit 180 is allocated to the pixels of three columns, but the application example B has the same configuration as the application example A. Since it is not necessary to alternately switch the function of the data line 114 and the function of the common line 116, one data voltage drive circuit 180 may be assigned to pixels of four columns or more, or two columns of pixels. One data voltage drive circuit 180 may be assigned.

<Second Embodiment> In the above-described first embodiment (see FIG. 1), the wirings that need to be routed to each pixel 10 may have the same channel type of the four TFTs formed in the pixel 10. If the condition is satisfied, the scanning line 112a,
A total of 6 of the auxiliary scanning line 112b, the data line 114, the common line 116, the power supply line of the voltage Vcc, and the ground line of the reference voltage Gnd.
It is a book. For this reason, in the first embodiment, the configuration becomes complicated by the amount of the wiring to be routed, and the aperture ratio tends to decrease. Therefore, the number of wires that need to be routed to each pixel 10 is reduced as compared with the first embodiment.
An embodiment will be described.

FIG. 15 shows a display device 1 according to the second embodiment.
It is a block diagram which shows the structure of 00. The main difference between the configuration shown in this figure and the configuration of the first embodiment (see FIG. 1) is that the auxiliary scanning line 112b and the inverter 162 are eliminated, and that a sustain signal ER, which will be described later, is applied to each pixel. 10 and the data voltage operating circuit 182. Further, due to the difference, the configuration of the pixel 10 and the configuration of the data voltage operation circuit 182 also differ.

FIG. 16 is a circuit diagram showing the configuration of the pixel 10 of this embodiment. In this figure, the shared line 117 is
It is provided for each pixel column and has a function as a current detection line that detects a current flowing through the EL element at the time of selection and a function as a power supply line for the EL element during the sustain period. Here, the function as the current detection line means a function equivalent to that of the shared line 116 in the above-described first embodiment. The sustain period is a period in which a current according to the gate voltage held in the capacitor 50 is passed through the EL element 130 to perform display, and in the present embodiment, the sustain signal ER is instructed by the L level. It TF
T127 and 129 are both inserted between the source S of the TFT 124 and the shared line 117 of the j-th column.
The gate of the FT 127 is connected to the i-th row scanning line 112a, and the gate of the TFT 129 is connected to the supply line of the sustain signal ER. In the present embodiment, the voltage Gn
The ground line of d and the supply line of the sustain signal ER are common to all the pixels 10, but are omitted in order to prevent complication of the drawing.

FIG. 17 is a timing chart showing the signal waveform of the sustain signal ER. As shown in this figure, the scanning signals Y1, Y2, Y3, ..., Ym are all H.
The sustain signal ER is at the L level during the period when it is at the level, that is, during the period when all the scanning lines 112a are unselected. It should be noted that such a sustain signal ER is N to which all the scanning signals Y1, Y2, Y3, ..., Ym are input.
It may be obtained by an AND circuit, or the scan signal Y1 in the next vertical scanning period from the rising of the scan signal Ym.
It is also possible to use a circuit that latches to the L level until the falling edge of. Further, here, the sustain signal ER is set to the L level during the period in which all the scanning lines 112a are unselected, but it may be set to the L level during only a part of the period. Further, in FIG. 17, the scanning signal Y
The sustain signal ER is set to the L level after all 1, Y2, Y3, ..., Ym are selected, but the present invention is not limited to this. For example, after selecting the scanning signal Y1, there is provided a period in which the scanning signals Y1, Y2, Y3, ..., Ym are all at the H level, and the sustain signal ER is set to the L level.
Next, the scanning signal Y2 is selected (the sustain signal ER is at the H level), and then the scanning signals Y1, Y2, Y3, ..., Y are again selected.
The sustain signal ER may be applied by providing a period in which all m are at the H level and setting the sustain signal ER at the L level. Further, after continuously selecting the scanning signals of a plurality of rows, the sustain signal ER is set at the L level. The period may be set.

FIG. 18 is a circuit diagram showing the configuration of the data voltage operation circuit 182 of this embodiment. The difference between the configuration shown in this figure and the configuration of the first embodiment (see FIG. 6) is that
A changeover switch 1822 is provided. When the sustain signal ER is at the H level, the changeover switch 1822 takes the position shown by the solid line in the figure,
If the sustain signal ER is at L level while the common line 117 is connected to one end of the resistor 1802, the common line 117 is connected to the power supply line of the voltage Vcc at the position shown by the broken line in the figure. In the second embodiment, TF
The source S of T124 is connected to the shared line 117 by the TFT 127 when the scanning signal Yi is at the L level, while the TFT 1 is connected when the sustain signal ER is at the L level.
29 and the changeover switch 1822, the voltage Vcc
Will be connected via the common line 117. That is, in the present embodiment, the TFTs 127, 129
And the changeover switch 1822, the source S of the TFT124, the common line 1 if the scanning signal Yi is L level.
On the other hand, when the sustain signal ER is at L level, it functions as a switch connected to the power supply line of the voltage Vcc.

Next, the display operation of the second embodiment will be described. FIG. 19 is a diagram for explaining the operation of the pixel 10 in the i-th row and the j-th column when the scanning line 112a in the i-th row is selected. First, the scanning line 112a of the i-th row
When is selected, the scanning signal Yi becomes L level.
The TFTs 122 and 127 are turned on. Moreover, since the sustain signal ER is at the H level, the TFT 129 is turned off,
With the changeover switch 1822, the common line 117 has the resistance 18
02 is connected to one end. Therefore, a current corresponding to the data voltage Xaj immediately after the start of selection is applied to the EL element 130 of the i-th row and the j-th column of the resistance 1802 → the changeover switch 1822 → the shared line 117 → TFT 127 → TFT 124 → (EL element 1
30) → It flows through the route of the ground line.

The second embodiment is different from the first embodiment only in the current path flowing through the EL element 130,
Since the others are the same, the same control operation as in the first embodiment is executed. That is, the scanning signal Y
In the period in which i is at L level, the data voltage Xaj is manipulated so that the current value flowing through the EL element 130 matches the target current value Id by the time immediately before the end of selection. After that, even if the scanning signal Yi transits to the H level, the data voltage Xaj is held by the capacitor 50.
However, in the second embodiment, even if the scanning signal Yi transits to the H level, no current flows through the EL element 130 unless the sustain signal ER reaches the L level. Here, although attention is paid to the i-th row (particularly to the j-th column), in reality, the operation for holding the data voltage in the capacitor 50 is 1,
Each time the scanning lines 112a of the second, third, ..., Mth rows are selected one by one, the scanning lines 112a are simultaneously executed for each column.

When the sustain signal ER becomes L level while the data voltage is held in the capacitor 50 of each pixel, the TFT 129 is turned on. Also, the changeover switch 1
The common line 117 is connected to the power supply line of the voltage Vcc by 822. For this reason, as shown in FIG. 20, the EL elements 130 of all the pixels have capacitances of 5
The current corresponding to the data voltage Xaj held by 0 is the power supply line of the voltage Vcc → the changeover switch 1822 → the shared line 117 → TFT129 → TFT124 → (EL element 1
30) → It will flow through the route of the ground line. Therefore, all the EL elements 130 have the sustain signal E
Until R returns to H level, the pixel capacity 5 related to self
The current continues to be emitted at a current corresponding to the data voltage held by 0 at the brightness, that is, at the brightness of the gradation indicated by the gradation data Dpix.

As described above, in the second embodiment, as in the first embodiment, the data voltage is manipulated so that the current actually flowing in the EL element 130 matches the target current value Id. It is possible to secure the uniformity of the brightness inside. Furthermore, in the second embodiment, the EL element 1
The voltage Vcc, which is one of the 30 power supply voltages, is supplied through the shared line 117 shared for each column and the changeover switch 1822 provided in the shared line 117.
It is not necessary to route the power supply line of the voltage Vcc to all pixels. Therefore, even if it is a condition that the channel types of the four TFTs formed in the pixel 10 are unified, the wirings that need to be routed to each pixel 10 are the scanning line 112a and the data line 11.
4, the common line 117, the supply line of the sustain signal ER, and the ground line of the voltage Gnd are required in total of five lines, and thus the configuration can be simplified and the aperture ratio can be improved as compared with the first embodiment. Is possible.

<Application of Second Embodiment> In the second embodiment (see FIG. 15) in which the common line 117 has both a function as a current detection line and a function as a power supply line,
Similar to the application example B (see FIG. 13) of the embodiment, it is possible to apply the technique of performing color display by associating the pixels of three columns with one set of the data line 114 and the common line 117. Then, an application example in which three columns of pixels are made to correspond to one set of the data line 114 and the common line 117 in the configuration shown in FIG. 15 will be described.

FIG. 21 is a block diagram showing the configuration of a display device according to an application example of the second embodiment. As shown in this figure, in the application example of the second embodiment, the data line 114
The common line 117 is provided corresponding to the pixels of three columns. On the other hand, the number of scanning lines 112a is three times (3 m) as compared with FIG. Furthermore, three scanning lines 11
Corresponding to the intersection of 2a and one data line 114 (shared line 116), three pixels 10R, 10G, and 10B are arranged adjacent to each other in the row (X) direction. The pixel 10
As described above, R, 10G, and 10B emit light in red (R), green (G), and blue (B), respectively.

Next, the pixels 10 forming the same dot
Details of R, 10G, and 10B will be described. here,
FIG. 22 shows the continuous i-th row, (i + 1) -th row, (i +
2) The scanning line 112a in the row and the data line 114 in the jth column
It is a circuit diagram which shows the structure of the pixels 10R, 10G, and 10B corresponding to the intersection with.

As shown in this figure, the pixels 10R, 1
Of the pixels 0G and 10B, the pixel 10R corresponds to the i-th scanning line 112a that is selected first. That is, in the pixel 10R, the gates of the TFTs 122 and 127 are connected to the i-th row scanning line 112a, respectively. Subsequently, the pixel 10G is selected next to the i-th row (i + 1).
It corresponds to the scanning line 112a in the row. That is, the pixel 10
In G, the gates of the TFTs 122 and 127 are connected to the scanning line 112a of the (i + 1) th row, respectively.
The pixel 10B corresponds to the (i + 2) th scanning line 112a selected next to the (i + 1) th row. That is, in the pixel 10B, the gates of the TFTs 122 and 127 are connected to the (i + 2) th row scanning line 112a.

In each of the pixels 10R, 10G, and 10B, the TFT 122 is a TFT associated with its own pixel.
The TFTs 127 and 129 are inserted between the gate of the column 124 and the data line 114 of the j-th column, and the TFTs 127 and 129 are inserted between the source of the TFT 124 relating to its own pixel and the common line 116 of the j-th column. . In addition, the pixels 10R, 10G, 10B
At the gate of the TFT 129, the sustain signal E
Commonly connected to the R supply line. Here, in the application example, if i is an integer such that the remainder becomes 1 when divided by 3, the scanning lines 112a of the continuous i-th row, the (i + 1) -th row, and the (i + 2) -th row, and j One dot formed by the pixels 10R, 10G, and 10B corresponding to the intersection with the data line 114 in the column is located in the (i + 2) / 3th row of the display array and is located in the jth column.

In the application example of the second embodiment, the gradation data Dpix of dots for one row in the pixel array is the same as that of the application example A of the first embodiment.
Is supplied over the three horizontal scanning periods required for selection.
Therefore, in the application example B, in the first horizontal scanning period in which the scanning signal Yi is at the L level, the EL element 130 of the pixel 10R in the (i + 2) / 3 rows in the pixel array.
The control is performed so that the current flowing through the target coincides with the target value. Next, the second 1 in which the scanning signal Y (i + 1) becomes L level
In the horizontal scanning period, in the pixel array (i + 2) / 3 rows, the control is performed so that the current flowing in the EL element 130 of the pixel 10G matches the target value, and then the scanning signal Y
In the third one horizontal scanning period in which (i + 2) is at the L level, pixel 1 in (i + 2) / 3 rows in the pixel arrangement is used.
Control is performed so that the current flowing through the 0B EL element 130 matches the target value. Then, when the sustain signal ER transits to the L level, the voltage V
cc is applied, and the current corresponding to the voltage held in the capacitor 50 associated with the pixel of interest continues to flow through the EL element 130. Here, as described above, the voltage held in the capacitor 50 is the data voltage that causes the value of the current flowing through the EL element 130 to match the target value.
G and 10B continue to emit light at the brightness corresponding to the brightness designated by the gradation data Dpix.

According to the application example of the second embodiment, as in the application example B of the first embodiment, not only color display is possible, but also the configuration can be simplified. Further, along with this, it is easy to increase the definition of the display.

<Others> The present invention is not limited to the above-described first and second embodiments, and various modifications are possible. For example, in the above description, except for the application example B of the first embodiment and the application example of the second embodiment, in principle, gradation display is performed for pixels of a single color, but in other configurations as well, R for each of the three pixels
Color display may be performed by selecting the EL layer so as to develop colors of (red), G (green), and B (blue), and configuring one dot by these three pixels. Also, EL
Instead of the element 130, another light emitting element such as an LED may be used.

The TFT 124 may be of N-channel type. However, when the TFT 124 is an N-channel type, the data voltage operation circuit 180 (182, 18)
In 4), it is necessary to reverse the operation direction of the data voltage with respect to the comparison result of the voltage Vdet at one end of the resistor 1802 and the voltage Vcc. That is, when the TFT 124 is an N-channel type, if the current flowing through the EL element 130 is smaller than Id and the voltage Vdet is higher than the voltage Vcc, it is necessary to increase the data voltage. The current flowing through the element 130 is larger than Id,
If the voltage Vdet is lower than the voltage Vcc, it is necessary to lower the data voltage. Further, instead of connecting the anode of the EL element to the drain D of the TFT 124, the TFT 1
The cathode of the EL element may be connected to the source of 24.

The TFTs 122, 126 (127),
The 128 (129) may also be an N-channel type or a hybrid with a P-channel type. For each of them, it is desirable that the transmission gate is a combination of the P-channel type and the N-channel type in a complementary type, since the voltage drop can be almost completely ignored.

Further, in the above-described embodiment, the data voltage operating circuit 180 has the configuration shown in FIG. 6, but the configuration is not limited to this. For example, the TFT 1810 may be replaced with a bipolar transistor, or a separate resistor may be added in series and / or in parallel to the voltage dividing circuit. Regarding the modification of the data voltage operation circuit 180, the data voltage scanning circuit 182 (see FIG.
), 184 (see FIG. 12). Further, in the above-described embodiment, the resistor 1802 is used to detect the current flowing through the EL element 130, but the present invention is not limited to this, and a Hall element may be used to detect the current.

In addition, in the above-described embodiment, the voltage V which is obtained by subtracting the voltage drop of the resistor 1802 from the gradation voltage Vdj.
Although it is configured to indirectly determine whether the current flowing through the EL element 130 matches the target current value Id by comparing det with the voltage Vcc.
The D / A converter 1740 is replaced with a constant power supply circuit that supplies a gradation current according to the gradation of the pixel, and the common line 116 is used.
The configuration may be such that it is directly determined whether the current flowing through the EL element 130 matches the gradation current through (117). Regarding the voltages Va and Vb, Va> V
Although it is not particularly mentioned except that it is b, this is because it should be set in consideration of the characteristics of the TFT 124 in the pixel 10.

<Electronic Equipment> Next, examples in which the electro-optical device according to the above-described embodiment is used in electronic equipment will be described.

<Part 1: Personal Computer> First, an example in which the above-described display device 100 is applied to the display unit of a mobile personal computer will be described. FIG. 23 is a perspective view showing the configuration of this personal computer. In the figure, a computer 1100
Includes a main body portion 1104 having a keyboard 1102 and a display device 100 used as a display portion.
Note that when a liquid crystal device is used as the display unit, it is necessary to provide a backlight on the back surface.
Since 0 is a self-luminous type, such an auxiliary light source can be eliminated, and the display unit can be thinned.

<Part 2: Mobile Phone> Further, an example in which the above-described display device 100 is applied to the display portion of a mobile phone will be described. FIG. 24 is a perspective view showing the configuration of this mobile phone. In the figure, a mobile phone 1200 includes a plurality of operation buttons 1202, an earpiece 1204, and a mouthpiece 12.
In addition to 06, the display device 100 described above is provided.

<Part 3: Digital Still Camera> Next, a digital still camera using the above-described display device 100 as a finder will be described. FIG. 25 is a perspective view showing the back surface of this digital still camera.
A normal silver halide camera exposes a film by an optical image of a subject, whereas a digital still camera 1300
Is a CCD (Charge Coupled Device) that captures the optical image of the subject.
An image pickup device such as the above photoelectrically converts the image pickup signal to generate and store the image pickup signal. Here, the digital still camera 1
The display device 100 described above is provided on the back surface of the case 1302 in the 300. Since the display device 100 performs display based on the image pickup signal, it functions as a finder that displays a subject. In addition, case 13
A light receiving unit 1304 including an optical lens and a CCD is provided on the front side (back side in FIG. 25) of 02.

When the photographer confirms the subject image displayed on the display device 100 and presses the shutter button 1306, the image pickup signal of the CCD at that time is displayed on the circuit board 1.
It is transferred and stored in the memory 308. Further, in this digital still camera 1300, a video signal output terminal 1 for external display is provided on the side surface of the case 1302.
312 and an input / output terminal 1314 for data communication are provided.

As the electronic equipment, in addition to the personal computer shown in FIG. 23, the mobile phone shown in FIG. 24, the digital still camera shown in FIG. 25, a television, a viewfinder type, a monitor direct-viewing type video tape recorder, and a car. Navigation device, pager, electronic organizer, calculator, word processor, workstation, videophone, POS
Examples thereof include a terminal and a device equipped with a touch panel.
It goes without saying that the above-mentioned display device can be applied as the display unit of these various electronic devices.

[0108]

As described above, in the present invention, when the first switch is closed, the data voltage applied to the data line is held by the capacitor, and the transistor shares the current corresponding to the data voltage. To the light-emitting element through the line, and the data voltage is further controlled by the data voltage operation circuit to eliminate the difference between the grayscale current corresponding to the grayscale of the pixel and the current flowing through the light-emitting element through the shared line. Since it is configured to be operated, the current flowing through the light emitting element accurately matches the gradation current. Therefore, according to the present invention, even if the characteristics of the transistors are varied, the currents flowing through the light emitting elements are aligned with each other at the same brightness, so that the display quality is deteriorated due to the different brightness of the pixels that should be the same. Can be prevented. Further, in the present invention, since the data line and the common line can be shared over a plurality of pixels provided corresponding to the intersections of the scanning lines and the data lines, the configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a display device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a pixel in the display device.

FIG. 3 is a timing chart for explaining the operation of the scanning line drive circuit.

FIG. 4 is a block diagram showing a configuration of a data drive circuit in the display device.

FIG. 5 is a timing chart for explaining the operation of the data line driving circuit.

FIG. 6 is a circuit diagram showing a configuration of a data voltage operating circuit in the display device.

FIG. 7 is a diagram for explaining an operation of operating a data voltage in the display device.

FIG. 8 is a diagram for explaining a display operation in the display device.

FIG. 9 is a block diagram showing a configuration of a display device according to an application example A of the first embodiment.

FIG. 10 is a circuit diagram showing a configuration of a pixel in the display device.

FIG. 11 is a timing chart for explaining the operation of the data line driving circuit in the display device.

FIG. 12 is a circuit diagram showing a configuration of a data voltage operating circuit in the display device.

FIG. 13 is a block diagram showing a configuration of a display device according to an application example B of the first embodiment.

FIG. 14 is a circuit diagram showing a configuration of a pixel in the display device.

FIG. 15 is a block diagram showing a configuration of a display device according to a second embodiment of the present invention.

FIG. 16 is a circuit diagram showing a configuration of a pixel in the display device.

FIG. 17 is a timing chart of a sustain signal ER in the display device.

FIG. 18 is a circuit diagram showing a configuration of a data voltage operating circuit in the display device.

FIG. 19 is a diagram for explaining the operation of manipulating the data voltage in the display device.

FIG. 20 is a diagram for explaining a display operation in the display device.

FIG. 21 is a block diagram showing a configuration of a display device according to an application example of the second embodiment.

FIG. 22 is a circuit diagram showing a configuration of a pixel in the display device.

FIG. 23 is a perspective view showing a configuration of a personal computer as an example of an electronic apparatus to which the display device according to the embodiment is applied.

FIG. 24 is a perspective view showing a configuration of a mobile phone which is an example of an electronic apparatus to which the display device is applied.

FIG. 25 is a perspective view showing a configuration of a digital still camera which is an example of an electronic apparatus to which the display device is applied.

FIG. 26 is a diagram showing a main configuration of a conventional display device.

FIG. 27 is a diagram showing a main configuration of a conventional display device.

FIG. 28 is a diagram showing a main configuration of a conventional display device.

[Explanation of symbols]

10 ... Pixels 50 ... Capacity 100 ... Display device 112a ... Scan line 112b ... Complementary scanning line 114 ... Data line 116, 117 ... Shared line 118a, 118b ... Combined line 122 ... TFT 124 ... TFT (transistor) 130 ... EL element (light emitting element) 126, 127, 128, 129 ... TFT 160 ... Scan line drive circuit 170 ... Output circuit on data side 180, 182, 184 ... Data voltage operating circuit 1802 ... Resistance 1804 ... Comparator 1810 ... transistor 1812 ... resistance 1842, 1844 ... Changeover switch

Front page continuation (51) Int.Cl. ⁷ identification code FI theme code (reference) G09G 3/20 623 G09G 3/20 623R 624 624B 641 641D 642 642A H05B 33/14 H05B 33/14 A F term (reference) 3K007 AB04 AB05 AB17 BA06 CB01 DA00 DB03 EB00 FA01 GA04 5C080 AA06 BB05 DD03 EE29 FF11 JJ02 JJ03 JJ04 5C094 AA03 AA53 AA55 BA03 BA23 BA27 CA19 EA04 EA07

Claims (4)

[Claims] 1. A first switch, which corresponds to a different scanning line at each intersection of the scanning line and the data line, and which is closed or opened according to a scanning signal supplied to the corresponding scanning line. A capacitor that holds a data voltage applied to the data line when the first switch is closed; a transistor that uses the data voltage held by the capacitor as a gate voltage; and a source or a drain of the transistor. The light-emitting element connected to one side and the other of the source and the drain of the transistor are connected to the common line when the first switch is closed and the power supply voltage is supplied during the period when the first switch is open and closed. A pixel including a second switch connected to an electric wire; and a pair of the data line and a current flowing through the light emitting element when the first switch is closed. And a data voltage operating circuit for operating the data voltage applied to the data line in a direction to eliminate the difference between the grayscale current corresponding to the grayscale of the pixel and the current flowing in the shared line. A display device comprising: 2. The number of pixels provided corresponding to the intersection of the scanning line and the data line is 2. When the scanning line corresponding to one of the two pixels is selected, the other pixel is selected. 2. The display device according to claim 1, further comprising a changeover switch for changing over the data line for the one pixel as a shared line for the one pixel and for changing the shared line for the other pixel as a data line for the one pixel. . 3. A first switch, which corresponds to a different scanning line at each intersection of the scanning line and the data line, and which is closed or opened according to a scanning signal supplied to the corresponding scanning line. A capacitor holding a data voltage applied to the data line when the first switch is closed, a transistor having a gate voltage of the data voltage held by the capacitor, and a source or a drain of the transistor. A pixel provided with a light emitting element connected to one side, a shared line for flowing a current to the light emitting element when the first switch is closed, and the other of the source or the drain of the transistor, When the first switch is closed and connected, it is connected to the shared line, while the first switch is connected and connected to the shared line, and the shared line is connected to the front side. A direction to eliminate the difference between the grayscale current corresponding to the grayscale of the pixel and the current flowing in the shared line when the second switch connected to the power supply line of the power supply voltage and the first switch are closed. And a data voltage operating circuit for operating the data voltage applied to the data line. 4. An electronic device comprising the display device according to claim 1.