JP2003069653A - Data communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously realize supply of power or a clock and two-way communication of serial data by only two contacts in a contact type data carrier system. SOLUTION: In a controller 1, an operation voltage Vout is made higher and amplitudes of clock pulse signals CK and ICK are made wider when a transmission signal TS1 is 'L', but the amplitudes are made shorter when the transmission signal TS1 is 'H'. In a data carrier device 2, signals CK and ICK are subjected to full wave rectification into the operation voltage by a rectifying circuit 21, and a reception signal RS2 is extracted by a second signal detection circuit 22. In the device 2, the impedance between contacts A and B is made lower and amplitudes of signals CK and ICK are made shorter when a transmission signal TS2 is 'L', but the amplitudes are made wider when the transmission signal TS2 is 'H'. In the controller 1, the change of the amplitude of the signal ICK is extracted as a reception signal RS1 by a first signal detection circuit 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique relating to a two-wire data communication device for performing data communication in a contact data carrier system.

[0002]

2. Description of the Related Art FIG. 13 is a diagram showing a schematic configuration of a conventional data communication system. As shown in FIG. 13, in the conventional configuration, the data carrier device 52 and the control device 5 are
When the data communication with 1 is performed, four contacts for the power supply, ground, clock, and data signal are provided and connected.

[0003]

However, in the conventional case, four contacts were required to perform data communication, which was not suitable for downsizing the system.

In view of the above problems, an object of the present invention is to enable bidirectional data communication with two contacts in a system in which a control device and a data carrier device perform data communication.

[0005]

In order to solve the above-mentioned problems, a solution means provided by the invention of claim 1 is that a control device and a data carrier device perform data communication via first and second contacts. As a system for performing the above, the control device converts a voltage of the power supply, a power supply that supplies power, a clock generation circuit that generates a clock pulse signal and supplies the clock pulse signal to at least one of the first and second contacts. A voltage level generation circuit to be supplied to the clock generation circuit as an operating voltage; a first transmission circuit that changes the operating voltage generated by the voltage level generation circuit according to a first transmission signal; A first signal detection circuit for detecting a change in voltage amplitude of any one of the second contacts as a first reception signal, wherein the data carrier device comprises: A rectifier circuit that rectifies the voltage between the first and second contacts and supplies the rectified voltage as an operating voltage of the data carrier device, and a change that detects the change in the operating voltage rectified by the rectifying circuit as a second received signal. A second signal detection circuit, a clock detection circuit that generates an operation clock from a clock pulse signal supplied to at least one of the first and second contacts, and an impedance between the first and second contacts that is second. And a second transmission circuit that changes the transmission signal according to the second transmission circuit.

According to the first aspect of the present invention, a clock pulse signal is supplied to at least one of the first and second contacts from the clock generation circuit of the control device.
In the data carrier device, the voltage between the first and second contacts is rectified by the rectifier circuit to become the operating voltage. Further, an operation clock is generated by the clock detection circuit from the supplied clock pulse signal. Further, the operating voltage of the clock generation circuit changes in response to the first transmission signal, which changes the amplitude of the clock pulse signal supplied from the control device. The data carrier device detects a change in the rectified operating voltage due to a change in the amplitude of the clock pulse signal as the second received signal. On the other hand, in the data carrier device, the first and second
The impedance between the contacts is changed according to the second transmission signal. The control device detects, as the first transmission signal, a change in the voltage amplitude of either the first contact or the second contact due to the change in the impedance. That is, the power supply and the clock supply from the control device to the data carrier device and the bidirectional communication of serial data between the both devices can be performed only through the first and second contacts.

In the invention of claim 2, the voltage level generating circuit in the data communication system of claim 1 has a plurality of resistors arranged in series between the power source and the ground, and the plurality of resistors are provided. It is assumed that the operating voltage is supplied from one end of one of the resistors, the first transmission circuit is connected in parallel with at least one of the plurality of resistors, and the conduction / non-conduction circuit is connected. It is assumed to have a switching element whose conduction is switched according to the transmission signal.

According to the invention of claim 3, said claim 1
A voltage level generation circuit in the data communication system according to, having a plurality of resistors arranged in series between the power supply and ground, from one end of the plurality of resistors, the operating voltage And the first
The transmission circuit of is connected to at least one of the plurality of resistors in series, and has a switching element that switches between conduction and non-conduction in accordance with the transmission signal.

Further, the solution means taken by the invention of claim 4 is a system in which the control device and the data carrier device perform data communication via the first and second contacts, and the control device supplies electric power. Power supply,
A voltage level generation circuit that converts the voltage of the power supply and supplies it as a signal voltage between the first and second contacts, and the signal voltage generated by the voltage level generation circuit is changed according to the first transmission signal. A first transmission circuit for causing the first transmission circuit
And a first signal detection circuit that detects a change in voltage between the second contacts as a first received signal,
The data carrier device stabilizes the voltage between the first and second contacts and supplies it as an operating voltage of the data carrier device, and the first and second regulators.
A second signal detection circuit that detects a change in voltage between the contacts of the second transmission signal and a second transmission that changes the impedance between the first and second contacts according to a second transmission signal. And a circuit.

According to the invention of claim 4, a signal voltage is supplied from the voltage level generating circuit of the control device between the first and second contacts, and in the data carrier device, the signal voltage is supplied between the first and second contacts. The voltage is stabilized by the regulator and becomes the operating voltage. The signal voltage supplied from the control device changes according to the first transmission signal. The data carrier device detects a change in signal voltage as the second received signal. On the other hand, in the data carrier device, the impedance between the first and second contacts is changed according to the second transmission signal. The control device detects the voltage between the first and second contacts, which is caused by the change in impedance, as the first transmission signal. That is, the power supply from the control device to the data carrier device and the bidirectional communication of serial data between both devices can be performed only through the first and second contacts.

According to the invention of claim 5, the voltage level generating circuit in the data communication system of claim 4 has a plurality of resistors arranged in series between the power source and the ground, and the plurality of resistors are provided. The signal voltage is supplied from one end of any one of the resistors, the first transmission circuit is connected in parallel with at least one of the plurality of resistors, and the first transmission circuit is conductive or non-conductive. It is assumed to have a switching element whose conduction is switched according to the transmission signal.

The means for solving the problems of the sixth aspect of the invention is a system in which the control device and the data carrier device perform data communication via the first and second contacts, and the control device supplies power. Power supply,
A clock generation circuit that generates a clock pulse signal and supplies it to at least one of the first and second contacts; a voltage level generation circuit that converts the voltage of the power supply and supplies it as an operating voltage to the clock generation circuit; A pulse width conversion circuit that changes the pulse width of the clock pulse signal generated by the clock generation circuit according to the first transmission signal;
The change in the voltage amplitude of either the first or the second is
And a first signal detection circuit for detecting the received signal as a received signal, the data carrier device rectifies a voltage between the first and second contacts and supplies the rectified voltage as an operating voltage of the data carrier device. And a second signal detection circuit for detecting a change in pulse width at any of the first and second contacts as a second received signal, and an impedance between the first and second contacts. And a second transmission circuit that changes according to a second transmission signal.

According to the invention of claim 6, a clock pulse signal is supplied to at least one of the first and second contacts from the clock generation circuit of the control device.
In the data carrier device, the voltage between the first and second contacts is rectified by the rectifier circuit to become the operating voltage. Further, the pulse width of the clock pulse signal supplied from the control device changes according to the first transmission signal. The data carrier device detects a change in the pulse width of the clock pulse signal as the second received signal. On the other hand, in the data carrier device, the impedance between the first and second contacts is changed according to the second transmission signal. The control device detects, as the first transmission signal, a change in the voltage amplitude of either the first contact or the second contact due to the change in the impedance. That is, the power supply from the control device to the data carrier device and the bidirectional communication of serial data between the two devices are performed by the first and second devices.
It can be done only through the contact of.

Further, in the invention of claim 7, the first signal detection circuit in the data communication system according to claims 1 and 6 is arranged in place of the change of the voltage amplitude of one of the first and second contacts. It is assumed that the voltage level generation circuit detects a change in voltage amplitude of a terminal outputting the operating voltage as the first reception signal.

Further, the solution means taken by the invention of claim 8 is a system in which the control device and the data carrier device perform data communication via the first and second contacts, and the control device supplies electric power. Power supply,
One of a clock pulse circuit that receives an operating voltage from the power supply, generates a clock pulse signal, and supplies the clock pulse signal to at least one of the first and second contacts, and a clock pulse signal generated by the clock generation circuit. A first transmission circuit that changes a voltage level according to a first transmission signal, and a first signal detection that detects a change in a voltage amplitude of one of the first and second contacts as a first reception signal. And a circuit, wherein the data carrier device comprises:
A rectifier circuit that rectifies the voltage between the first and second contacts and supplies the rectified voltage as an operating voltage of the data carrier device;
The second change in the operating voltage rectified by the rectifier circuit is
Second signal detection circuit for detecting the received signal as a received signal, a clock detection circuit for generating an operation clock from a clock pulse signal supplied to at least one of the first and second contacts, and the first and second And a second transmission circuit that changes the impedance between the contacts according to the second transmission signal.

According to the present invention, a clock pulse signal is supplied to at least one of the first and second contacts from the clock generation circuit of the control device.
In the data carrier device, the voltage between the first and second contacts is rectified by the rectifier circuit to become the operating voltage. Further, an operation clock is generated by the clock detection circuit from the supplied clock pulse signal. Further, one of the voltage levels of the clock pulse signal supplied from the control device changes according to the first transmission signal. In the data carrier device, a change in the rectified operating voltage caused by a change in the voltage level of one of the clock pulse signals is detected as the second received signal.
On the other hand, in the data carrier device, the impedance between the first and second contacts is changed according to the second transmission signal. The control device detects, as the first transmission signal, a change in the voltage amplitude of either the first contact or the second contact due to the change in the impedance. That is, the power supply and the clock supply from the control device to the data carrier device and the bidirectional communication of serial data between the both devices can be performed only through the first and second contacts.

In the invention of claim 9, the control device in the data communication system of claim 1, 6 or 8 supplies the clock pulse signal generated by the clock generation circuit to the first contact. At the same time, the second contact is supplied with a clock pulse signal generated by the clock generation circuit and having a phase opposite to that of the clock pulse signal, and the rectifier circuit is provided between the first and second contacts. Full-wave rectification shall be performed on the voltage.

Further, in the invention of claim 10, the control device in the data communication system of claim 1, 6 or 8 supplies the clock pulse signal generated by the clock generation circuit to the first contact. At the same time, a ground potential is supplied to the second contact, and the rectifier circuit performs half-wave rectification on the voltage between the first and second contacts.

In the invention of claim 11, the control device in the data communication system of claim 1 is
It is assumed that the voltage level generation circuit and the clock generation circuit are connected in series.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram of a data communication system according to a first embodiment of the present invention. In the data communication system of FIG. 1, the control device 1 and the data carrier device 2 perform data communication via two contacts A and B.

In FIG. 1, the control device 1 generates a power supply 11 for supplying electric power, a clock pulse signal CK and a clock pulse signal ICK having a phase opposite to that of the clock pulse signal CK.
And a voltage level generation circuit 13 for converting the voltage of the power supply 11 and supplying it to the clock generation circuit 12 as an operating voltage Vout. A first transmission circuit 14 that changes the generated operating voltage Vout according to the first transmission signal TS1, and a first signal detection that detects a change in voltage amplitude of the second contact B as a first reception signal RS1. And a circuit 15. The amplitudes of the clock pulse signal CK and the anti-phase clock pulse signal ICK supplied from the clock generation circuit 12 are determined by the voltage level generation circuit 13
Is determined according to the operating voltage Vout generated by That is, the amplitudes of the signals CK and ICK are changed by the first transmission circuit 14 according to the first transmission signal TS1.

On the other hand, the data carrier device 2 has a rectifying circuit 21 for rectifying the voltage between the first and second contacts A and B.
A second signal detection circuit 22 for detecting a change in the amplitude of the clock pulse signals CK and ICK supplied to the first and second contacts A and B as a second reception signal RS2;
And a second transmission circuit 23 that changes the impedance between the second contacts A and B according to the second transmission signal TS2.
And a clock detection circuit 24 for generating the operation clock CK2 of the data carrier device 2 from the signal of the first contact A. The output of the rectifier circuit 21 is used as the operating voltage of the data carrier device 2. Further, the voltage change between the first and second contacts A and B caused by the change in impedance by the second transmission circuit 23 is given to the control device 1 as a signal.

In the control device 1, the voltage level generation circuit 13 has a plurality of resistors R1, R2 and R3 for dividing the voltage of the power supply 11, and outputs the voltage between the resistors R2 and R3 as the operating voltage Vout. To do. Further, the first transmission circuit 14 has a MOS transistor 14a connected in parallel with the resistor R2 of the voltage level generation circuit 13. MOS transistor 14a as a switching element
The first transmission signal TS1 is applied to the gate of the
The conduction / non-conduction of the transistor 14a is switched according to the voltage level of the first transmission signal TS1. When the MOS transistor 14a is conductive, both ends of the resistor R2 are short-circuited, so that the operating voltage Vout becomes relatively high.
On the other hand, when the MOS transistor 14a is off, the operating voltage Vout is relatively low.

Further, the clock generation circuit 12 is composed of two stages of inverters 12a and 12b connected in series, and the first inverter 12a outputs a clock pulse signal CK in phase with the applied operation clock CK1. Then, the operation clock CK is output from the second inverter 12b.
A clock pulse signal ICK having a phase opposite to that of 1 is output. Operating voltage Vout output from the voltage level generation circuit 13
Are supplied to the power supply terminals of the inverters 12a and 12b, respectively, and the amplitudes of the signals CK and ICK are the operating voltage Vou.
It changes according to t. Further, the first signal detection circuit 15
Is connected to the contact B and detects the signal sent from the data carrier device 2 which is superimposed on the reverse phase clock pulse signal ICK.

On the other hand, in the data carrier device 2, the rectifier circuit 21 responds to the voltage between the first and second contacts A and B to which the clock pulse signal CK and the negative phase clock pulse signal ICK are transmitted from the control device 1. Perform full-wave rectification. The second signal detection circuit 22 includes the rectification circuit 2
The signal component superimposed on the voltage rectified by 1 is extracted and output as the second received signal RS2.

The second transmission circuit 23 has a resistor 23a and a switching element 23b which are connected in series between the first and second contacts A and B. Then, the second transmission signal TS2 causes the switching element 23b to conduct.
The impedance between the first and second contacts A and B is changed by switching the non-conduction. As a result, a signal is transmitted to the control device 1.

Further, the clock detection circuit 24 is composed of an inverter 24a which receives the voltage of the first contact A as an input, detects the clock pulse signal CK output from the control device 1, and detects the clock pulse signal CK from the data carrier device 2. Output as operation clock CK2.

The operation of the data communication system configured as above will be described.

First, data transmission from the control device 1 to the data carrier device 2 is performed as follows.

In the control device 1, the operation clock CK1 of the control device 1 is input to the input terminal of the clock generation circuit 12, the inverter 12a outputs the clock pulse signal CK in the same phase as the operation clock CK1, and the inverter 12b outputs the clock pulse signal CK. Operation clock CK
A clock pulse signal ICK having a phase opposite to that of 1 is output. Then, when the first transmission signal TS1 is at the “L” level, the MOS transistor 14a of the first transmission circuit 14 becomes conductive, so that the operating voltage Vout output from the voltage level generation circuit 13 is Voltage R3 / (R1 +
R3) doubles. On the other hand, the first transmission signal TS1 is "H"
When the voltage is at the level, the MOS transistor 14a becomes non-conductive, so that the operating voltage Vout is R3 of the voltage of the power supply 11.
/ (R1 + R2 + R3) times and signal TS1 is "L"
It will be lower than when. That is, the first transmission signal TS
When 1 is "L", the amplitudes of the signals CK and ICK are large, while when they are "H", the amplitudes are small. Clock pulse signal CK and anti-phase clock pulse signal I
CK is, as shown in FIG. 2, the first and second contact points A,
It is output to B respectively.

The data carrier device 2 comprises a first and a second
The clock pulse signal CK and the anti-phase clock pulse signal ICK are received from the contacts A and B of. This signal CK, IC
K is full-wave rectified by the rectifier circuit 21, and thereby the operating voltage of the data carrier device 2 is generated. As shown in FIG. 2 (between terminals C and D), the rectified voltage is
Since the signals are superimposed, the voltage difference between the terminals C and D is extracted by the second signal detection circuit 22, and the transmitted signal is restored as the second received signal RS2.

On the other hand, data transmission from the data carrier device 2 to the control device 1 is performed as follows.

In the data carrier device 2, when the second transmission signal TS2 is "L", the switching element 23b in the second transmission circuit 23 becomes conductive, so that between the first and second contacts A and B. Has a smaller impedance. On the other hand, when the second transmission signal TS2 is "H", the switching element 23b is in the non-conducting state, so that the impedance between the contacts A and B becomes large. Therefore, the amplitudes of the clock pulse signal CK and the negative-phase clock pulse signal ICK at the contacts A and B are determined by the second transmission signal TS.
When 2 is "L", it becomes small, while when it is "H", it becomes large.

The control device 1 extracts the change in the amplitude of the anti-phase clock pulse signal ICK at the second contact B by the first signal detection circuit 15 and outputs the signal transmitted from the data carrier device 2 as the first signal. The received signal RS1 is restored.

As described above, according to the configuration of FIG. 1, the data carrier device 2 receives the clock pulse signals CK and ICK from the control device 1 via the contacts A and B.
Obtains its own operating voltage and operating clock. The control device 1 and the data carrier device 2 also transmit data to each other according to the amplitude changes of the clock pulses CK and ICK. That is, the power supply and the clock supply from the control device 1 to the data carrier device 2 and the bidirectional communication of serial data between the two devices can be executed via only two contacts.

FIG. 3 is a diagram showing another configuration of the data communication system according to the first embodiment of the present invention. 3, the same components as those in FIG. 1 are designated by the same reference numerals as those in FIG. 1, and detailed description thereof will be omitted here.

In comparison with FIG. 1, in the configuration of FIG. 3, first, in the control device 1A, the clock generation circuit 12 is used.
Instead of the above, a clock generation circuit 12A that outputs only the clock pulse signal CK and does not output the clock pulse signal of the opposite phase is provided. Further, instead of the first signal detection circuit 15, a first signal detection circuit 15A that detects a change in the voltage amplitude of the terminal where the voltage level generation circuit 13 outputs the operating voltage Vout as the first reception signal RS1 is provided. Has been. The clock generation circuit 12A is composed of one inverter 12c, and the control device 1A
The reverse phase signal of the operation clock CK1 is output to the first contact A as the clock pulse signal CK. The amplitude of the clock pulse signal CK changes according to the first transmission signal TS1 as in the configuration of FIG. The ground voltage is applied to the second contact B.

Further, in the data carrier device 2A, a rectifier circuit 21A for performing half-wave rectification on the clock pulse signal CK sent to the first contact A is provided in place of the rectifier circuit 21 for performing full-wave rectification. There is. The voltage half-wave rectified by the rectifier circuit 21A is used as the operating voltage of the data carrier device 2A.

The operation of the data communication system configured as described above will be described.

First, data transmission from the control device 1A to the data carrier device 2A is performed as follows.

In the control device 1A, the operation clock CK1 of the control device 1 is input to the input terminal of the clock generation circuit 12A, and the inverter 12c outputs the clock pulse signal CK having a phase opposite to that of the operation clock CK1. Then, similar to the operation of the configuration of FIG. 1, when the first transmission signal TS1 is “L”, the amplitude of the signal CK increases, while when it is “H”, the amplitude decreases.
The clock pulse signal CK is output to the first contact A as shown in FIG.

The data carrier device 2A has a first contact A.
From the clock pulse signal CK. The signal CK is half-wave rectified by the rectifier circuit 21A, and thereby the operating voltage of the data carrier device 2A is generated. As shown in FIG. 4 (between terminals C and D), the rectified voltage is
Since the signals are superimposed, the voltage difference between the terminals C and D is extracted by the second signal detection circuit 22, and the transmitted signal is restored as the second received signal RS2.

On the other hand, data transmission from the data carrier device 2A to the control device 1A is performed as follows.

In the data carrier device 2A, the amplitude of the clock pulse signal CK at the first contact A is the same as the operation of the configuration of FIG. 1 when the second transmission signal TS2 is "L". When the signal TS2 is "H", it decreases as the impedance between B and B decreases, but it increases as the impedance between the contacts A and B increases.

In the control device 1A, the first contact A
The level of the operating voltage Vout changes in accordance with the change in the amplitude of the clock pulse signal CK. This level change is extracted by the first signal detection circuit 15A, and the transmitted signal is restored as the first reception signal RS1.

Thus, according to the configuration of FIG. 3, the data carrier device 2A obtains its own operating voltage and operating clock from the clock pulse signal CK sent from the control device 1A via the contact A. Further, the control device 1A and the data carrier device 2A transmit data to each other according to the change in the amplitude of the clock pulse CK. That is, the supply of power and clock from the control device 1A to the data carrier device 2A, and the bidirectional communication of serial data between the two devices can be executed via only two contacts.

In this embodiment, the voltage level generation circuit 13 is composed of three resistors, but the number of resistors may be other than three. For example, the resistor R3 may be omitted and only the resistors R1 and R2 may be used. In this case, for example, the configuration is as shown in FIG. 5, and the voltage level generation circuit 133 and the clock generation circuit 12 are connected in series. In addition, the operating voltage Vout is set to the resistors R2 and R3.
It is assumed that the output is performed from the end between the two, but the output may be output from the other end. For example, the operating voltage Vout may be output from the end between the resistors R1 and R2.

In the configuration of FIG. 1, the first signal detection circuit 15 may be connected to the first contact A or may be connected to the output terminal of the operating voltage Vout of the voltage level generation circuit 13. Further, in the configuration of FIG. 3, the first signal detection circuit 15A may be connected to either of the first and second contacts A and B.

Further, as shown in FIG. 6, the switching elements 141a, which constitute the first transmission circuits 141, 142,
142a may be connected in series with at least one of the plurality of resistors forming the voltage level generation circuits 131 and 132.

(Second Embodiment) FIG. 7 is a diagram showing the configuration of a data communication system according to a second embodiment of the present invention. 7, the same components as those in FIG. 1 or 3 are designated by the same reference numerals as those in FIG. 1 or 3, and detailed description thereof will be omitted here.

Compared to FIG. 3, in the configuration of FIG. 7, first, in the control device 1B, the clock generation circuit 12A is omitted, and the output voltage Vout of the voltage level generation circuit 13 is used as a signal voltage at the first terminal A. Has been output to.

In the data carrier device 2B, the second
In addition to the transmission circuit 23 of the
Series regulator 25 for stabilizing the operating voltage generated from the signal voltage Vout supplied to the contact A of the
And the change in voltage between the first and second contacts A, B
Second signal detection circuit 2 for detecting the received signal RS2 as
6 and a clock generation circuit 27 for generating the operation clock CK2 of the data carrier device 2B.

The series regulator 25 stabilizes the voltage of the terminal C, reduces its fluctuation, and supplies it as the operating voltage of the data carrier device 2B. The second signal detection circuit 26 detects a change in the signal voltage Vout and restores the transmitted signal as the second reception signal RS2. The second clock generation circuit 27 generates an operation clock CK2 when a voltage is applied to the data carrier device 2B.

The operation of the data communication system configured as described above will be described.

First, data transmission from the control device 1B to the data carrier device 2B is performed as follows.

In the control device 1B, when the first transmission signal TS1 is at "L" level, the first transmission circuit 1
Since the 4th MOS transistor 14a becomes conductive,
The signal voltage Vou output from the voltage level generation circuit 13
t becomes R3 / (R1 + R3) times the voltage of the power supply 11. On the other hand, when the first transmission signal TS1 is at the “H” level, the MOS transistor 14a is in a non-conducting state, so that the signal voltage Vout is R3 / (R1
+ R2 + R3) times, which is lower than when the signal TS1 is "L". That is, the signal voltage Vout is output to the first contact A as shown in FIG.

The data carrier device 2B has a first contact A
The change in the voltage at is detected by the second signal detection circuit 26 and is restored as the second received signal RS2. Also,
The regulator 25 stabilizes the voltage of the terminal C, as shown in FIG. Further, the second clock generation circuit 27
Is the signal voltage Vou sent from the control device 1B.
The operation clock CK2 is generated in response to the application of t.

On the other hand, data transmission from the data carrier device 2B to the control device 1B is performed as follows.

In the data carrier device 2B, the signal voltage Vout at the first contact A is equal to the second transmission signal T
When S2 is "L", the impedance between the contacts A and B is reduced to be smaller, while the signal TS2 is reduced.
Is "H", the impedance between the contacts A and B is increased, and the impedance is increased. The control device 1B extracts a change in the voltage of the signal voltage Vout by the first signal detection circuit 15A and outputs the transmitted signal as the first signal.
Of the received signal RS1.

Thus, according to the configuration of FIG. 7, the data carrier device 2B obtains its own operating voltage from the signal voltage Vout sent from the control device 1B via the contact A. Further, the control device 1B and the data carrier device 2B transmit data to each other according to the change in the signal voltage Vout. That is, the control device 1
Power supply from B to the data carrier device 2B and bidirectional communication of serial data between both devices can be executed only through two contacts.

In this embodiment, the voltage level generating circuit 13 is composed of three resistors, but the number of resistors may be other than three. For example, the resistor R3 may be omitted and only the resistors R1 and R2 may be used. Although the signal voltage Vout is output from the end between the resistors R2 and R3, it may be output from the other end. For example, from the end between the resistors R1 and R2 to the signal voltage V
You may output out.

(Third Embodiment) FIG. 9 is a block diagram of a data communication system according to a third embodiment of the present invention. In FIG. 9, components common to those in FIG. 1 or FIG.
Alternatively, the same reference numerals as in FIG. 7 are attached, and detailed description thereof will be omitted here.

In comparison with FIG. 1, in the configuration of FIG. 9, first, in the control device 1C, the pulse widths of the clock pulse signals CK and ICK generated by the clock generation circuit 12 are changed according to the first transmission signal TS1. A pulse width conversion circuit 16 is provided. Pulse width conversion circuit 1
6 receives the operation clock CK1 of the control device 1C and changes its pulse width according to the first transmission signal TS1. Then, the clock generation circuit 12 outputs the clock pulse signal CK and its reverse phase clock pulse signal ICK based on the signal output from the pulse width conversion circuit 16 instead of the operation clock CK1.

The voltage level generation circuit 13A is composed of two resistors R1 and R2 for dividing the voltage of the power supply 11, and outputs a constant operating voltage Vout from the end between the resistors R1 and R2. . This operating voltage Vout is
It is supplied to each inverter 12a, 12b of the clock generation circuit 12. That is, both the clock pulse signal CK and the reverse phase clock pulse signal ICK have a constant amplitude and the pulse width changes according to the first transmission signal TS1.

Further, in the data carrier device 2C, in addition to the rectifying circuit 21, the first transmitting circuit 23 and the second clock generating circuit 27, the change of the pulse width at the first contact A is changed to the second receiving signal RS2. A second signal detection circuit 28 for detecting the signal is provided. Second signal detection circuit 28
Detects a change in the pulse width of the clock pulse signal CK at the first contact A using the operation clock CK2 generated by the second clock generation circuit 27.

The operation of the data communication system configured as above will be described.

First, data transmission from the control device 1C to the data carrier device 2C is performed as follows.

In the control device 1C, the pulse width conversion circuit 16 outputs a pulse signal having a width corresponding to "L" or "H" of the first transmission signal TS1. The clock generation circuit 12 receives the output of the pulse width conversion circuit 16, outputs the clock pulse signal CK in phase with this pulse signal from the inverter 12a, and outputs the clock pulse signal ICK in antiphase from the inverter 12b. Clock pulse signal CK and anti-phase clock pulse signal ICK
Is, as shown in FIG. 10, first and second contacts A, B
Are output respectively.

The data carrier device 2C receives the clock pulse signal CK and the anti-phase clock pulse signal ICK from the first and second contacts A and B. This signal CK, I
The CK is full-wave rectified by the rectifier circuit 21, and thereby the operating voltage of the data carrier device 2C is generated. Further, the second clock generation circuit 27 generates the operation clock CK2 by applying the rectified voltage.

Then, the second signal detection circuit 28
The control device 1 is connected to the first contact A by using the operation clock CK2 generated by the clock generation circuit 27 of
The pulse width of the clock pulse signal CK supplied from C is measured. Then, the second received signal RS2 is obtained by associating the measured pulse width with "L" or "H" of the data logic.

On the other hand, data transmission from the data carrier device 2C to the control device 1C is performed as follows.

In the data carrier device 2C, the amplitudes of the clock pulse signals CK and ICK at the contacts A and B are the same as those in the configuration of FIG. 1 when the second transmission signal TS2 is "L". , B decreases when the impedance between B and B decreases, and when the signal TS2 is "H", the impedance between contacts A and B increases and increases.

The control device 1C changes the amplitude of the negative phase clock pulse signal ICK at the second contact B by
The signal received by the first signal detection circuit 15 and transmitted from the data carrier device 2C is the first reception signal RS1.
To restore as.

As described above, according to the configuration of FIG. 9, the data carrier device 2C is connected to the contacts A, from the control device 1C.
The self operating voltage is obtained from the clock pulse signals CK and ICK sent via B. Also, the control device 1
C transmits data to the data carrier device 2C according to the pulse width changes of the clock pulse signals CK and ICK, and the data carrier device 2C transmits data to the control device 1C according to the amplitude change of the clock pulse signals CK and ICK. To do. That is, supply of electric power from the control device 1C to the data carrier device 2C,
Two-way communication of serial data between both devices
It can only be carried out via one contact.

In the configuration of FIG. 9, the control device 1C transmits the clock pulse signal CK and the anti-phase clock pulse signal ICK, but as in FIG.
A configuration is also possible in which the reverse phase clock pulse signal is not transmitted. In this case, the control device 1C has the second contact B
The rectifier circuit 21 of the data carrier device 2C may be configured to perform half-wave rectification while applying a ground potential to the.

The first signal detection circuit 15 may be connected to the first contact A, or the voltage level generation circuit 13 may be connected.
It may be connected to the output terminal of the operating voltage Vout of A.

(Fourth Embodiment) FIG. 11 shows a fourth embodiment of the present invention.
It is a figure which shows the structure of the data communication system which concerns on embodiment of this. 11, constituent elements common to FIG. 3 are assigned the same reference numerals as those in FIG. 3, and detailed description thereof will be omitted here.

In the configuration of FIG. 11, the control device 1D
In addition to the first signal detection circuit 15A, is a clock generation circuit 17 that receives a voltage from the power supply 11 to generate a clock pulse signal CK, and a lower voltage level of the clock pulse signal CK is the first transmission signal TS1. And a first transmission circuit 18 that changes in accordance with the above. The clock pulse signal CK is supplied to the first contact A, and the ground potential is applied to the second contact B.

The data carrier device 2D has substantially the same structure as the data carrier device 2A shown in FIG. 3, but a clock detecting circuit 24A having a different internal structure from that of the clock detecting circuit 24 is provided. There is.

The clock generation circuit 17 is composed of three resistors R1, R2 and R3 for dividing the voltage of the power supply 11 and a MOS transistor 17a connected in parallel with the resistor R1. The operation clock CK1 of the control device 1D is applied to the gate of the MOS transistor 17a, and the conduction / non-conduction of the MOS transistor 17a is switched according to the change in the voltage level of the operation clock CK1. Therefore, the voltage at the end between the resistors R1 and R2 changes in synchronization with the operation clock CK1 and is output to the first contact A as the clock pulse signal CK.

The first transmission circuit 18 has a MOS transistor 18a connected in parallel to the resistor R3 of the clock generation circuit 17. The first transmission signal TS1 is given to the gate of the MOS transistor 18a, and the signal T
In response to the change in the voltage level of S1, the MOS transistor 1
The conduction / non-conduction of 8a is switched. Therefore, the lower voltage level of the clock pulse signal CK changes according to the first transmission signal TS1.

The clock detection circuit 24A includes a differentiation circuit composed of a resistor 24b and a capacitor 24c, and a comparator 2.
4d, the operation clock CK2 of the data carrier device 2D is detected from the clock pulse signal CK supplied to the first contact A.

The operation of the data communication system configured as above will be described.

First, data transmission from the control device 1D to the data carrier device 2D is performed as follows.

In the control device 1D, the operation clock CK1 of the control device 1D is input to the input terminal of the clock generation circuit 17, and the clock pulse signal CK is output from the end between the resistors R1 and R2. The higher voltage level of the clock pulse signal CK is approximately the voltage level (V) of the power supply 11, but the lower voltage level is controlled by the first transmission circuit 18. That is, when the first transmission signal TS1 is "H", the MOS transistor 18a of the first transmission circuit 18 is in a non-conducting state, so that the lower voltage level of the clock pulse signal CK is V1.
(= V · (R2 + R3) / (R1 + R2 + R3)). On the other hand, when the first transmission signal TS1 is "L", the MOS transistor 18a of the first transmission circuit 18 becomes conductive, so that the lower voltage level of the clock pulse signal CK is V2 (= V. R2 / (R1 + R2),
It becomes lower than V1. As a result, the clock pulse signal CK supplied to the first contact A is, as shown in FIG.
When the first transmission signal TS1 is "H", the potential difference (V-
While it becomes a pulse signal with V1), when it is "L",
The pulse signal has a potential difference (V-V2).

The data carrier device 2D has the first contact A
From the clock pulse signal CK. This signal CK is half-wave rectified by the rectifier circuit 21A, and thereby the operating voltage of the data carrier device 2D is generated. Since a signal is superimposed on this rectified voltage, this terminal C
The voltage difference between −D is extracted by the second signal detection circuit 22, and the transmitted signal is restored as the second received signal RS2. Further, the clock extraction circuit 24A restores the operation clock CK2 by removing the DC component of the clock pulse signal CK by the differentiating circuit and extracting the change.

On the other hand, data transmission from the data carrier device 2D to the control device 1D is performed as follows.

In the control device 1D, the first transmission signal TS1 is fixed at "H" and the operation clock CK1 is given to the clock generation circuit 17. Data carrier device 2D
Then, similarly to the operation of the configuration of FIG. 1, the amplitude of the clock pulse signal CK at the first contact A is equal to the second transmission signal T.
When S2 is "L", the impedance between the contacts A and B is reduced, and the impedance is reduced, while the signal TS is reduced.
When "2" is "H", the impedance between the contacts A and B increases, and the impedance increases. The control device 1D extracts the change in the voltage at the first contact A by the first signal detection circuit 15A and restores the transmitted signal as the first reception signal RS1.

Thus, according to the configuration of FIG. 11, the data carrier device 2D is connected to the contact A from the control device 1D.
From the clock pulse signal CK sent via, the self operating voltage and operating clock are obtained. In addition, the control device 1D causes the data carrier device 2 to transfer the data according to the change in the lower voltage level of the clock pulse signal CK.
At the same time as transmitting the data to D, the data carrier device 2D transmits data to the control device 1D according to the amplitude change of the clock pulse signal CK. That is, the power supply and the clock supply from the control device 1D to the data carrier device 2D and the bidirectional communication of serial data between the two devices can be executed via only two contacts.

Here, the clock pulse signal CK
Although the data transmission from the control device 1D to the data carrier device 2D is performed by changing the voltage level of the lower one, the higher voltage level of the clock pulse signal CK can be changed. is there.

Further, the configuration of FIG. 11 can be modified to a configuration in which the control device 1D transmits an anti-phase clock pulse signal as in the case of FIG. In this case, the half-wave rectifier circuit 21A of the data carrier device 2D may be replaced with one that performs full-wave rectification.

[0093]

As described above, according to the present invention, in a data communication system, bidirectional data transmission between the control device and the data carrier device is performed as well as supply of power and clock from the control device to the data carrier device. It can be done with two contacts. Therefore, it is possible to realize a data communication system that is more suitable for miniaturization than ever before.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a data communication system according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the configuration of FIG.

FIG. 3 is a diagram showing another configuration of the data communication system according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the configuration of FIG.

FIG. 5 is a diagram showing another configuration example of a voltage level generation circuit.

6A and 6B are diagrams showing another configuration example of the first transmission circuit.

FIG. 7 is a diagram showing a configuration of a data communication system according to a second embodiment of the present invention.

FIG. 8 is a timing chart showing the operation of the configuration of FIG.

FIG. 9 is a diagram showing a configuration of a data communication system according to a third embodiment of the present invention.

10 is a timing chart showing the operation of the configuration of FIG.

FIG. 11 is a diagram showing a configuration of a data communication system according to a fourth embodiment of the present invention.

12 is a timing chart showing the operation of the configuration of FIG.

FIG. 13 is a configuration example of a conventional data communication system.

[Explanation of symbols]

1, 1A, 1B, 1C, 1D Control device 2, 2A, 2B, 2C, 2D Data carrier device 11 Power supply 12, 12A Clock generation circuit 13, 13A, 131, 132, 133 Voltage level generation circuit R1, R2, R3 Resistance 14, 141, 142 First transmission circuit 14a, 141a, 142a MOS transistor (switching element) 15, 15A First signal detection circuit 16 Pulse width conversion circuit 17 Clock generation circuit 18 First transmission circuit 21, 21A Rectification circuit 22 second signal detection circuit 23 second transmission circuit 24, 24A clock detection circuit 25 regulator 26 second signal detection circuit 28 second signal detection circuit CK clock pulse signal ICK anti-phase clock pulse signal Vout operating voltage, signal Voltage TS1 First transmission signal RS1 First reception signal TS 2 Second transmission signal RS2 Second reception signal

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] August 6, 2002 (2002.8.6)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

[0004] An object of the present invention, in a system in which a control device and a data carrier device perform data communications, with two contacts, and issues to enable two-way data communications.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0066

[Correction method] Change

[Correction content]

Further, in the data carrier device 2C, in addition to the rectifying circuit 21, the second transmitting circuit 23 and the second clock generating circuit 27, the change in the pulse width at the first contact A is changed to the second receiving signal RS2. A second signal detection circuit 28 for detecting the signal is provided. Second signal detection circuit 28
Detects a change in the pulse width of the clock pulse signal CK at the first contact A using the operation clock CK2 generated by the second clock generation circuit 27.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0087

[Correction method] Change

[Correction content]

The data carrier device 2D has the first contact A
From the clock pulse signal CK. This signal CK is half-wave rectified by the rectifier circuit 21A, and thereby the operating voltage of the data carrier device 2D is generated. Since a signal is superimposed on this rectified voltage, this terminal C
The voltage difference between −D is extracted by the second signal detection circuit 22, and the transmitted signal is restored as the second received signal RS2. Further, the clock detection circuit 24A restores the operation clock CK2 by removing the DC component of the clock pulse signal CK by the differentiating circuit and extracting the change.

Continued front page    F term (reference) 5K029 AA18 CC01 DD25 EE06 FF02                       FF10                 5K046 AA01 BA01 BB05 PP01 YY02

Claims (11)

[Claims] 1. A system in which a control device and a data carrier device perform data communication via first and second contacts, wherein the control device supplies a power source for supplying electric power and a clock pulse signal. A voltage generation circuit that supplies at least one of the first and second contacts, a voltage level generation circuit that converts the voltage of the power supply and supplies the voltage to the clock generation circuit as an operating voltage, and the voltage level generation circuit. A first transmission circuit that changes the operating voltage generated by the first transmission signal according to a first transmission signal; and a change in the voltage amplitude of one of the first and second contacts is detected as a first reception signal. And a first signal detecting circuit for rectifying the voltage between the first and second contacts, A rectifier circuit that supplies an operating voltage, a second signal detection circuit that detects a change in the operating voltage rectified by the rectifier circuit as a second received signal, and at least one of the first and second contacts. A clock detection circuit that generates an operation clock from the supplied clock pulse signal and an impedance between the first and second contacts are
And a second transmission circuit that changes in accordance with the transmission signal of 1. 2. The data communication system according to claim 1, wherein the voltage level generation circuit has a plurality of resistors arranged in series between the power supply and the ground, and any one of the plurality of resistors is provided. The first transmission circuit is connected in parallel with at least one of the plurality of resistors, and the conduction / non-conduction is the A data communication system having a switching element that switches according to a transmission signal. 3. The data communication system according to claim 1, wherein the voltage level generation circuit has a plurality of resistors arranged in series between the power supply and the ground, and any one of the plurality of resistors is provided. The first transmission circuit is connected in series with at least one of the plurality of resistors, and the conduction / non-conduction is the A data communication system having a switching element that switches according to a transmission signal. 4. A system in which a control device and a data carrier device perform data communication via first and second contacts, wherein the control device supplies a power supply for supplying power and a voltage of the power supply. A voltage level generating circuit that converts and supplies as a signal voltage between the first and second contacts, and a first voltage that changes the signal voltage generated by the voltage level generating circuit according to a first transmission signal. A first signal detection circuit that detects a change in voltage between the first and second contacts as a first reception signal; and the data carrier device includes the first signal detection circuit. And a regulator for stabilizing the voltage between the second contact and the operating voltage of the data carrier device, and a change in the voltage between the first and second contacts as a second reception signal. A second signal detection circuit for output, the impedance between the first and second contacts, the second
And a second transmission circuit that changes in accordance with the transmission signal of 1. 5. The data communication system according to claim 4, wherein the voltage level generation circuit has a plurality of resistors arranged in series between the power supply and the ground, and any one of the plurality of resistors is provided. The first transmission circuit is connected in parallel with at least one of the plurality of resistors, and the conduction / non-conduction is the above-mentioned. A data communication system having a switching element that switches according to a transmission signal. 6. A system in which a control device and a data carrier device perform data communication via first and second contacts, wherein the control device supplies a power supply for supplying electric power and a clock pulse signal. A clock generation circuit that supplies at least one of the first and second contacts, a voltage level generation circuit that converts the voltage of the power supply and supplies the voltage to the clock generation circuit as an operating voltage, and the clock generation circuit. A pulse width conversion circuit that changes the pulse width of the generated clock pulse signal according to the first transmission signal, and a change in the voltage amplitude of either the first or second voltage is detected as the first reception signal. A first signal detection circuit, wherein the data carrier device rectifies the voltage between the first and second contacts, A rectifier circuit supplied as an operating voltage of a rear device; a second signal detection circuit for detecting a change in pulse width at one of the first and second contacts as a second reception signal; The impedance between the second contacts is
And a second transmission circuit that changes in accordance with the transmission signal of 1. 7. The data communication system according to claim 1, wherein the first signal detection circuit generates the voltage level in place of a change in voltage amplitude of one of the first and second contacts. A data communication system, wherein a circuit detects a change in voltage amplitude of a terminal outputting the operating voltage as the first received signal. 8. A system in which a control device and a data carrier device perform data communication via first and second contacts, wherein the control device includes a power supply for supplying power, and an operating voltage from the power supply. In response to the above, the voltage level of one of the clock pulse circuit that generates the clock pulse signal and supplies it to at least one of the first and second contacts and the clock pulse signal that the clock generation circuit generates is A first transmission circuit that changes according to a first transmission signal; and a first signal detection circuit that detects a change in voltage amplitude of any of the first and second contacts as a first reception signal. The data carrier device includes a rectifying circuit that rectifies a voltage between the first and second contacts and supplies the rectified voltage as an operating voltage of the data carrier device. A second signal detection circuit for detecting a change in the operating voltage rectified by the rectification circuit as a second reception signal; and a clock pulse signal supplied to at least one of the first and second contacts. A clock detection circuit that generates an operation clock, and an impedance between the first and second contacts,
And a second transmission circuit that changes in accordance with the transmission signal of 1. 9. The data communication system according to claim 1, 6 or 8, wherein the control device supplies the clock pulse signal generated by the clock generation circuit to the first contact, and the second contact. A clock pulse signal having a phase opposite to that of the clock pulse signal generated by the clock generating circuit is supplied to the contact of the rectifier circuit, the rectifying circuit with respect to a voltage between the first and second contacts. A data communication system characterized by performing full-wave rectification. 10. The data communication system according to claim 1, 6 or 8, wherein the control device supplies the clock pulse signal generated by the clock generation circuit to the first contact, and the second contact. The data communication system is characterized in that a ground potential is supplied to the contact of the above, and the rectifier circuit performs half-wave rectification on the voltage between the first and second contacts. 11. The data communication system according to claim 1, wherein the control device includes the voltage level generation circuit and the clock generation circuit.
A data communication system characterized by being connected in series.