JP2003058905A - CLAMPING OF z VALUE IN NEAR RANGE OF z FOR MAXIMIZING ACCURACY OF VISUALLY IMPORTANT z COMPONENT AND EVADING CLIPPING NEAR z IN GRAPHICS RENDERING SYSTEM - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure accuracy of depth of a z value when depth data of the z value should be compressed in a 3D (three-dimensional) graphics rendering system. SOLUTION: A graphics pipe line performs z buffering and when an anti- aliasing rendering mode is selected, z value bit compression is performed to more efficiently use usable z buffer memory. The accuracy of visually important z components is improved by using z clamping structure by clamping the z value of a pixel within a prescribed z axis range in the vicinity of a z=0 view/ camera (view port) plane. This fact enables use of a z clipping surface of excessively in the vicinity of the viewpoint/camera plane and the accuracy of the z value to the remaining depth of a scene is secured as evading undesirable visual artifact which is generated when the object rendered in the vicinity of the viewpoint/camera plane is clipped.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to computer graphics, and more particularly to interactive graphics systems such as home video game platforms. Still more particularly, the invention provides a Z that is visually important in rendering anti-aliased scenes.
It relates to Z-value clamping in the Z-nearest range in order to maximize the accuracy of the components and avoid Z-nearest clipping.

[0002]

BACKGROUND OF THE INVENTION Many of us are amazingly realistic dinosaurs,
I've seen movies that include aliens, animated toys, and other fantastic creatures. Such animations are made possible by computer graphics. Using these techniques, computer graphics artists can specify what each object should look like, and how it should change its appearance over time, and the computer models the objects On a display such as a TV or computer screen. The computer uses the position and orientation of each object in the scene, the direction in which light appears to be incident on each object, the surface texture of each object, and other factors to ensure that each portion of the displayed image is exactly the same. Responsible for performing many of the operations necessary to ensure that it is correctly colored and shaped.

Due to the complexity of computer graphics generation, just a few years ago, computer generated 3D graphics were largely limited to expensive dedicated flight simulators, high-end graphics workstations, and supercomputers. It had been. Although the public has seen some of the images produced by these computer systems in movies and expensive television advertisements, most of us have no direct contact with the computers that do the graphics generation. There wasn't. This has all changed with the availability of relatively inexpensive 3D graphics platforms, such as the Nintendo 64 (R), and various 3D graphics cards currently available in personal computers. It is now possible to come into contact with exciting 3D animations and simulations on relatively inexpensive computer graphics systems at home or in the office.

[0004]

Most 3D graphics computer systems have a Z-axis (scene depth).
In response to polygon vertex attribute data that typically contains values,
Render and prepare an image for display. A well-known technique called Z-buffering is often used to properly render objects according to their respective depth in the 3D scene (ie distance from the observer / camera). Since processing large amounts of 3D image polygon vertex attribute data can be very time consuming, graphics system designers often use polygon decimation and clipping processes to eliminate processing of hidden image data. This hidden image data is typically
Polygon vertex data outside the view frustum in a virtual 3D image rendering space called "camera space" (also called "screen space"), separated by a given "clipping" plane. For example, the portion of the 3D scene or object behind the camera (viewport) position need not be rendered and may be decimated or clipped. Similarly, scene parts and 3D objects that are very far in the scene distance (ie, far from the camera / viewpoint along the scene depth or Z axis) need not be rendered.

Scene depth clipping may be performed using both near and far clipping planes, where the far clipping plane is many times the depth of the near clipping plane. Scene depth clipping also
It may be done with a clipping plane at or behind the camera / viewpoint position (ie Z = 0 plane), or no near clipping plane at all. However, for various reasons not described in detail herein, a 3D image at or very close to the camera / viewpoint position is used.
The rendering of objects can cause certain data processing problems such as overflow and wrapping errors due to the small Z values involved. For example, in the case of geometry projection, "too close" to the camera (Z = 0) plane
The w (uniform coordinate scale factor) value of the vertex is very small. Dividing the vertex x, y and z coordinate attributes by such small w values during screen space transformation operations often results in accuracy and overflow issues. Especially w
When = 0, the obtained scale value becomes infinity. Geometry clipping on the near plane avoids this problem. That is, each triangle with the violating vertices is decomposed into parts by the near plane, and the "too close" half is discarded. Therefore, when performing scene depth clipping using a near clipping plane in front of the camera / viewpoint position, the near clipping plane must be located far enough in front of the camera to avoid such overflow or wrapping errors. .

Alternatively, without using the near clipping plane,
Or if scene depth clipping is done using the camera / viewpoint or a clipping plane behind it, the responsibility to prevent such overflow and wrapping issues lies with the allowable distance between the camera position and the rendered object. Must be imposed on the application program by regulating One problem that designers of graphics systems have faced in the past is that certain undesired visual artifacts associated with clipping of polygons in the displayed 3D image object that approach the observer's plane (ie camera / view plane). How to avoid the effect. In particular, graphics artists and game developers may find 3D clipped by a clipping plane in front of the viewer.
I hate to see objects. This is because it makes a hole in the object, giving the impression that the object is hollow. One solution is to define a 6-sided view frustum clipping box such that the near clipping plane is very close to the viewpoint / camera plane (ie Z = 0 plane), and any 3D animated object The point is to establish an application program rule that you must not come close to the viewpoint / camera plane side. By placing the near clipping plane very close to the viewpoint / camera plane, objects that need to be rendered slightly closer to the viewpoint / camera plane are less likely to be too close to be adversely affected by clipping. Unfortunately, placing the near clipping plane very close to the viewpoint / camera plane reduces the Z depth accuracy towards the far clipping plane. This Z
The accuracy problem is exacerbated especially when only a limited number of Z-buffer bits are available for depth accuracy. The smaller the number of bits to represent the Z value, the greater the accuracy problem.

When performing Z-buffering in a graphics system where many bits are available, eg, 24 bits or more, to represent the Z-axis depth value in hardware, Z-value precision may not be an issue. However, in certain systems or embodiments where fewer bits are available to represent Z-axis depth values, lack of sufficient Z-value accuracy can severely impact Z-buffering performance and accuracy. It may be. For example, in certain embodiments it may be desirable to perform data compression to accommodate storage memory constraints. When Z-data compression is performed, the degree of Z-accuracy to provide accurate Z-buffering can be adversely affected.

[0008]

The present invention also provides a Z-value depth accuracy when performing Z-buffering in a 3D graphics rendering system when the Z-value depth data must be compressed. The above problems are solved by providing techniques and arrangements for ensuring.

The present invention also provides a 3D graphics rendering system to ensure Z-value depth accuracy while avoiding undesirable visual artifacts that occur when an object is rendered too close to the viewpoint / camera plane. , View Z clipping plane /
The above problems are solved by providing techniques and configurations to allow use very close to the camera plane.

The present invention also provides a 3D graphics rendering system in which the Z depth value corresponding to one vertex is represented using, for example, 23 bits or less.
The above problems are solved by providing techniques and configurations for performing buffering.

More specifically, in one embodiment of the present invention, a Z-clamping arrangement is used by providing Z-value clamping within a predetermined range from the Z = 0 viewpoint / camera (viewport) plane. To improve the accuracy of the visually important Z component. This configuration keeps the Z-precision while avoiding unwanted visual artifacts that occur when objects rendered close to the viewpoint / camera plane are clipped to the viewpoint / camera plane's extremes. It can be used near to. The near clipping plane “znear” is Z =
It is set to the Z plane very close to the 0 plane, and the far clipping plane “zfar” is set to the Z plane far from the Z = 0 plane. Then, set the clamping surface "znear2" to Z
= Znear * (1 << n). Here, n is the position on the znea2 plane.
An integer that effectively determines the Z resolution of the scene by setting it relative to the plane. zneaar
Z-buffering is done for all pixels in the range between the two planes and the Z-far clipping plane. zne
Any pixel lying in the range between the ar plane and the znear2 plane will have its Z value clamped to, for example, zero or the Z value of the clamping plane. Hardware geometry clipping is performed for all pixels where z <znear.

In one embodiment, a conventional Z value compression circuit provided in the graphics pipeline is extended to perform Z clamping within a predetermined range of Z values. The extended circuit includes an adder to shift the Z value left one bit or more to the left before compression, and a gate to mask out the non-zero shifted most significant bits to zero.

[0013]

DETAILED DESCRIPTION OF THE INVENTION FIG. 1 illustrates an example of an interactive 3D computer graphics system 50. System 5
0 can be used to play interactive 3D video games with interesting stereo sounds. It may also be used in various other applications.

In the present example, system 50 is capable of interactively processing real-time digital representations or models of a three-dimensional world. The system 50
Part or all of the world can be displayed from any arbitrary viewpoint. For example, system 50
Can interactively change viewpoints in response to real-time input from handheld controllers 52a, 52b or other input devices. This allows a player of the game to see the world through the eyes of people inside or outside the world. System 5
0 can be used for applications that do not require real-time 3D interactive display (eg, 2D display generation and / or non-interactive display), but it is very realistic for its ability to display high quality 3D images very quickly. And can be used to create exciting gameplay or other graphical interactions.

To play a video game or other application using system 50, a user first connects main unit 54 to his color television 56 by connecting a cable 58 therebetween.
Or connect to other display devices. The main unit 54 generates both a video signal and an audio signal for controlling the color television 56. The video signal is
It controls the image displayed on the television screen 59, and the audio signal is the stereo speaker 61 of the television.
It is reproduced as a sound via L and 61R.

The user also needs to connect the main unit 54 to a power source. This power supply connects to a standard household electrical outlet to supply household current to the main unit 5
4 may be a conventional AC adapter (not shown) that converts to a suitable lower DC voltage signal to power the 4. As another embodiment, a battery may be used.

A user may use the hand controllers 52a, 52b to control the main unit 54.
The control 60 may be used, for example, to specify the direction (up, down, left, right, near, or far) in which the character displayed on the television 56 should move within the 3D world. The control 60 also provides input for other applications (eg, menu selection, pointer / cursor control, etc.). The controller 52 can take various forms. In the present example, the illustrated controllers 52 each include controls 60 as joysticks, push buttons and / or direction switches. The controller 52 uses a cable to
Alternatively, it may be connected to the main unit 54 wirelessly via electromagnetic (eg radio frequency or infrared) waves.

To play an application such as a game, the user selects an appropriate storage medium 62 that stores the video game or other application he or she wishes to play, and that storage medium is slot 64 of main unit 54. To insert. Storage medium 62 may be, for example, a specially coded and / or encrypted optical and / or magnetic disk. The user operates the power switch 66 to operate the main unit 54.
May be turned on to cause the main unit to start running a video game or other application based on the software stored in the storage medium 62. A user may operate the controller 52 to provide an input to the main unit 54. For example, manipulating control 60 may start a game or other application. By moving the other controls 60, the animated character can be moved in different directions and the user's viewpoint in the 3D world can be changed. Depending on the particular software stored on the storage medium 62, the various controls 60 on the controller 52 may perform different functions at different times.

Example Electronic Circuitry of Entire System FIG. 2 shows a block diagram of example elements of system 50. The main elements include: A main processor (CPU) 110, a main memory 112, and a graphics and audio processor 114

In this example, the main processor 110
(For example, function-enhancing IBM Power PC75
0) receives input from the handheld controller 108 (and / or other input device) via the graphics and processor 114. Main processor 11
0 interactively responds to user input and executes, for example, a video game or other program provided from external storage medium 62 via mass storage access device 106, such as an optical disk drive. For video game play, by way of example, main processor 110 may perform collision detection and animation processing in addition to various interactive and control functions.

In this example, the main processor 110
Generates 3D graphics commands and voice commands and sends them to the graphics and voice processor 114. Graphics and audio processor 1
14 processes these commands to produce an entertaining visual image on the display 59 and an entertaining stereo sound on the stereo speakers 61R, 61L or other suitable audio production device.

The exemplary system 50 receives image signals from the graphics and audio processor 114,
It has a video encoder 120 for converting the image signal into an analog and / or digital video signal suitable for display on a standard display device such as a computer monitor or a home color television 56. The system 50 also compresses and decompresses the digitized audio signal, and optionally converts between digital and analog audio signaling formats, an audio codec (compressor / decompressor) 12.
Have two. The audio codec 122 has a buffer 124.
Audio input via the and process them into the graphics and audio processor 114 (eg, mixed with other audio signals generated by the processor and / or received via the audio streaming output of the mass storage access device 106). A) can be supplied for. Graphics and audio processor 114 in this example
Can store voice related information in the voice memory 126 available for voice tasks. The graphics and audio processor 114 supplies the resulting audio output signal to the audio codec 122 for decompression and conversion into analog signals (eg, via buffer amplifiers 128L, 128R), thereby causing the speaker 61L. , 61R.

Graphics and audio processor 11
4 has the ability to contact various additional devices that may be present in system 50. For example, parallel digital bus 130 may be used to communicate with mass storage access device 106 and / or other elements. The serial peripheral bus 132 may be, for example: a programmable read-only memory and / or a real-time clock 134; a modem 136 or other networked interface (which may be the Internet or a program or data may be downloaded or uploaded; The system 50 may be connected to a communications network 138, such as other digital networks), and may communicate with various peripheral devices or other devices, including flash memory 140.

A further external serial bus 142 may be used to communicate with additional expansion memory 144 (eg memory cards) and other devices. Various devices may be used to connect various devices to buses 130, 132, 142.

Example Graphics and Audio Processor FIG. 3 is a block diagram of an example graphics and audio processor 114. In one example, the graphics and audio processor 114 is a single chip ASI.
It may be C (application specific integrated circuit). In this example, the graphics and audio processor 114
Includes: Processor interface 150 memory interface / controller 152 3D graphics processor 154 audio digital signal processor (DSP) 156 audio memory interface 158 audio interface and mixer 160 peripheral controller 162 and display controller 164

The 3D graphics processor 154 is
Perform graphics processing tasks. Audio digital signal processor 156 performs audio processing tasks. The display controller 164 accesses the image information from the main memory 112 and sends it to the display device 10.
2 to the video encoder 120 for display. Voice interface and mixer 160 interfaces with voice codec 122 and also voice from different sources (eg voice streaming from mass storage access device 106, output of voice DSP 156, and external voice input received via voice codec 122). Can be mixed. Processor interface 150 provides a data and control interface between main processor 110 and graphics and audio processor 114.

Memory interface 152 provides a data and control interface between graphics and audio processor 114 and memory 112. In the present example, the main processor 110 accesses the main memory 112 via a processor interface 150 and a memory interface 152 that are part of the graphics and audio processor 114. Peripheral controller 162 provides a data and control interface between graphics and audio processor 114 and the various peripherals described above. Audio memory interface 158 provides an interface with audio memory 126.

Example Graphics Pipeline FIG. 4 shows a more detailed view of an example 3D graphics processor 154. 3D graphics processor 1
54 includes, among other things, a command processor 200 and a 3D graphics pipeline 180. Main processor 110 communicates a stream of data (eg, a graphics command stream and display list) to command processor 200. Main processor 1
The 10 has a two-level cache 115 to minimize memory latency and also has a write collection buffer 111 for non-cached data streams intended for the graphics and audio processor 114. The write collection buffer 111 maximizes bus utilization by collecting partial cache lines into complete cache lines and sending data one cache line at a time to the graphics and audio processor 114.

The command processor 200 receives and parses the display commands from the main processor 110 (any additional data needed to process them comes from the shared memory 112). The command processor 200 processes the stream of vertex commands in 2D and / or
Or feed the graphics pipeline 180 for 3D processing and rendering. The graphics pipeline 180 generates an image based on these commands. The resulting image information may be transferred to main memory 112 for access by display controller / video interface unit 164 (displaying the frame buffer output of pipeline 180 on display 102).

FIG. 5 illustrates the graphics processor 154.
FIG. The main processor 110 uses the graphics command stream 210, the display list 2
12, and the vertex array 214 may be stored in the main memory 112 and a pointer may be passed to the command processor 200 via the bus interface 150. The main processor 110 stores graphics commands in one or more graphics first in first out (FIFO) buffers 210 allocated in the main memory 110. The command processor 200 includes: A command stream from the main memory 112 via an on-chip FIFO memory buffer 216 that receives and buffers graphics commands for synchronization / flow control and load balancing, an on-chip call FIFO memory buffer 218. Display list 212 from main memory 112, and via vertex cache 220, from the command stream and / or vertex array 2 in main memory 112.
Take in the vertex attributes from 14).

The command processor 200 performs a command processing operation 200a that converts the attribute type to floating point format and passes the resulting complete vertex polygon data to the graphics pipeline 180 for rendering / rasterization. Programmable memory arbitration circuit 130 (see FIG. 4) provides access to shared main memory 112 to graphics pipeline 1
80, command processor 200, and display controller / video interface unit 164
Arbitrate between.

FIG. 4 illustrates the graphics pipeline 18
Indicates that 0 can include: Conversion unit 300 setup / rasterizer 400 texture unit 500 texture environment unit 600, and pixel engine 700

The conversion unit 300 performs various 2D and 3D conversions and other operations 300a (see FIG. 5). The transformation unit 300 may have one or more matrix memories 300b for storing the matrices used in the transformation process 300a. The conversion unit 300 is
The received graphic is converted from the object space to the screen space for each vertex, and the received texture coordinates are converted to generate projected texture coordinates (300c). The conversion unit 300 uses polygon clipping / thinning 3
00d. Lighting process 300e, also performed by transform unit 300b, provides per-vertex lighting operations for up to eight independent lights in one embodiment. Transform unit 300 may also perform texture coordinate generation (300c) for embossed style bump mapping effects. The transform unit 300 also performs depth (Z-value) compression and clamping, as described in more detail below in this specification.

The setup / rasterizer 400 receives the vertex data from the transformation unit 300 and sends the triangle setup information to one or more rasterizer units (400b) which perform boundary rasterization, texture coordinate rasterization and color rasterization. Have.

The texture unit 500 (which may include an on-chip texture memory (TMEM 502)) performs various processing related to texturing. This includes, for example: -Retrieving texture 504 from main memory 112-For example, multi-texturing, post-cache texture decompression, texture filtering, embossing, shadows and shades through the use of projected textures, and alpha transparency and Texture processing including BLIT with depth (500a), bump mapping, pseudo texture, and bump map processing for calculation of texture coordinate displacement for texture tiling effect (500b), and indirect texture processing (500c) included.

Texture unit 500 performs texture processing using both normal (non-indirect) and indirect texture lookup operations. For a more detailed description of exemplary graphics pipeline circuits and procedures for performing normal and indirect texture lookup operations, see "Method And Apparatus Attributes Fo.
r Direct And Indirect Tex
true Processing In A Grap
co-pending patent application Serial No. assigned to the same assignee under the name "Hics Systems". 09 /
722, 382 (Patent Attorney's reception number 723-961), and its corresponding provisional application serial number No. related to the application dated August 23, 2000. 60 / 226,891. Both of these are incorporated herein by reference.

Texture unit 500 outputs the filtered texture values to texture environment unit 600 for texture environment processing (600a). The texture environment unit 600 blends polygons and texture colors / alpha / depth, and
Texture fog processing (600b) to achieve the reverse range type fog effect may be performed. Texture environment unit 600 may provide multiple stages for performing various other interesting environment-related functions based on, for example, color / alpha modulation, embossing, detailed texturing, texture swapping, clamping, and depth blending. . Texture environment unit 600 can also combine (eg, subtract) textures in hardware in a single pass. For more details on the texture environment unit 600, see “Re
circulating Shade Tree Bl
ender for a Graphics System
application serial No. assigned to the same assignee with the name "em". 09/722, 367 (patent attorney reception number 72)
3-968) and its corresponding provisional application serial no. 60 / 226,888
checking ... Both of these are incorporated herein by reference.

The pixel engine 700 has a depth (z)
Comparison (700a) and pixel blending (70
0b). In this example, the pixel engine 700
Stores the data in the embedded (on-chip) frame buffer memory 702. Graphics pipeline 180 may include one or more embedded Ds for storing frame buffer and / or texture information locally.
A RAM memory 702 may be included. z comparison 700a '
Also, depending on the rendering mode currently in effect, it may occur earlier in the graphics pipeline 180 (eg, z-comparison may occur earlier if alpha blending is not needed). The pixel engine 700 includes an on-chip frame buffer 702 and a display / video interface unit 164.
A copy operation 700c that periodically writes to the main memory 112 for access by the. This copy operation 7
00c may also be used to copy the contents of the embedded frame buffer 702 to a texture in main memory 112 to obtain a dynamic texture compositing effect.

In this example graphics system,
Antialiasing and other filtering can also be done during the copyout operation. For more information on anti-aliasing, see “Method And Apparatus For For.
Anti-Aliasing In A Graph
2000, with the name "ics System"
Provisional application No. related to the application dated March 23. 60/226, 9
00 and its corresponding utility patent application Nos. 09 / 726,226 (patent attorney reception number 723-964). Both of these are incorporated herein by reference.

The frame buffer output of graphics pipeline 180 (finally stored in main memory 112) is read by display / video interface unit 164 for each frame. Display controller / video interface unit 164 provides digital RGB pixel values for display on display 102.

Example of Z-Clamping Configuration A Z-clamping configuration is used by clamping the Z value of pixels within a predetermined range in front of the viewpoint / camera (viewport) plane where Z = 0 to zero. Improves the accuracy of visually significant Z-axis (depth) attributes of rendered scene elements. FIG. 6 shows an example of the Z-value clamping arrangement of the present invention as viewed in screen space. The Z clipping plane 201 "znear" is defined very close to the Z = 0 viewpoint / camera plane 202 to prevent unwanted visual artifacts that occur when an object is rendered too close to the viewpoint / camera plane. To avoid. Clamping plane 203 "znear2"
Is set such that znear2 lies in the Z plane equal to znear * (1 << n), where n is zne
An integer that effectively determines the Z resolution of the scene by setting the position of the ar2 plane relative to the zneare plane. Also, the far clipping plane 204 "z
far "is set to the Z plane far from the Z = 0 plane.
Z-buffering is done for all pixels in the range between the zneare2 plane and the Z-far clipping plane. Any pixel lying in the range between the znear and znear2 planes has its Z value clamped to, for example, zero (or the minimum Z value, such as the Z value of the znear2 clamping surface), and z <znear. For all pixels, the normal (norma)
l) Clipping is performed.

FIG. 7 shows a flow chart of an example set of summary processing steps 301 for obtaining improved Z accuracy when performing Z buffering in a graphics processing system. The "Z" depth value is either generally computed as a polygon vertex attribute or provided to the graphics rendering system, as shown in block 302. In the Z-clamping method of the present invention, the clipping plane "znear" is set to the Z-axis plane very close to the Z = 0 plane and another clipping plane "zfar" is set to Z = 0, as shown in block 304.
The Z-axis position is set far from the plane. Also, as indicated by block 306, the clamping plane "znear
2 ”is Z = znear2 = znear * (1 << n)
Is set to lie in the Z-axis plane, where n
Is an integer that effectively determines the Z resolution of the scene by setting the position of the znear2 plane relative to the znear plane (ie, znear2
The further away the plane is from the zneare plane, the greater the Z buffering resolution obtained for portions of the rendered scene farther from the camera / view plane than the zneare2 plane). As shown in block 308, normal Z buffering is performed for all pixels with Z values where znear2 <Z <zfar. As shown in block 310, z
with a Z value equal to or between the near and znear2 clamping surfaces (ie zneaar ≤
For Z ≦ znear2) pixels, the Z value is clamped (eg, to zero or the smallest value such as the value in the znear2 plane) and the corresponding pixels are written to the frame buffer in order from first to last. As shown in block 312, conventional geometry clipping is performed on pixels where Z <znear. In this graphics pipeline embodiment, most of the steps of FIG. 7 are performed by clipping logic and expanded Z compression logic in transform unit 300, as described in the hardware embodiments below.

Hardware Implementation In the example graphics pipeline 180, the transform unit 300 includes a clipping plane logic circuit and a Z plane.
It has both compression logic circuits. Since processing anti-aliased pixels requires storing more data in a Z buffer of limited size (ie, embedded frame buffer 702), Z value compression in this embodiment is less than full scene anti-aliasing. Only done when allowed. Such Z compression circuits typically operate to compress the calculated 24-bit Z attribute value into a 16-bit value. FIG. 8 shows an example hardware logic circuit that can be used to obtain Z compression without any Z value clamping. This example Z-compression circuit essentially comprises a priority encoder 320 and a shifter 322 for compressing the four 24-bit Z-values and converting them into 16-bit values.

In this graphics pipeline 180 embodiment, the compression algorithm performs a type of inverse floating point encoding. While conventional floating point notation clamps most of the resolution towards the bottom of the numerical scale, the nature of screen space Z requires that most of the resolution be provided at the top of the numerical scale. To achieve this, three compression schemes are used. The choice of three schemes is made based on the particular near-to-far ratio used in the rendered scene. For example, when using orthographic or small far-to-near ratios, a direct linear compression mapping is used such that the lower 8 bits are simply removed from the input Z value. Moderate distance-pair-
For near ratios, floating point conversion to 16 bits using 14e2 notation is used to represent 24-bit Z values. This form of compression results in an effective 15-bit resolution bit in the near plane and a 17-bit resolution in the far plane. 13e for high far-to-near ratios
A 24-bit Z value is represented using floating point conversion to 16 bits using 3 notation. This gives an effective resolution of 14 bits in the near plane and 20 bits in the far plane.

One direct and simple embodiment of the floating point conversion approach to compression described above is to select an exponent and a shift value, shift the input value by the shift value, and place this exponent in the higher order bit positions. Including adding. In this example, as shown in the table below,
The exponent and shift value are selected by detecting a particular value range that includes the upper bits of the input Z value. 1
In case of 4e2 notation compression

[Table 1] 13e3 notation compression

[Table 2]

In this example, the transform unit 300 uses conventional hardware clipping circuitry to programmably set and provide the Z near clipping plane and the Z far clipping plane (as well as the appropriate X and Y axis clipping planes). Good. Achieves Z clamping configuration and Z
In order to set the clamping plane as described above, the conversion unit 300 uses the extended Z compression logic circuit shown in FIG. In addition to Z-value compression, this circuit is available before implementing one of the two floating point transform compression schemes described above.
Perform one or more left shifts from the most significant bit of the input Z value. As shown in FIG. 9, this extended circuit configuration includes a priority encoder 320, a 4-bit (or less) adder 324 and a shifter 324, and an AND gate (not shown) for masking the most significant Z value bit. To use. The left shift of the precompressed input Z value is the programmable adder 3
24, where n represents the number of left shifts to be performed.

Other Compatible Embodiments Some of the system elements 50 described above may be implemented other than the home video game console configurations described above. For example, a graphics application or other software written for system 50
The system 50 can be emulated or otherwise run on platforms with different compatible configurations. If the other platform can successfully emulate, simulate and / or provide some or all of the hardware and software resources of system 50, the other platform can successfully execute the software. .

As an example, the emulator is the system 5
There may be different hardware and / or software configurations (platforms) than the zero hardware and / or software configurations (platforms). This emulator system consists of system hardware and / or application software
Or it may have software and / or hardware elements that emulate or simulate some or all of the software elements. For example, the emulator system may comprise a general purpose digital computer such as a personal computer running a software emulator program that simulates the hardware and / or firmware of system 50.

Some general purpose digital computers (eg, IBM or Macintosh personal computers and compatibles) currently provide 3D graphics pipelines that are compatible with DirectX or other standard 3D graphics command APIs.
Has a graphics card. It may also have a stereo sound card that provides high quality stereo sound based on a standard set of voice commands. A personal computer equipped with such multimedia-hardware, if running emulator software, may have sufficient capabilities to match the graphics and sound capabilities of system 50. The emulator software processes the home video game console platform on which the game programmer wrote the game software, 3D graphics, audio,
Control hardware resources on a personal computer platform to simulate peripherals and other functions.

FIG. 10 shows the host platform 120.
1, an emulator element 1303, and an overall example of an emulation process using a game software executable binary image stored on a storage medium 62. Host 12
01 may be a general or special purpose digital computing device, such as a personal computer, video game console, or any other platform with sufficient computing power. The emulator 1303 runs on the host platform 1201 and stores the storage medium 6
Software and / or hardware that provides real-time conversion of commands, data, and other information from two to a form processed by the host. For example, emulator 1303 captures “source” binary image program instructions that are intended to be executed by system 50 from storage medium 62 and may execute these other program instructions by host 1201 or other processing. Convert to format.

As an example, the software may be IBM P
is written to run on a platform using a powerPC or other specific processor,
If the host 1201 is a personal computer using a different (eg, Intel) processor, the emulator 1303 fetches one or a series of binary image program instructions from the storage medium 62 and one or more of these program instructions. Converted to the equivalent Intel binary image program instruction. The emulator 1303 also
Hardware and / or software graphics that captures and / or generates graphics and voice commands intended to be processed by the graphics and voice processor 114, and these commands are available on the host 1201. And to a format or formats that can be processed by the audio processing resource. As an example,
Emulator 1303 may translate these commands into commands that may be processed by the particular graphics and / or audio hardware of host 1201 (eg, using standard DirectX, OpenGL, and / or audio APIs). .

An emulator 1 used to provide some or all of the features of the video game system described above.
The 303 may also be equipped with a graphics user interface (GUI) that simplifies or automates the selection of various options and screen modes for games run using the emulator. In one example, such emulator 1303 may also include more sophisticated functionality as compared to the host platform for which the software was originally intended. If the particular graphics support hardware in the emulator does not include the z neighborhood processing features shown in FIGS. 7, 8 and 9, the emulator designer may: You have the option of providing the rendered image with near image artifacts by implementing the neighborhood processing function in software, or by "stubping" (ie, ignoring) the z neighborhood processing.

The flowchart of FIG. 6 may be implemented entirely in software, entirely in hardware, or a combination of hardware and software, although in the preferred embodiment, higher speeds are used. Most of these calculations are done in hardware for performance and other benefits. However, in other embodiments (eg, where a very fast processor is available), the operations and steps of FIG. 6 may be implemented in software to provide similar or identical image results.

FIG. 11 illustrates an emulation host system 12 suitable for use with emulator 1302.
Indicates 01. The system 1201 includes a processing unit 120.
3 and system memory 1205. A system bus 1207 connects various system elements, including system memory 1205, to processing unit 1203. The system bus 1207 may be any of several types of bus structures including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures. System memory 120
7 has a read only memory (ROM) 1252 and a random access memory (RAM) 1254.
A basic input / output system (BI) containing the basic routines that help to transfer information between elements within personal computer system 1201 (eg, during start-up).
OS) 1256 is stored in the ROM 1252.
System 1201 further includes various drives and associated computer-readable media. Hard disk drive 1209 reads from and writes to (typically fixed) magnetic hard disk 1211. An additional (possible option) magnetic disk drive 1213 reads from and writes to a removable "floppy" or other magnetic disk 1215. The optical disk drive 1217 reads from a removable optical disk 1219 such as a CD ROM or other optical media,
Also, write to this in some configurations. The hard disk drive 1209 and the optical disk drive 1217 are connected to the system bus 1207 by a hard disk drive interface 1221 and an optical drive interface 1225, respectively. The drive and its corresponding computer-readable medium non-volatilely store computer-readable instructions, data structures, program modules, game programs and other data for the personal computer system 1201. In other configurations, other types of computer-readable media capable of storing computer-accessible data, such as magnetic cassettes, flash memory cards,
Digital video disc, Bernoulli
li) cartridge, random access memory (RA
M) Read only memory (ROM) and the like may also be used.

A plurality of program modules including the emulator 1303 includes a hard disk 1211, a removable magnetic disk 1215, an optical disk 1219, and / or a ROM 1252 and / or a system memory 1205.
Alternatively, it may be stored on the RAM 1254. Such a program module is a graphics and audio AP.
It may include an operating system that provides I, one or more application programs, other program modules, program data, and game data. A user may input commands and information to the personal computer system 1201 via input devices such as a keyboard 1227, pointing device 1229, microphone, joystick, game controller, satellite dish, scanner, and the like. These and other input devices may be connected to the processing unit 1203 via a serial port interface 1231 connected to the system bus 1207, such as a parallel port, game port firewire bus or universal serial bus (USB). May be connected by other interfaces. In addition, the monitor 123
3 or other type of display device is connected to the system bus 1207 via an interface such as a video adapter 1235.

System 1201 may include a modem 1154 or other network interface means for establishing communications over network 1152, such as the Internet. Modem 1 which can be internal or external
154 is connected to the system bus 123 via the serial port interface 1231. Also, a network interface 1156 may be provided (or such communication may be provided to allow the system 1201 to communicate with a remote computing device 1150 (eg, another system 1201) via a local area network 1158. , Via wide area network 1152 or other communication path such as dial-up or other communication means). System 1201 may typically have other peripheral output devices, such as printers and other standard peripheral devices.

In one example, video adapter 1235.
Is a fast 3D in response to 3D graphics commands issued based on standard 3D graphics application programmer interfaces such as Microsoft's DirectX 7.0 or other versions.
It may have a 3D graphics pipeline chipset that provides graphics rendering. Further, since a pair of stereo speakers 1237 are connected to the system bus 1207 via a sound generation interface such as a conventional “sound card”, the bus 1
Provides hardware and embedded software support for producing high quality stereo audio based on the audio commands provided by 207. These hardware capabilities are provided by the system 1201 in the storage medium 62.
Allows you to provide sufficient graphics and sound speed capabilities to play the software stored in.

All references referred to above are incorporated herein by reference.

While the present invention has been described above with respect to what is determined to be the most practical and preferred embodiment at the present time, the present invention should not be limited to the disclosed embodiment. On the contrary, various modifications and equivalents shall be made within the scope of the appended claims.

[Brief description of drawings]

FIG. 1 is a general diagram of an example of an interactive computer graphics system.

2 is a block diagram of the example computer graphics system of FIG.

3 is a block diagram of the example graphics and audio processor shown in FIG. 2. FIG.

4 is a block diagram of the example 3D graphics processor shown in FIG. 3. FIG.

5 is an example logic flow diagram of the graphics and audio processor of FIG.

FIG. 6 is a flowchart showing example steps for implementing Z clamping in the Z neighborhood according to the present invention.

FIG. 7 is a diagram showing a screen space of a Z vicinity clamping configuration according to the present invention.

FIG. 8 is an example of a hardware logic diagram for implementing Z compression in a graphics pipeline embodiment of the present invention.

FIG. 9 is a hardware logic diagram for realizing an example of a Z-nearest neighbor clamping configuration in the graphics pipeline embodiment of the present invention.

FIG. 10 illustrates another compatible embodiment.

FIG. 11 shows another compatible embodiment.

Claims (7)

[Claims] 1. A method for Z-buffering in a 3D graphics rendering system, wherein a first clipping plane znear is set to a Z-axis position very close to a Z = 0 plane and a second clipping plane zfar is set.
Is set to a Z-axis position that is very far from the Z = 0 plane, and z-value clamping surface znear2 is znea2 = zn.
set to ear * (1 << n), perform conventional Z-buffering on pixels with z-values where zneare <z <zfar, and set Z-values for pixels with zneare2 <Z <zfar And writing the corresponding pixel data to the display frame buffer in a first-to-last order. 2. The graphics system of claim 1, wherein the predetermined value for clamped Z values is zero. 3. An improvement in a 3D graphics rendering system having a processor and a separate graphics processing pipeline having transformation and lighting circuitry and performing z-value compression operations during rendering of anti-aliased scenes. An adder and a bit masking circuit included in the graphics pipeline Z-value compression circuit, the adder being connected between the priority encoder and the shifter and having a Z-value of 2 before the Z-value compression operation. An improvement used to effectively clamp Z values within a given range of Z values to a given Z value by shifting the value data to the left by a given number of bit positions. 4. The predetermined Z value is zero.
Graphics system described in. 5. The predetermined range of the Z value is defined by a predetermined Z axis position very close to the Z = 0 plane.
Clipping planes znear and znear2 = zn
Z clamping plane zn defined in ear * (1 << n), where n is equal to the number of bit positions left shifted
The graphics system of claim 3, as determined by ear2. 6. A 3D graphics rendering system having a processor and a separate graphics processing pipeline that performs full scene anti-aliasing with Z value compression for avoiding pixel clipping near the Z = 0 plane. Shifting the binary Z-value data to the left by one or more bit positions prior to performing the Z-value compression, wherein the amount of left shift is to clamp the Z-value to a predetermined value. A method determined by a predetermined range of Z values to be performed. 7. A hardware implementation in a graphics processing system for rendering and displaying an image in at least partial response to polygon vertex attribute data including Z-value binary data stored in an associated memory. And a Z-value compression processing unit, which is connected between the priority encoder, the shifter, and the priority encoder and the shifter, and converts the Z-value binary data into a predetermined number of bit positions before compression. A Z value compression processor, which can be used to effectively clamp a Z value within a predetermined range of Z values to a predetermined Z value by shifting the Z value to the left.