JP2003051557A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fine nonvolatile semiconductor storage device wherein cutoff characteristic of a transistor is improved, and to provide its manufacturing method. SOLUTION: This nonvolatile semiconductor storage device is provided with a semiconductor substrate 10; element regions formed in the semiconductor substrate, element isolation regions for isolating the element regions in the semiconductor substrate; a plurality of memory cell gates 1 which are formed in the element regions, have the same gate length, and are isolated from each other by isolation distance equal to the gate length; and two selection gates 2 which are adjacent to the memory cell gates at the isolation distance, isolated from each other by the isolation distance, and formed having the gate length.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a fine non-volatile semiconductor memory device having a transistor in which a channel region is implanted with impurities.

[0002]

2. Description of the Related Art Conventionally, as a nonvolatile semiconductor memory device, for example, EEP for electrically writing / erasing data
ROM (Electrically Erasable Programmable Read-On
ly Memory) is known. In this EEPROM,
Particularly in the case of the NAND type, memory cells are arranged at intersections of row lines and column lines intersecting with each other to form a memory cell array. A MOS transistor having a stacked gate structure in which a floating gate and a control gate are stacked is usually used for the memory cell.

In the EEPROM, there is a flash memory that can be electrically erased collectively. As a flash memory, a NAND flash memory with high integration is widely used.

A typical memory cell of a NAND flash memory is, for example, “R. Shirota,“ A Review of 256Mb
it NAND Flash Memories and NAND Flash Future Tren
d, Non-Volatile Semiconductor Memory Workshop (= NVS
MW) (2000) ”pp 22-31”. Therefore, a planar structure of the memory cell unit is shown in FIG. As shown in FIG. 20, it has a NAND type structure in which memory cell select transistors are arranged on both sides of a plurality of memory cell transistors connected in series.

As shown in FIG. 20, a plurality of memory cell gates 50 are linearly formed in parallel with each other.
1 is provided at each end of the plurality of memory cell gates.
Book select gates 51 are linearly formed parallel to each other and parallel to the memory cell gates 50. Here, the plurality of memory cell gates have the same gate length W3. The pair of select gates 51 have the same gate length W4, and the gate length W4 is formed to be twice the gate length W3 of the memory cell gate 50.

Spaces F having the same width (F is a minimum processing size) are provided between the memory cell gates 50. This space F is equal to the gate length W3 of the memory cell gate 50. Further, a memory cell gate 1 is provided between the select gate and the memory cell gate adjacent to the select gate.
The same space F as the space F between them is provided.

Element active regions 52 are formed in parallel with each other in a direction orthogonal to the memory cell gate 50. The element active region 52 is a plurality of element isolation regions 53 formed in parallel with each other in a direction orthogonal to the memory cell gate 50.
It has been divided into multiple parts.

Here, a pair of one select gate 51 is formed at both ends of a plurality of, for example, 16 memory cell gates 50 to form one NAND string 54.
Another NAND string 54 is formed at the end of the NAND string 54 with a space about 2F which is about twice as large as the space F provided between the memory cell gates 50. Here, a contact 55 is formed on the element active region 52 between the select gates 51 of the NAND strings 54 adjacent to each other.

As described above, the gate lengths are all constant lines and spaces in the memory cell unit, and are arranged at the same pitch. Further, the channel length of the select gate is miniaturized to the same size as the memory cell gate. Two adjacent gates of the select gate function as a select transistor.

Here, in the conventional nonvolatile semiconductor memory device having a planar structure shown in FIG. 20, the selection gate length itself is about 2F, and since there is one on the source side and one on the drain side, it becomes about 4F. The distance from the select gate of another adjacent memory cell unit is about 2F, which is about 6 in total.
It is F.

FIG. 21 shows a cross section taken along the line EF in FIG. As shown in FIG. 21, the memory cell gate 50 and the select gate 51 are provided on the semiconductor substrate 58. A source / drain diffusion layer 59 is provided in the semiconductor substrate 58 around the memory cell gate 50 and the selection gate 51. A channel ion implantation layer 60 is formed in the semiconductor substrate 58 below the memory cell gate 50 and the selection gate 51. Also, N
Select gate 51 provided at the end of AND string 54
Contact 5 to the source / drain diffusion layer 59 outside the
5 is connected.

Each memory cell gate 50 and select gate 5
1 is on the semiconductor substrate 58 via the gate insulating film 63,
A first conductive layer 64 that serves as a floating gate that is a charge storage layer is formed. A second conductive layer 66 that serves as a control gate is formed on the first conductive layer 64 via an inter-gate insulating film 65. The inter-gate insulating film 65 is composed of, for example, an ONO (Oxide-Nitride-Oxide) film which is a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film.

As described above, the select gate is generally longer than the gate length of the memory cell transistor and ensures the deterioration of the cutoff characteristic of the transistor due to the short channel effect.

Here, the nonvolatile semiconductor memory device having the sectional structure shown in FIG. 21 has the circuit configuration as shown in the circuit diagram of FIG.

As shown in FIG. 22, in the memory cell unit of the NAND flash memory, a plurality of memory blocks 70 forming the area surrounded by the broken line are formed.
For example, 16 memory cell transistors M0 to M15 are connected in series, one drain side selection transistor SG1 is connected to one side thereof, and one source side selection transistor SG2 is connected to the other side thereof.

A plurality of memory cells are connected in series to form a NAND cell (memory cell unit) which is one memory cell array. The source and drain of each memory cell are connected in series with each other via a diffusion layer region provided on the element region.

Word lines WL0 to WL15 are connected to the gates of the memory cell transistors M0 to M15 in a one-to-one relationship. Drain side selection transistor SG
A select gate line SGD is connected to the gate of 11. A select gate line SGS is connected to the gate of the source side select transistor SG2.

The source of the drain side select transistor SG1 is connected to the bit line DQ which is a data line.
The source of the source side select transistor SG2 is connected to the common source line CS.

Although not shown, a plurality of NAND strings 70 are connected in the direction in which the data lines extend. A plurality of NAND strings 70 having the same circuit configuration are provided for each bit line in the extending direction of the word line.

The NAND strings 70 are serially connected in series, contacts are provided at the ends of the NAND strings, and a plurality of memory cell transistors are connected via the select transistors at both ends.

Further, an AND type flash memory as shown in the circuit diagram of the memory cell unit in FIG. 23 is also used. Even in this case, the memory cell transistor constitutes a non-volatile memory cell array composed of one or more transistors having a structure having a floating gate which is a charge storage layer.

That is, as shown in FIG. 23, AND
In the memory cell unit of the type flash memory, a plurality of memory cell transistors M0 to M0, for example, 16 forming a memory block 71 indicated by a region surrounded by a broken line are formed.
M15 is connected in parallel, and one drain side selection transistor SG1 is connected to one side of the M15 and one source side selection transistor SG2 is connected to the other side thereof.

A plurality of memory cells are connected in series to form an AND cell (memory cell unit) which is one memory cell array. The source and drain of each memory cell are connected in parallel to each other via a diffusion layer region provided on the element region.

Word lines WL0 to WL15 are connected to the gates of the memory cell transistors M0 to M15 in a one-to-one relationship. Drain side selection transistor SG
The select gate line SG is connected to the first gate.
A select gate line SGS is connected to the gate of the source side select transistor SG2.

The source of the drain side select transistor SG1 is connected to the bit line DQ which is a data line.
The source of the source side selection transistor SG2 is connected to the source line CS.

Although not shown, a plurality of memory blocks 71 are connected in the direction in which the data lines extend. A plurality of similar memory blocks are provided for each bit line in the extending direction of the word line.

Here, in Japanese Unexamined Patent Publication No. 59-74677, in FIGS. 4 to 11 thereof, etc., in the field,
A technique is disclosed in which an opening is provided in an interlayer oxide film between a floating gate and a control gate of a peripheral transistor portion to improve the degree of freedom of wiring.

Further, in Japanese Unexamined Patent Publication No. 2000-188384, a select gate cell having the same structure as the memory cell is provided, and all word lines including the select gate have the same spacing, which is close to miniaturization. A structure of an EEPROM having high dimensional controllability that is not affected by the effect is described. Further, the publication describes that not only one select gate cell is necessarily arranged on the bit line and source line sides, but also a plurality of select gate cells may be arranged respectively.

[0029]

The conventional semiconductor device as described above has the following problems.

As a result, the NAND string has irregular lines / spaces in the portion of the select gate,
This will lead to a reduction in the processing margin at the time of patterning by lithography as fine processing advances. When designed with an irregular pattern, miniaturization may be limited.

That is, when the minimum line width based on the limit of the fine processing technology is F, the gate length of the memory cell transistor, the gate interval of the memory cell transistor, and the interval between the gate of the memory cell transistor and the gate of the select transistor are all. Formed with F. However, the gate width of the select transistor is formed at about 2F in order to improve the cutoff characteristic, and as a result, irregular line widths and space widths exist.

That is, in the memory cell gate, if the line / space is 1F, and in the case of the select gate, the line / space has a gate length of about 2F, the gate length of the memory cell gate adjacent to the select gate is manufactured. In the process, excessive etching is performed during lithography and the film is not formed to have a desired length, so that the necessary characteristics cannot be obtained. Therefore, the minimum line width F
All the gate lengths must be designed with a larger value, resulting in an increase in the area of the memory cell transistor region.

An object of the present invention is to solve the above problems of the prior art.

A particular object of the present invention is to provide a fine non-volatile semiconductor memory device having improved transistor cutoff characteristics.

[0035]

To achieve the above object, the present invention is characterized by a semiconductor substrate, an element region formed in the semiconductor substrate, and an element for separating the element region in the semiconductor substrate. The isolation region and a plurality of memory cell gates formed in the element region, each having an equal gate length and having a spacing distance equal to the gate length, and the spacing distance between the memory cell gate. Adjacent to each other, each separated by the separation distance,
A non-volatile semiconductor memory device comprising two select gates each having the gate length.

Another feature of the present invention is that a plurality of memory cell gates connected in series, each having an equal gate length and arranged at a distance equal to the gate length, and a plurality of memory cell gates. The memory cell gate has the same gate length connected to one of the source side or drain side end of the cell gate, and is separated from the memory cell gate by a distance equal to the distance. 2 spaced apart by an equal distance
One first select gate group and a gate length equal to the memory cell gate connected to one of the source side or drain side ends of the plurality of memory cell gates, and the separation distance from the memory cell gate. Is a non-volatile semiconductor memory device having at least one second selection gate group arranged with a separation distance equal to.

Another feature of the present invention is that a plurality of first memory cells connected in series, each having an equal first gate length, and having a first distance apart from each other equal to the first gate length. A gate and a first gate length equal to the plurality of first memory cell gates connected to one of source-side or drain-side ends of the plurality of first memory cell gates, respectively, Two first select gate groups arranged at a first separation distance and separated from the plurality of first memory cell gates by the first separation distance;
A plurality of first memory cell gates having a first gate length equal to the plurality of first memory cell gates connected to one of source-side and drain-side ends of the plurality of first memory cell gates; At least one second selection gate group arranged at a first distance from the cell gate, and a plurality of first memory cells arranged at a second distance from the second selection gate group. At least one third select gate group having a first gate length equal to the gate;
The third selection gate group is arranged at a second separation distance equal to the first separation distance and connected in series, and each has a second gate length equal to the first gate length. A plurality of second memory cell gates that are arranged with a second separation distance that is equal to the plurality of second memory cell gates, and the plurality of second memory cell gates that are connected to one of the source-side or drain-side ends of the plurality of second memory cell gates. A nonvolatile memory having two fourth selection gate groups each having a second gate length and being separated from each other by the second separation distance and separated from the plurality of second memory cell gates by the second separation distance. Semiconductor memory device.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 2 shows a plan configuration of a memory cell unit of a NAND type nonvolatile semiconductor memory device according to the present embodiment. As shown in FIG. 2, a plurality of memory cell gates 1 are linearly formed in parallel with each other. Two select gates 2 are arranged in parallel with each other at both ends of the plurality of memory cell gates.
It is formed linearly in parallel with the memory cell gate 1.
Here, the plurality of memory cell gates have the same gate length W1. Note that the plurality of memory cell gates can be configured by the number of 8 or 16, etc. The pair of two select gates 2 have the same gate length W2, and the gate length W2 is formed to be equal to the gate length W1 of the memory cell gate 1.

Spaces F having the same width (F is a minimum processing dimension) are provided between the memory cell gates 1.
This space F is the gate length W1 of the memory cell gate 1.
And equal to the gate length W2 of the select gate 2. Further, a space F which is the same as the space F between the memory cell gates 1 is provided between the select gate and the memory cell gate adjacent to the select gate.

Element active regions 3 are formed in parallel with each other in a direction orthogonal to the memory cell gate 1. The element active region 3 is formed by a plurality of element isolation regions 4 formed in parallel to each other in a direction orthogonal to the memory cell gate 1.
It is divided into multiple pieces.

Here, a pair of two select gates 2 are formed at both ends of a plurality of, for example, 16 memory cell gates 1 to form one NAND string 5. This N
At the end of the AND string 5, a space F which is the same as the space F between the memory cell gates 1 is placed, and another NAND string 5 is formed. Here, a contact 6 is formed on the element active region 3 between the select gates 2 of the NAND strings 5 adjacent to each other.

As described above, the gate lengths are all constant line and space in the memory cell unit and are arranged at the same pitch. Further, the channel length of the select gate is miniaturized to the same size as the memory cell gate. Two adjacent gates of the select gate function as a select transistor.

A cross section taken along the line AB in FIG. 2 is shown in FIG. As shown in FIG. 1, a memory cell gate 1 and a select gate 2 are provided on a semiconductor substrate 10. A source / drain diffusion layer 11 is provided in the semiconductor substrate 10 around the memory cell gate 1 and the select gate 2. A channel ion implantation layer 12 is formed in the semiconductor substrate 10 below the memory cell gate 1 and the selection gate 2. Also, NAND string 5
Source / drain diffusion layer 1 outside the select gate 2 at the edge of
A contact 6 is connected to 1.

Each memory cell gate 1 and select gate 2
On the semiconductor substrate 10, a first conductive layer 14 serving as a floating gate that is a charge storage layer is formed via a gate insulating film 13. A second conductive layer 16 serving as a control gate is formed on the first conductive layer 14 with an inter-gate insulating film 15 interposed therebetween. The inter-gate insulating film 15 is composed of, for example, a silicon oxide film, a silicon nitride film, and an ONO film which is a laminated film of a silicon oxide film.

Here, in the select gate 2, the presence of the inter-gate insulating film 15 gives a potential only to the lower charge storage layer 14, and the upper control gate 16 remains insulated.

Unlike the memory cell gate 1, the select gate 2 has a potential applied only to the first conductive layer. In this case, the first conductive layer 14 is drawn out on the element isolation region and a potential is applied independently of the second conductive layer 16.

By using a pair of two select gates at both ends of each NAND string, 3F is required for the select gate region. That is, since the selection gate has two gate lengths of F, 2F is occupied as the gate length, the distance between the two gates is F, and a total of 3F is required.

Accordingly, the distance between the select gates is also F, and if the gate length of the select gate in the conventional method is 2F, it is 6F in the conventional method, but the nonvolatile semiconductor memory device of the present embodiment. Then, the chip area is slightly increased to 7F, but the processing margin can be improved by that amount. Therefore, if the ground rule can be miniaturized to the extent that it is canceled, there is a merit in sufficiently reducing the chip area.

That is, in the nonvolatile semiconductor memory device of the present embodiment, the distance between the select gates is F, the two select gates are 2F, and the distance F between the select gates is added to 2F, and 3F is the source side and the drain side. Therefore, it is 6F, and F between other memory cell units is added to obtain 7F.

In this way, the select gate has the same pitch and gate length as the memory cell gate, and as a result, the length of the memory cell unit other than the memory cell portion is 6F to 7F.
Even if it is expanded to, if the F itself can be made small enough to compensate for this increase, the miniaturization of the memory cell unit can be realized in total.

For example, in the conventional irregular pattern, F is 0.
When F can be miniaturized to 0.09 μm when this embodiment is applied while miniaturization can be performed only to 1 μm, 0.6 in the related art, which is the product of 6 and 0.1, is the memory cell unit of the memory cell unit. Other than length. On the other hand, in the nonvolatile semiconductor memory device of the present embodiment, the product of 7 and 0.09 is 0.63, and if F can be further miniaturized, the area of the present embodiment can be reduced.

Further, in the conventional nonvolatile semiconductor memory device, N
In the AND string, if the distance between the select gate and the memory cell gate is F, the margin for patterning an irregular pattern is reduced, but all are arranged at the same pitch as in the nonvolatile semiconductor memory device of the present embodiment. If so, there is no need to worry about a local decrease in the lithography margin.

Here, the two select gates formed adjacent to each other can be controlled by the same signal line. Also, depending on the case, it is possible to
It is also possible to individually control the select gates of the book and change the cutoff characteristics of each select gate. In this case, a control circuit is provided to control each select gate.

In some cases, the number of source side select gates in the NAND string may be one, and the number of drain side select gates may be two.
In this case, even if the leak occurs on the source side, it is sufficient if the leak is within the allowable range.

Further, in some cases, the source side select gate in the NAND string may have two gates, and the drain side select transistor may have one gate. In this case, even if the leak occurs on the drain side, it is sufficient that the leak is within the allowable range.

As described above, all the gate patterns of the memory cells are set to a common line and space, and the select gate portion has the same gate length as that of the memory cells to secure a margin. Can be improved.

The number of select gates adjacent to the source side and the drain side of the memory cell gate in one memory cell unit may be three or more, respectively. However, the lengths of the respective selection gates and the distances between the respective selection gates are all equal to the distance between the memory cell gates and the memory cell gate length. In consideration of the increase in area, it is preferable to provide two select gates on each of the source side and the drain side in one memory cell unit.

As described above, in the nonvolatile semiconductor memory device of the present embodiment, since the lines and spaces are formed in a high density pattern of 1: 1, the processing margin in lithography is improved and a fine nonvolatile memory is provided. Semiconductor memory device can be provided.

According to the nonvolatile semiconductor memory device of the present embodiment, the cutoff characteristic of the select transistor can be improved to achieve miniaturization, and the select transistor and the memory cell transistor have different threshold voltages of the transistors. Channel length dependence is obtained.

Here, the nonvolatile semiconductor memory device having the sectional structure shown in FIG. 1 has the circuit configuration as shown in the circuit diagram of FIG.

As shown in FIG. 3, in the memory cell unit of the NAND flash memory, a plurality of, for example, 16 memory cell transistors M0 to M15 forming the memory block 5 shown by the area surrounded by the broken line are connected in series. , Two drain side select transistors SG11, SG12 are connected to one side, and two source side select transistors SG21, SG22 are connected to the other side.

A plurality of memory cells are connected in series to form a NAND cell (memory cell unit) which is one memory cell array. The source and drain of each memory cell are connected in series with each other via a diffusion layer region provided on the element region.

Word lines WL0 to WL15 are connected to the gates of the memory cell transistors M0 to M15 in a one-to-one relationship. Drain side selection transistor SG
The select gate line SGD1 is connected to the gate of 11,
A select gate line SGD2 is connected to the gate of the drain side select transistor SG12. The gate of the source side select transistor SG21 has a select gate line SGS.
1 is connected, and the selection gate line SGS2 is connected to the gate of the source side selection transistor SG22.

The source of the drain side select transistor SG12 is connected to the bit line DQ which is a data line. The source of the source side selection transistor SG22 is connected to the common source line CS.

Although not shown, a plurality of NAND strings 5 are connected in the direction in which the data lines extend.
Further, a plurality of NAND strings 5 having the same circuit configuration are provided for each bit line in the extending direction of the word line.

The select transistors need not be arranged on both sides of the memory cell transistor in order to select a block of memory cells, but may be arranged on only one side.

The NAND strings 5 are serially connected in series, contacts are provided at the ends of the NAND strings, and a plurality of memory cell transistors are connected via the select transistors at both ends.

The present embodiment is not limited to the NAND flash memory, but can be applied to an AND flash memory as shown in the circuit diagram of the memory cell unit in FIG. Even in this case, the memory cell transistor has a structure having a floating gate which is a charge storage layer.
A non-volatile memory cell array composed of one or more transistors is configured.

That is, as shown in FIG. 4, in the memory cell unit of the AND-type flash memory, a plurality of memory cell transistors M0 to M forming the memory block 20 shown by the area surrounded by the broken line, for example, 16 memory cell transistors M0 to M.
15 are connected in parallel, two drain side select transistors SG11 and SG12 are connected to one side, and two source side select transistors SG21 and SG22 are connected to the other side.

A plurality of memory cells are connected in series to form an AND cell (memory cell unit) which is one memory cell array. The source and drain of each memory cell are connected in parallel to each other via a diffusion layer region provided on the element region.

Word lines WL0 to WL15 are connected to the gates of the memory cell transistors M0 to M15 in a one-to-one relationship. Drain side selection transistor SG
The select gate line SGD1 is connected to the gate of 11,
A select gate line SGD2 is connected to the gate of the drain side select transistor SG12. The gate of the source side select transistor SG21 has a select gate line SGS.
1 is connected, and the selection gate line SGS2 is connected to the gate of the source side selection transistor SG22.

The source of the drain side select transistor SG12 is connected to the bit line DQ which is a data line. The source of the source side selection transistor SG22 is connected to the source line CS.

Although not shown, a plurality of memory blocks 20 are connected in the direction in which the data lines extend. A plurality of similar memory blocks are provided for each bit line in the extending direction of the word line.

The select transistors need not be arranged on both sides of the memory cell transistor in order to select a block of memory cells, but may be arranged on only one side.

As described above, this embodiment can be applied not only to the NAND flash memory but also to the AND flash memory. That is, for a flash memory cell having a select gate, the select gate has a gate length similar to that of the memory cell and is arranged at the same pitch, thereby realizing a memory cell structure in which fine processing can be performed lithographically.

The present embodiment realizes a memory cell array which has a high exposure margin and is scalable with miniaturization. When the gate length is the same as that of the memory cell transistor, transistor characteristics such as short channel effect of the select gate cannot be secured, but transistor characteristics can be secured by connecting two select gates.

In the nonvolatile semiconductor memory device of this embodiment, by connecting two transistors having a gate length of F in series, the same characteristics as those of a transistor having a gate length of 2F can be obtained, and the gate length of 2F can be obtained. A cutoff characteristic equivalent to that of a transistor can be obtained.

(Second Embodiment) In the first embodiment, only the first conductive layer of the select gate functions as a conductive layer, and the second conductive layer is insulated. In the present embodiment, the impurity concentration of the channel region of the select gate is changed to that of the channel region of the memory cell gate, so that the gate length is kept at F even if the select transistor is two series-connected transistors having the minimum feature size. It can be realized without impairing the function. That is, the impurity concentration can be appropriately controlled by the impurities injected into the channel region through the opening provided in the insulating film between the first conductive layer and the second conductive layer.

Since the select gate has the same gate length as the memory cell gate, the cutoff characteristic due to the short channel effect is sacrificed. As a solution to this problem, in addition to the configuration described in the first embodiment, for example, Japanese Patent Application No. 2001
No. 158066, there is also proposed a method of forming a memory cell gate and a select gate by separate channel implanters and performing different channel control as proposed.

FIG. 5 shows a plan configuration of the memory cell unit according to the present embodiment. As shown in FIG. 5, a plurality of memory cell gates 1 are linearly formed in parallel with each other. Two select gates 21 are linearly formed on both ends of each of the plurality of memory cell gates in parallel with each other and in parallel with the memory cell gate 1. here,
The plurality of memory cell gates have the same gate length W1
have. In addition, a plurality of memory cell gates are eight,
It can be configured by the number such as 16. Further, the pair of two select gates 2 have the same gate length W2,
This gate length W2 is the gate length W1 of the memory cell gate 1.
Is formed equal to.

Spaces F having the same width (F is a minimum processing size) are provided between the memory cell gates 1.
This space F is the gate length W1 of the memory cell gate 1.
And equal to the gate length W2 of the select gate 2. Further, a space F which is the same as the space F between the memory cell gates 1 is provided between the select gate and the memory cell gate adjacent to the select gate.

Element active regions 3 are formed parallel to each other in a direction orthogonal to the memory cell gate 1. The element active region 3 is formed by a plurality of element isolation regions 4 formed in parallel to each other in a direction orthogonal to the memory cell gate 1.
It is divided into multiple pieces.

On each element active region 3 of each select gate 21, an opening 22 for ion implantation for the select transistor channel is provided.

Further, in the plan view of FIG. 5, impurity implantation is performed in a self-aligned manner in the opening 22 indicated by the broken line with the vicinity of the intersection of the active region 3 and the select gate 21 as the center. As a result, although the select gate and the memory cell gate are densely arranged in high density, the impurity concentrations of different channel portions can be individually formed in a self-aligned manner.

The source and drain of each memory cell are connected to each other in series via the active region 3.

Here, a pair of two select gates 2 are formed at both ends of a plurality of, for example, 16 memory cell gates 1 to form one NAND string 23. At the end of this NAND string 5. Another NAND string 23 is formed with the same space F as the space F between the memory cell gates 1 placed. here,
A contact 24 is formed on the element active region between the select gates of the NAND strings adjacent to each other.

As described above, the gate lengths are all constant lines and spaces in the memory cell and are arranged at the same pitch. In addition, the channel length of the select gate is miniaturized to the same size as the memory cell transistor.
The select gate is used as a select transistor by using two gates.

A cross section taken along the line CD in FIG. 5 is shown in FIG. As shown in FIG. 6, the memory cell gate 1 and the select gate 21 are provided on the semiconductor substrate 10. In the semiconductor substrate 10 around the memory cell gate 1 and the select gate 21, the source / drain diffusion layer 11
Is provided. A channel ion implantation layer 12 is formed in the semiconductor substrate 10 under each memory cell gate 1. In addition, the semiconductor substrate 10 below the selection gate 21
A channel ion implantation layer 25 implanted through the opening 22 is provided therein. A contact 24 is connected to the source / drain diffusion layer 11 outside the select gate 2 at the end of the NAND string 23.

Each memory cell gate 1 has a semiconductor substrate 10
A first conductive layer 14 serving as a floating gate which is a charge storage layer is formed on the gate insulating film 13. A second conductive layer 16 serving as a control gate is formed on the first conductive layer 14 with an inter-gate insulating film 15 interposed therebetween. The inter-gate insulating film 15 is composed of, for example, a silicon oxide film, a silicon nitride film, and an ONO film which is a laminated film of a silicon oxide film.

Here, the select gate 21 is the semiconductor substrate 1
A first conductive layer 14 serving as a floating gate that is a charge storage layer is formed on the gate insulating film 13 via the gate insulating film 13. An inter-gate insulating film 15 is formed on the first conductive layer 14. An opening 22 is provided in the inter-gate insulating film 15. A second conductive layer 16 serving as a control gate is formed on the inter-gate insulating film 15 and the opening 22. A conductive material amount of the same material as that of the second conductive layer 16 is embedded in the opening portion 22 and the second conductive layer 16 and the first conductive layer 16
It serves as a connection portion electrically connected to the conductive layer 14. The inter-gate insulating film 15 is ON which is, for example, a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film.
It is composed of an O film.

A channel ion implantation layer 12 is formed in contact with the source / drain diffusion layer 11 near the surface of the region between the source / drain diffusion layers 11 in the semiconductor substrate 10. Further, in the vicinity of the surface of the semiconductor substrate 10, the opening 2 is surrounded by the source / drain diffusion layer 11.
The select transistor channel diffusion layer 25 is formed in a region including at least immediately below 2.

The selection transistor channel diffusion layer 25 is
Its impurity concentration is higher than that of the memory cell transistor channel diffusion layer 12, and its depth in the semiconductor substrate is deeper than that of the memory cell transistor channel diffusion layer 12.

Here, the size of the opening 22 provided in the insulating film 15 below the selection gate 21 is about half the length of the selection gate 21.

The length of the select transistor channel diffusion layer 25 can be changed by controlling the length of the opening 22 in the select gate 21.

Further, the selection gate 2 is provided through the opening 22.
By controlling the dose amount of the ion implantation performed under 1 independently of the memory cell transistor, the concentration of the channel diffusion layer of the select transistor can be freely set.

The impurity concentration of the channel portion of the select gate 21 is, for example, about 10 ¹⁷ / cm ³ .

Further, the height of the memory cell gate 1 is formed to be equal to the height of the select gate 21.

In the present embodiment, as in the first embodiment, not only a NAND flash memory but also a flash memory cell having a selection gate such as an AND flash memory, the selection gate is the same as the memory cell. By making the gate length to be the same and arranging at the same pitch, it is possible to realize a memory cell structure in which fine processing can be performed lithographically.

As described above, the select gate 21 is the first conductive layer 1
4 can be supplied with a potential,
It functions similarly to the SFET, and its laminated gate structure has the same composition and size as the memory cell transistor except that it has an opening.

In this way, this embodiment can obtain the same effect as that of the first embodiment.

Further, in the present embodiment, the impurity concentration of the channel region of the select transistor can be set higher than that of the channel region of the memory cell transistor, so that the threshold value of the select transistor can be set higher than that of the memory cell transistor. It is possible to provide a nonvolatile semiconductor memory device having a cutoff characteristic (current cutoff characteristic) required for the selection transistor.

Furthermore, the floating gate of the selection transistor and the selection gate are connected through an opening provided in the insulating film between the gates. By using the nonvolatile semiconductor memory device having such a configuration, the data writing characteristics and the data can be obtained by using the selection transistor having a necessary channel ion concentration and the channel concentration set to be thin so as to be suitable for miniaturization. It is possible to provide a fine non-volatile semiconductor memory device provided with a memory cell transistor having excellent characteristics such as a memory cell transistor such as retention characteristics and resistance to read stress.

Next, a method of manufacturing the nonvolatile semiconductor memory device of this embodiment will be described with reference to FIGS.
6 to 17 correspond to a partial or entire cross section taken along the line C-D in FIG.

First, as shown in FIG. 7, a sacrificial silicon oxide film 3 is formed on a semiconductor substrate 10 made of P-type silicon.
Form 0. Next, depending on the case, a P-type well or N
A double well such as a type well and a P-type well is formed and activated.

Next, when an N-type transistor is formed in the semiconductor substrate 10 or in a region where a well is formed on the semiconductor substrate 10, the same P (B-type) such as B (boron) is simultaneously applied to both the memory cell transistor and the selection transistor. Channel ion implantation of impurities is performed for channel control, and an impurity ion implantation layer 12 is formed near the surface of the semiconductor substrate 10.

Next, as shown in FIG. 8, the sacrificial silicon oxide film 30 formed for ion implantation is peeled off to form a gate insulating film 13. Then, as the gate electrode material for the floating gate electrode, for example, polysilicon is deposited to form the floating gate electrode layer 14. In order to make this polysilicon conductive, for example, P (phosphorus) that is previously doped is used. Alternatively, P may be ion-implanted by ion implantation.

Next, a mask material 31, for example, a silicon nitride film (Si ₃ N ₄ ) for processing the element isolation region is deposited on the floating gate electrode layer 14.

Next, as shown in FIG. 9, the mask material 31 which is a silicon nitride film is removed.

Next, as shown in FIG. 10, an inter-gate insulating film 15 is deposited on the exposed surface as an ONO film, for example.

Next, as shown in FIG. 11, polysilicon and other mask materials such as a silicon oxide film are deposited as the mask material 32 on the deposited inter-gate insulating film 15.

Next, as shown in FIG. 12, a part of the planned channel region of the select transistor of the memory cell unit is patterned by lithography, a photoresist 33 is deposited on the mask material 32, and an opening 34 is formed. To provide. Here, a state in which two openings 34 are provided is shown.

Next, as shown in FIG. 13, the mask material 32 immediately below the opening 34 of the photoresist 33 is etched and opened.

When patterning this mask material,
Processing is performed by a method capable of processing the minimum processing dimension in each generation in the semiconductor device manufacturing technology (generally, an expensive fine processing technology with the highest performance is used). For this reason, misalignment in the opening provided in the mask material is suppressed to a minimum.

Next, as shown in FIG. 14, the photoresist 33 is removed, and the inter-gate insulating film 15, the floating gate electrode layer 14, and the gate insulating film 13 are formed on the semiconductor substrate 10 which will be the channel region of the select transistor. Ion implantation is performed through the above to form the select transistor channel diffusion layer 25. B (boron) is usually used as the implanted ion species at this time. However, if the surface channel type PMOS is P
It may be (phosphorus).

At this time, there is a mask material 32 in the memory cell transistor region, and the film thickness is such that the ion species implanted are attenuated in the mask material 32. The acceleration energy is adjusted to reach the semiconductor substrate 10 beyond the charge storage layer.

Although the ion implantation is performed without leaving the photoresist 33 here, it is also possible to perform the ion implantation with the photoresist 33 left and then remove the photoresist 33.

Next, as shown in FIG. 15, the opening 3
The inter-gate insulating film 15 underneath 4 is opened by etching.

The ion implantation for forming the select transistor channel diffusion layer 25 may be performed after the intergate insulating film 15 is opened by etching. When the ion implantation is performed with the inter-gate insulating film 15 left, the contamination of the surface of the floating gate electrode layer 14 made of a polycrystalline silicon layer can be prevented and the inter-gate insulating film 15 can be used as a protective film.

Next, as shown in FIG. 16, the mask material 32 is peeled off. Next, as the control gate electrode material 16,
As polysilicon and metal silicide, for example, WSi
(Tungsten silicide) or the like is deposited. Here, as the control gate material, for example, only polysilicon may be deposited. In this case, after depositing polysilicon and performing gate processing, salicide (Salicide: Self-Aligned
Silicide: a self-aligned silicide formation technique) method can be used to form an electrode using silicide.

Next, as shown in FIG. 17, the gate electrode region is patterned by lithography, the laminated gate structure is etched, and the memory cell including the charge storage layer 14, the intergate insulating film 15, and the control gate 16 is formed. Transistor gate electrode, charge storage layer 14, inter-gate insulating film 1
5. The select transistor gate electrode including the control gate 16 is formed to have the same gate length and the same pitch. RIE is used for the etching process at this time. Here, a pair of two control gates are formed at the end of the memory cell for each memory cell unit.

Next, as shown in FIG. 6, the semiconductor substrate 1 is masked with the memory cell transistor gate electrode and the select transistor gate electrode having the stacked gate structure.
Impurities are ion-implanted into 0 to form a source / drain.

In particular, if ion implantation is performed after opening the inter-gate insulating film of the select transistor in order to electrically short-circuit the floating gate and the control gate, the present embodiment can be performed without adding a lithography process. Become.

This manufacturing method employs a method of partially removing the inter-gate insulating film 15 separating the charge storage layer 14 and the control gate 16. This method is applied to the select gate electrode in the memory cell unit. This method is for making contact with the charge storage layer 14, but if the following conditions are satisfied during the manufacturing process,
It is possible to implant ions only in the channel portion of the select gate through the floating gate.

That is, impurities are attenuated in the mask material by the ion implantation into the memory cell gate and do not reach the charge storage layer, and on the select gate, ions are implanted through the charge storage layer and the gate insulating film. When the impurity is injected into the semiconductor substrate to form channel regions having different impurity concentrations in the memory cell gate and the select gate, the respective channel portions are formed so as to satisfy the characteristics of the memory cell and the select gate, respectively. The respective characteristics can be improved by the self-alignment process without adding a new lithography process.

Self-aligned channel ion implantation into the select gate can be performed, and there is no misalignment, and channel impurities of the select gate can be formed.

By the manufacturing method described above, the select transistor and the memory cell transistor can be independently formed in different channel impurity concentrations in a self-aligned manner.

In this manner, the respective transistors having different impurity concentrations in a part of the channel part of the select transistor of the memory cell and in the channel part of the memory cell part are formed in a self-aligned manner. Here, in the select transistor, some of the passing ions at the time of channel ion implantation remain in the gate insulating film below the charge storage layer. The remaining region is a peripheral region including immediately below the shape of the opening provided in the interelectrode insulating film on the charge storage layer.

According to the present embodiment, channel injection is not performed through the gate insulating film of the memory cell transistor, and in particular, characteristic deterioration of the nonvolatile semiconductor memory device having the floating gate structure is not caused.

Note that this embodiment may be an N-type transistor or a P-type transistor, and B (boron) is used as an impurity ion species to be ion-implanted for channel control of the memory cell transistor and the selection transistor. However, it may be P (phosphorus).

As described above, in this embodiment, the memory cell transistor is masked to provide a highly accurate opening portion of the mask material corresponding to the channel region of the selection transistor, and the opening portion is used to make the channel. Ion implantation is performed on the region to perform channel ion implantation without causing misalignment.

Since the memory cell transistor is ion-implanted into the select transistor in a state where there is no opening in the insulating film between the first conductive layer and the second conductive layer of the gate electrode, the concentration of the channel region of the memory cell transistor is reduced. Is set independently of the channel concentration of the selection transistor.

(First Modification of Second Embodiment) In the structure of the nonvolatile semiconductor memory device of this modification, the structure of the nonvolatile semiconductor memory device shown in FIG. 6 is changed to that shown in FIG. A deep channel ion-implanted region 25 is formed in the semiconductor substrate 10 corresponding to the opening 22 in the inter-gate insulating film of one of the pair of two select gates, the select gate farther from the memory cell gate. It can be formed to improve the cutoff characteristic. Here, the same channel ion implantation region 12 as the memory cell gate is formed below the select gate adjacent to the memory cell gate.

Incidentally, in one NAND string,
Two select gates are provided on each of the source side and the drain side, but the impurity concentration and depth of the channel ion implantation region under the select gate adjacent to the memory cell gate may be adjusted on both the source side and the drain side. The impurity concentration and the depth of the channel ion implantation region of the memory cell gate can be set to be equal.

The manufacturing method of this modification is similar to the manufacturing method of the second embodiment except that after the step shown in FIG.
A region where a selective gate is to be formed below the selective gate is not covered with a photoresist, and a thick ion-implanted region 25 is formed in the semiconductor substrate only for the selective gate under which the selective gate is to be implanted.

As described above, while adopting the gate structure shown in FIG. 6, the side of the select transistor adjacent to the memory cell transistor is masked with a resist (not shown), and channel ion implantation is performed. The concentration and depth of the region may be formed to be thinner and shallower than those of the selection transistor separated from the memory cell transistor, so that the cutoff characteristics of the selection transistors can be made different.

That is, the concentration and depth of the channel ion implantation region of the select gate adjacent to the memory cell transistor are equal to the concentration and depth of the channel ion implantation region of the memory cell gate. On the other hand, the concentration and depth of the channel ion implantation region of the select gate on the side distant from the memory cell transistor are formed deeper and deeper than the concentration and depth of the channel ion implantation region of the memory cell gate. .

In this case, it is possible to strongly impart the cutoff characteristic farther from the memory cell and suppress the influence of the impurity diffusion to the memory cell closer to the memory cell. With such a configuration, it is possible to prevent the phenomenon of channel impurities from seeping out to the memory cell transistor adjacent to the select gate.

(Second Modification of Second Embodiment) In the structure of the nonvolatile semiconductor memory device of this modification, the structure of the nonvolatile semiconductor memory device shown in FIG. 6 is changed to that shown in FIG. One of the pair of two select gates 21 is modified,
It is possible to improve the cutoff characteristics by forming the deep channel ion implantation region 25 in the semiconductor substrate 10 corresponding to the opening 22 in the inter-gate insulating film 15 of the select gate 21 adjacent to the memory cell gate 1. Here, the memory cell gate 1
The same channel ion implantation region 12 as that of the memory cell gate 1 is formed below the select gate 21 spaced apart from.

In one NAND string,
Two selection gates 21 are provided on each of the source side and the drain side, and the impurity concentration of the channel ion implantation region under the selection gate 21 that separates one or both of the source side and the drain side from the memory cell gate 1, The depth can be set equal to the impurity concentration and depth of the channel ion implantation region of the memory cell gate 1.

The manufacturing method of this modification is the same as the manufacturing method of the second embodiment except that after the step shown in FIG.
A region where a selective gate is to be formed below the selective gate is not covered with a photoresist, and a thick ion-implanted region 25 is formed in the semiconductor substrate only for the selective gate under which the selective gate is to be implanted.

As described above, while adopting the gate structure shown in FIG. 6, the side of the select transistor separated from the memory cell transistor is masked with a resist (not shown), and channel ion implantation is performed. The concentration and depth of the region may be formed to be thinner and shallower than those of the select transistor adjacent to the memory cell transistor so that the cutoff characteristics of the select transistors can be made different.

That is, the concentration and depth of the channel ion implantation region of the select gate 21 separated from the memory cell gate 1 are equal to the concentration and depth of the channel ion implantation region of the memory cell gate 1. On the other hand, the channel ion implantation region of the select gate 21 adjacent to the memory cell gate 1 has a concentration and a depth which are different from those of the memory cell gate 1.
The concentration and depth of the channel ion implantation region are formed deeper and deeper.

In this case, the cutoff characteristic closer to the memory cell is strongly provided.

Each embodiment can be applied to a nonvolatile semiconductor memory device having a selection gate. further,
Each embodiment can be applied to the transistors in the peripheral circuit.

Further, not limited to the nonvolatile semiconductor memory device,
Each embodiment is applicable to a memory-embedded semiconductor device including a nonvolatile semiconductor memory device.

[0146]

According to the present invention, it is possible to provide a fine non-volatile semiconductor memory device in which the cutoff characteristic of a transistor is improved and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing the structure of the nonvolatile semiconductor memory device according to the first embodiment of the invention.

FIG. 3 is a circuit diagram showing an example flash memory cell unit configured by a NAND flash memory of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example flash memory cell unit configured with an AND flash memory of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a plan view showing a structure of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 6 is a sectional view showing a structure of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step in the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the invention.

FIG. 8 is a sectional view showing a step of the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a step in the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the invention.

FIG. 10 is a cross-sectional view showing a step in the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the invention.

FIG. 11 is a cross-sectional view showing a step in the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the invention.

FIG. 12 is a cross-sectional view showing a step in the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the invention.

FIG. 13 is a cross-sectional view showing a step in the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the invention.

FIG. 14 is a cross-sectional view showing a step in the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the invention.

FIG. 15 is a cross-sectional view showing a step in the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the invention.

FIG. 16 is a cross-sectional view showing a step in the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the invention.

FIG. 17 is a cross-sectional view showing a step in the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the invention.

FIG. 18 is a cross-sectional view showing a structure of a nonvolatile semiconductor memory device according to a first modification of the second embodiment of the present invention.

FIG. 19 is a cross-sectional view showing a structure of a nonvolatile semiconductor memory device according to a second modification of the second embodiment of the present invention.

FIG. 20 is a plan view showing the structure of a conventional nonvolatile semiconductor memory device.

FIG. 21 is a cross-sectional view showing the structure of a conventional nonvolatile semiconductor memory device.

FIG. 22 is a circuit diagram showing a flash memory cell unit of a nonvolatile semiconductor memory device of a conventional NAND flash memory.

FIG. 23 is a circuit diagram showing a flash memory cell unit of a conventional AND type flash memory nonvolatile semiconductor memory device.

[Explanation of symbols]

1 Memory cell gate 2, 21 Select gate 3 Element active region 4 Element isolation region 5, 23 NAND string 6, 24 Contact 10 Semiconductor substrate 11 Source / drain diffusion layer 12 Channel ion implantation layer 13 Gate insulating film 14 First conductive layer ( Charge storage layer 15 Inter-gate insulating film (ONO film) 16 Second conductive layer (control gate) 20 Memory block 22, 34 Opening 25 Select transistor channel diffusion layer 31, 32 Mask material 33 Photoresist CS Common source line DQ data Lines M0 to M15 Memory cell transistors SG11, SG12, SG21, SG22 Select transistors SGD1, SGD2, SGS1, SGS2 Select gate lines WL0 to WL15 Word lines

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yuji Takeuchi             8th Shinsugita Town, Isogo Ward, Yokohama City, Kanagawa Prefecture             Ceremony company Toshiba Yokohama office (72) Inventor Tatsuaki Kuji             8th Shinsugita Town, Isogo Ward, Yokohama City, Kanagawa Prefecture             Ceremony company Toshiba Yokohama office (72) Inventor Seiichi Mori             8th Shinsugita Town, Isogo Ward, Yokohama City, Kanagawa Prefecture             Ceremony company Toshiba Yokohama office (72) Inventor Riichiro Shirata             8th Shinsugita Town, Isogo Ward, Yokohama City, Kanagawa Prefecture             Ceremony company Toshiba Yokohama office F term (reference) 5F083 EP02 EP23 EP33 EP34 EP55                       EP56 EP76 EP79 GA09 LA21                       PR43 PR53 ZA01                 5F101 BA29 BA36 BB05 BD22 BH21

Claims (8)

[Claims] 1. A semiconductor substrate, an element region formed in the semiconductor substrate, an element isolation region separating the element region in the semiconductor substrate, and a plurality of element regions formed in the element region, each having an equal gate length. And a memory cell gate that is separated from each other by a distance equal to the gate length, and is adjacent to the memory cell gate with the distance separated from each other, and is separated from the memory cell gate by the distance separated from each other. And two select gates formed to have the gate length. 2. The memory cell gate is a NAND type EEP.
The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory devices are connected to each other by a ROM or an AND type EEPROM. 3. The two select gates include a first conductive layer,
It has a gate insulating film thereon and a second conductive layer on the insulating film, and the first conductive layer and the second conductive layer are short-circuited on the element active region. The non-volatile semiconductor memory device according to claim 1. 4. One of the two select gates is a first
A conductive layer, a gate insulating film on the conductive layer, and a second conductive layer on the insulating film, and an opening is provided in a part of the gate film on the element active region. And the second
3. The non-volatile semiconductor memory device according to claim 1, wherein the conductive layer is short-circuited. 5. The nonvolatile semiconductor memory device according to claim 1, wherein the impurity concentration of the channel region of the select gate and the impurity concentration of the channel region of the memory cell gate are different from each other. 6. The memory cell gate and the select gate each have a first conductive layer, a gate insulating film on the first conductive layer, and a second conductive layer on the insulating film, and the first conductive layer is the The memory cell gate and the select gate have the same thickness, the gate insulating film has the same thickness in the memory cell gate and the select gate, and the second conductive layer has the memory cell gate. 3. The nonvolatile semiconductor memory device according to claim 1, wherein the select gate and the select gate have the same thickness. 7. A plurality of memory cell gates connected in series, each having an equal gate length, and arranged at a distance equal to the gate length, and a plurality of memory cell gates on the source side or Each of the memory cell gates has a gate length equal to that of the memory cell gate connected to one of the drain-side end portions, is separated from each other by a distance equal to the distance, and is separated from the memory cell gate by a distance equal to the distance. Two first placed
A select gate group and a gate length that is equal to the memory cell gate connected to one of the source side or drain side ends of the plurality of memory cell gates, and is separated from the memory cell gate by the distance equal to the distance. A non-volatile semiconductor memory device, comprising: at least one second selection gate group arranged at a distance. 8. A plurality of first memory cell gates connected in series, each having an equal first gate length and being spaced apart from each other by a first separation distance equal to the first gate length, and the plurality of first memory cell gates. Of the first memory cell gates, each of which has a first gate length equal to the plurality of first memory cell gates connected to one of the source-side end and the drain-side end of the first memory cell gate, and is separated from each other by the first distance. A plurality of first memory cell gates spaced apart from each other by the first separation distance;
One first select gate group, and a first gate length equal to the plurality of first memory cell gates connected to one of the source side or drain side ends of the plurality of first memory cell gates. A plurality of first memory cell gates and at least one second selection gate group which is arranged at a first distance from the first memory cell gate; and a second selection gate group which is arranged at a first distance from the second selection gate group; A first memory cell gate having a plurality of first memory cell gates;
At least one third selection gate group having a gate length, and a second separation distance equal to the first separation distance from the third selection gate group, connected in series, and respectively connected to the first gate length. A plurality of second memory cell gates having an equal second gate length and arranged at a second distance equal to the second gate length, and a source side or a drain of the plurality of second memory cell gates; Each having the plurality of second gate lengths connected to one of the end portions on the side, and separating the second separation distance from each other,
A non-volatile semiconductor memory device comprising: a plurality of second memory cell gates and two fourth selection gate groups arranged at the second distance.