JP2003023102A - Method of manufacturing capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a capacitor for reducing a gap that occurs in an interlayer insulating film and for reducing the deterioration of contact performance between a lower electrode and a contact plug. SOLUTION: The contact plug 3 is formed by making it project from the surface of the interlayer insulating film 2, and a stopper layer 4 is formed on it. The projecting distance of the contact plug 3 is made longer than the distance (t) of the thickness direction of the stopper layer 4. Thus, a contact distance (a) between the side 33 of the projecting part 13 of the contact plug 3 and the stopper 4 becomes longer than the distance (t) of the thickness direction of the stopper layer 4. The soaking route of hydrofluoric acid used when an inter-dummy layer film 5 is removed becomes longer than the distance (t) of the thickness direction of the stopper layer 4. Thus, hydrofluoric acid is difficult to soak into the interlayer insulating film 2, and the deterioration of the contact performance of the lower electrode 9 and the contact plug 3 can be reduced. Since the stopper layer has one layer, a contact hole for peripheral circuit, which is opened to the periphery of the capacitor, can easily be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor, and more particularly to a method of manufacturing a capacitor incorporated in a DRAM (dynamic random access memory).

[0002]

41 to 49 are cross-sectional views showing a manufacturing process of a capacitor in the first conventional technique, particularly D
7 shows a manufacturing process of a capacitor incorporated in a RAM.

First, an interlayer insulating film 2 made of a silicon oxide film is formed on a substrate 1, and a contact plug 3 electrically contacting the substrate 1 is formed inside the interlayer insulating film 2 (FIG. 41). At this time, the upper surface of the structure obtained in the step shown in FIG. 41 is flattened by using the CMP method. Next, a stopper layer 4 which is a silicon nitride film is formed on the interlayer insulating film 2 and the contact plug 3 (FIG. 42), and a dummy interlayer film 5 which is a silicon oxide film is further formed on the stopper layer 4 (FIG. 42). 43).

Next, using photolithography technology,
Contact holes 7 are formed in the dummy interlayer film 5 and the stopper layer 4.
To open. Specifically, a resist 6 is formed on the dummy interlayer film 5, the resist 6 is patterned, the dummy interlayer film 5 and the stopper layer 4 are etched using the patterned resist 6 as a mask, and the contact plug 3 is formed. To open the contact hole 7 reaching (Fig. 4
4). Then, the resist 6 used for forming the contact hole 7 is removed (FIG. 45).

In the contact hole 7 and the dummy interlayer film 5 formed as described above, the conductive layer 8 is formed by using a film forming method having a good covering property such as a CVD method (FIG. 4).
6). After that, the conductive layer 8 is etched by dry etching or CMP to leave the conductive layer 8 only in the contact hole 7 and form the lower electrode 9 of the capacitor in the contact hole 7 (FIG. 47).

Next, using the stopper layer 4 as an etching stopper, the dummy interlayer film 5 is selectively removed using hydrofluoric acid to expose the pillar-shaped lower electrode 9 (FIG. 4).
8). Then, the dielectric film 20 is formed so as to cover the surfaces of the lower electrode 9 and the stopper layer 4 each having a leaf shape, and the upper electrode 19 is further formed on the dielectric film 20 to complete a capacitor incorporated in a DRAM ( (Fig. 49).

In the first prior art capacitor formed as described above, when the lower electrode 9 is formed in the contact hole 7 and then the dummy interlayer film 5 is removed with hydrofluoric acid, the hydrofluoric acid is removed. Permeates into the interlayer insulating film 2 to generate voids in the interlayer insulating film 2, which deteriorates the contact performance between the lower electrode 9 and the contact plug 3. FIG. 50 is a cross-sectional view showing a state of voids generated in the interlayer insulating film 2 of the capacitor according to the first conventional technique.

As shown in FIG. 50, when the dummy interlayer film 5 is removed with hydrofluoric acid, the hydrofluoric acid penetrates the interlayer insulating film 2 through the gap between the lower electrode 9 and the stopper layer 4, and the silicon oxide film is formed. Then, the interlayer insulating film 2 is etched to form a void 10 in the interlayer insulating film 2 near the upper end of the contact plug 3. Due to this void 10, there is a problem that the contact resistance between the lower electrode 9 and the contact plug 3 increases, and the contact performance deteriorates.

In order to solve such a problem, a stopper layer is further provided on the upper end portion of the interlayer insulating film 2 in which the contact plug 3 is formed, and the stopper layer is made into two layers so that the hydrofluoric acid is used as the interlayer insulating film. The route through which it penetrates into 2 (hereafter
A second conventional technique has been proposed in which the "impregnated path" is lengthened to suppress the generation of voids in the interlayer insulating film 2. 51 to 54 are cross-sectional views showing the manufacturing process of the capacitor according to the second conventional technique. First, the interlayer insulating film 2 is formed on the substrate 1, and further, the stopper layer 14 which is a silicon nitride film is formed on the interlayer insulating film 2. Then, inside the interlayer insulating film 2 and the stopper layer 14, the contact plug 3 which is in electrical contact with the substrate 1 is formed (FIG. 51). At this time, the upper surface 23 of the contact plug 3
And the surface 49 of the stopper layer 14 are formed on substantially the same plane. Next, the stopper layer 4 is formed on the stopper layer 14 and the contact plug 3, and the dummy interlayer film 5 is further formed on the stopper layer 4 (FIG. 52).

Next, similarly to the first conventional technique, a contact hole 7 reaching the contact plug 3 is opened in the dummy interlayer film 5 by using the photolithography technique (FIG. 53). Then, the lower electrode 9 of the capacitor is formed in the contact hole 7 (FIG. 54).

After the step shown in FIG. 54, the dummy interlayer film 5 is formed.
Is removed by hydrofluoric acid. At this time, the hydrofluoric acid permeates the interlayer insulating film 2 through the gap between the lower electrode 9 and the stopper layer 4 and further through the gap between the contact plug 3 and the stopper layer 14. . As described above, in the second conventional technique, the hydrofluoric acid used when removing the interlayer insulating film 2 passes through the gap between the contact plug 3 and the stopper layer 14, and therefore is more hydrofluoric acid than the first conventional technique. The path for the hydrofluoric acid to soak in becomes longer. Therefore, hydrofluoric acid is less likely to soak into the interlayer insulating film 2, and the generation of voids in the interlayer insulating film 2 can be reduced. As a result, it is possible to reduce the deterioration of the contact performance between the lower electrode 9 and the contact plug 3.

[0012]

However, in the second prior art, as shown in FIG. 54, since the stopper layer is double formed around the contact plug 3,
The stopper layer is formed thicker than in the first conventional technique. Further, since the silicon nitride film is usually a material that is harder to etch than the silicon oxide film, it is difficult to open the contact hole in the peripheral circuit of the capacitor in the second prior art in which the stopper layer is double formed. There was a problem of becoming.

Therefore, the present invention has been made in order to solve the above-mentioned problems, and reduces the occurrence of voids in the interlayer insulating film without increasing the thickness of the stopper layer, and reduces the lower electrode and the contact plug. It is an object of the present invention to provide a method for manufacturing a capacitor that reduces deterioration of contact performance with.

[0014]

[Means for Solving the Problems] Claim 1 of the present invention
In the method for manufacturing a capacitor described in (a), a contact plug having a protrusion protruding from the surface of the interlayer insulating film is formed,
Forming in the interlayer insulating film, (b) forming a stopper layer to cover the side surface and the upper surface of the protruding portion of the contact plug and the surface of the interlayer insulating film, and (c) the stopper Forming a dummy interlayer film covering the surface of the layer; and (d) forming a contact hole in the dummy interlayer film and the stopper layer, the contact hole reaching the upper surface of the protrusion of the contact plug.
(E) a step of forming a lower electrode in the contact hole.

According to a second aspect of the present invention, the method of manufacturing a capacitor comprises: (a) a step of forming a contact plug having a protrusion protruding from the surface of the interlayer insulating film in the interlayer insulating film. And (b) a step of forming a stopper layer so as to cover a side surface and an upper surface of the protruding portion of the contact plug and the surface of the interlayer insulating film, and (c)
The step of forming a second interlayer insulating film so as to cover the surface of the stopper layer, and (d) removing the stopper layer and the second interlayer insulating film, thereby obtaining the step (c). Planarizing the upper surface of the structure to expose the upper surface of the protrusion of the contact plug; (e) the surface of the stopper layer obtained in step (d); and the protrusion of the contact plug. Covering the upper surface of
Forming a dummy interlayer film; (f) forming a contact hole in the dummy interlayer film to reach the upper surface of the protruding portion of the contact plug; and (g) forming a lower electrode in the contact hole. And a step of performing.

The method of manufacturing a capacitor according to a third aspect of the present invention is the method of manufacturing a capacitor according to any one of the first and second aspects, wherein the protrusion of the contact plug is provided. The portion has a protrusion distance from the surface of the interlayer insulating film longer than a distance in the thickness direction of the stopper layer.

According to a fourth aspect of the present invention, in the method of manufacturing a capacitor, (a) a step of forming a contact plug exposed from the interlayer insulating film in the interlayer insulating film, and (b) the contact. Forming a stopper layer by covering the surfaces of the plug and the interlayer insulating film; (c) forming a dummy interlayer film by covering the surface of the stopper layer; (d) the dummy interlayer film and the A step of opening a contact hole reaching the contact plug in the stopper layer; (e) a step of forming a lower electrode in the contact hole; and (f) a step of (e),
A step of selectively removing the dummy interlayer film by dry etching using the stopper layer as an etching stopper.

The method of manufacturing a capacitor according to a fifth aspect of the present invention is the method of manufacturing a capacitor according to the fourth aspect, wherein the dummy interlayer film is made of an organic polymer.

According to a sixth aspect of the present invention, in the method of manufacturing a capacitor, (a) a step of forming a contact plug exposed from the interlayer insulating film in the interlayer insulating film, and (b) the contact. Forming a stopper layer by covering the surfaces of the plug and the interlayer insulating film; (c) forming a dummy interlayer film by covering the surface of the stopper layer; (d) the dummy interlayer film and the A step of opening a contact hole reaching the contact plug in the stopper layer; (e) a step of forming a lower electrode in the contact hole; and (f) a step of (e),
And a step of selectively removing the dummy interlayer film by wet etching using a mixed solution of hydrofluoric acid and nitric acid with the stopper layer as an etching stopper.

The method of manufacturing a capacitor according to a seventh aspect of the present invention is the method of manufacturing a capacitor according to the sixth aspect, wherein the dummy interlayer film is made of silicon.

The method of manufacturing a capacitor according to claim 8 of the present invention includes: (a) a step of forming a contact plug exposed from the interlayer insulating film in the interlayer insulating film; and (b) the contact. Forming a stopper layer by covering the surfaces of the plug and the interlayer insulating film; (c) forming a dummy interlayer film by covering the surface of the stopper layer; (d) the dummy interlayer film and the A step of opening a contact hole reaching the contact plug in the stopper layer; (e) a step of forming a lower electrode in the contact hole; and (f) a step of (e),
And a step of selectively removing the dummy interlayer film by wet etching using hot phosphoric acid and using the stopper layer as an etching stopper.

A ninth aspect of the present invention is the method for producing a capacitor according to the eighth aspect, wherein the dummy interlayer film is made of silicon nitride.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. 1 to 11 are cross-sectional views showing the manufacturing process of the capacitor according to the first embodiment of the present invention, and particularly show the manufacturing process of the capacitor incorporated in the DRAM. Normally, the capacitors incorporated in the DRAM are formed in an array, but FIG.
11 to 11, the manufacturing process is shown focusing on one of the capacitors arranged in an array.

First, the interlayer insulating film 2 is formed on the substrate 1,
A contact plug 3 that is in electrical contact with the substrate 1 is formed inside the interlayer insulating film 2 (FIG. 1). At this time, the upper surface of the structure obtained in the step shown in FIG. 1 is planarized by the CMP method, and the upper surface 23 of the contact plug 3 is exposed from the interlayer insulating film 2. And contact plug 3
The upper surface 23 and the surface 12 of the interlayer insulating film 2 are located on substantially the same plane. The interlayer insulating film 2 is, for example,
Using TEOS (tetraethylorthosilicate) as a raw material, C
The contact plug 3, which is a silicon oxide film formed by the VD method, is made of, for example, polysilicon, tungsten (W), and titanium nitride (TiN) formed by the CVD method.

Next, the interlayer insulating film 2 is etched off by about 1000 Å with hydrofluoric acid diluted to about 10: 1, the contact plug 3 is projected from the surface 12 of the interlayer insulating film 2, and the contact plug 3 is pillared. Shape (Fig. 2).
As a result, the contact plug 3 comes to have the protruding portion 13 protruding from the surface 12 of the interlayer insulating film 2. Then, the stopper layer 4 is covered with 500 Å by covering the side surface 33 and the upper surface 23 of the contact plug 3 and the surface 12 of the interlayer insulating film 2 by a film forming method with good coverage such as a low pressure CVD method.
To some extent (FIG. 3). Here, as shown in FIG. 3, the distance (henceforth simply referred to as “protrusion distance”) h by which the protrusion 13 of the contact plug 3 protrudes from the surface 12 of the interlayer insulating film 2 is 1000 Å, and The distance t in the thickness direction of the layer 4 is 500Å. That is, in the protruding portion 13 of the contact plug 3, the protruding distance h from the surface 12 of the interlayer insulating film 2 is longer than the distance t in the thickness direction of the stopper layer 4. The stopper layer 4 is a silicon nitride film having high selectivity with respect to the interlayer insulating film 2, that is, the silicon oxide film.

Then, a dummy interlayer film 5 is formed on the surface 40 of the stopper layer 4 to a thickness of about 8000 Å (FIG. 4).
The dummy interlayer film 5 is flattened by polishing about 2000Å by the CMP method (FIG. 5). Here, the dummy interlayer film 5 is T
A silicon oxide film formed by a CVD method using EOS as a raw material, specifically, a plasma CVD method. Next, a contact hole 7 is opened in the dummy interlayer film 5 and the stopper layer 4 by using the photolithography technique. Specifically, a resist 6 is formed on the dummy interlayer film 5, the resist 6 is patterned, the dummy interlayer film 5 and the stopper layer 4 are dry-etched using the resist 6 as a mask, and the protruding portion of the contact plug 3 is formed. The contact hole 7 reaching the upper surface 23 of 13 is opened (FIG. 6).
Then, the resist 6 used for forming the contact hole 7 is removed (FIG. 7).

A conductive layer 8 is formed in the contact hole 7 and the dummy interlayer film 5 formed as described above by using a film forming method having a good covering property such as a CVD method (FIG. 8). After that, the conductive layer 8 is etched by dry etching or CMP to leave the conductive layer 8 only in the contact hole 7 and form the lower electrode 9 of the capacitor in the contact hole 7 (FIG. 9). Here, the conductive layer 8,
That is, the lower electrode 9 is made of a noble metal material such as platinum (Pt) or ruthenium (Ru).

Next, using the stopper layer 4 as an etching stopper, the dummy interlayer film 5 is selectively removed using hydrofluoric acid to expose the pillar-shaped lower electrode 9 (FIG. 1).
0). Then, a dielectric film 20 is formed in a thickness of 200 to 300Å to cover the surfaces of the lower electrode 9 and the stopper layer 4 having a leaf shape, and the upper electrode 19 is formed in a thickness of 300 to 300 on the dielectric film 20.
A capacitor to be incorporated into a DRAM is completed by forming 500Å. The capacitors formed in the steps shown in FIGS. 1 to 11 are called “damascene pillar type capacitors”.

According to the method of manufacturing a capacitor according to the first embodiment shown in FIGS. 1 to 11 described above, when the dummy interlayer film 5 is removed with hydrofluoric acid after the formation of the lower electrode 9, the above-mentioned first method is used. It is more difficult for the hydrofluoric acid to soak into the interlayer insulating film 2 than in the conventional method for manufacturing a capacitor. Specifically, in the first embodiment, as shown in FIG. 3, the protrusion distance h of the protrusion 13 of the contact plug 3 from the surface 12 of the interlayer insulating film 2 is the distance in the thickness direction of the stopper layer 4. longer than t. Further, since the stopper layer 4 is formed so as to cover the side surface 33 of the protruding portion 13 of the contact plug 3, the side surface 33 of the protruding portion 13 of the contact plug 3 and the stopper layer 4 are formed as shown in FIG. The contact distance (hereinafter, simply referred to as “contact distance”) a is determined by the stopper layer 4
Is longer than the distance t in the thickness direction.

On the other hand, when the dummy interlayer film 5 formed to cover the surface 40 of the stopper layer 4 is etched with hydrofluoric acid,
In the method of manufacturing the capacitor according to the first embodiment, the hydrofluoric acid is used as the side surface 33 of the protrusion 13 of the contact plug 3.
Then, it penetrates into the interlayer insulating film 2 through the gap with the stopper layer 4. For example, as shown in FIG.
Even if the opening positions of the
As shown in FIG. 2, even if the opening position of the contact hole 7 is largely deviated, the hydrofluoric acid used when removing the dummy interlayer film 5 is the protruding portion 13 of the contact plug 3.
It penetrates into the interlayer insulating film 2 through the gap between the side surface 33 and the stopper layer 4. That is, the path for the hydrofluoric acid to soak is longer than the distance t in the thickness direction of the stopper layer 4.

In the above-mentioned first conventional technique, as shown in FIG. 47, the path of the hydrofluoric acid used for removing the dummy interlayer film 5 was the same as the distance in the thickness direction of the stopper layer. . Therefore, since the hydrofluoric acid seepage route in the first embodiment is longer than the hydrofluoric acid seepage route in the first conventional technique, the hydrofluoric acid is less likely to seep into the interlayer insulating film 2. Therefore, the generation of voids in the interlayer insulating film 2 can be reduced. As a result, it is possible to reduce the deterioration of the contact performance between the lower electrode 9 and the contact plug 3.

Further, as shown in FIG. 9, the stopper layer 4 is a single layer and is opened when forming the peripheral circuit of the capacitor, as compared with the second prior art in which the stopper layer is two layers. Contact holes for peripheral circuits can be easily formed. In other words, it is possible to reduce the deterioration of the contact performance between the lower electrode 9 and the contact plug 3 with the same thickness as that of the stopper layer 4 of the above-mentioned first conventional technique. Therefore, when forming the peripheral circuit of the capacitor,
The contact hole for the peripheral circuit can be opened by the same means as in the first conventional technique.

Further, in order to bring the lower electrode 9 formed in the contact hole 7 into contact with the contact plug 3, the upper surface of the contact plug 3 may be etched when the contact hole 7 is opened. However, in order to ensure that the lower electrode 9 formed in the contact hole 7 and the contact plug 3 are in contact with each other, the etching amount when the contact hole 7 is opened is increased.
Of the upper surface 23 of the substrate 1 is further over-etched.

In the above-mentioned first conventional technique, since the upper surface 23 of the contact plug 3 is located on the same plane as the surface 12 of the interlayer insulating film 2, if overetching is performed when opening the contact hole 7, The interlayer insulating film 2 is also etched, and the lower electrode 9 formed in the contact hole 7 may enter the interlayer insulating film 2. Therefore, when the dummy interlayer film 5 is removed by using hydrofluoric acid, the hydrofluoric acid easily permeates into the interlayer insulating film 2 and promotes the generation of voids in the interlayer insulating film 2, thereby lowering the lower electrode 9 and the contact plug 9. However, there is a problem that the contact performance of is further deteriorated.

In the first embodiment, the contact plug 3
Are projected from the surface 12 of the interlayer insulating film 2, the upper surface 23 of the protruding portion 13 of the contact plug 3 is located above the surface 12 of the interlayer insulating film 2. for that reason,
Even if overetching is performed when the contact hole 7 is opened, the interlayer insulating film 2 is less likely to be etched. As a result, deterioration of contact performance between the lower electrode 9 and the contact plug 3 due to overetching can be reduced.

Embodiment 2. 13 to 21 are cross-sectional views showing the manufacturing steps of the capacitor according to the second embodiment, and the steps before the step shown in FIG.
Since it is the same as the process shown in FIG. 13, the detailed description of the process before the process shown in FIG. 13 is omitted here.

First, similarly to the steps shown in FIGS. 1 to 3 described above, the contact plug 3 having the protruding portion 13 protruding from the surface 12 of the interlayer insulating film 2 is formed in the interlayer insulating film 2, and the contact plug 3 is formed. The stopper layer 4 is formed so as to cover the side surface 33 and the upper surface 22 of the protrusion 13 and the surface 12 of the interlayer insulating film 2. Then, an interlayer insulating film 30 which is, for example, a silicon oxide film is formed to cover the surface 40 of the stopper layer 4 to a thickness of about 500 Å (FIG. 13).

Next, the interlayer insulating film 30 and the stopper layer 4 are removed by using, for example, the CMP method, and the upper surface 50 of the structure obtained in the step shown in FIG. The upper surface 23 of 13 is exposed (Fig. 1
4). Then, the dummy interlayer film 5 is covered with the surface 41 of the stopper layer 4, the upper surface 23 of the protrusion 13 of the contact plug 3 and the surface 51 of the interlayer insulating film 30 obtained in the step shown in FIG. Formed (FIG. 15).

Next, using the photolithography technique,
A contact hole 7 is opened in the dummy interlayer film 5. Specifically, a resist 6 is formed on the dummy interlayer film 5, the resist 6 is patterned, the dummy interlayer film 5 is dry-etched using the resist 6 as a mask, and the upper surface 23 of the protrusion 13 of the contact plug 3 is formed. The reaching contact hole 7 is opened (FIG. 16). Then, the resist 6 used for forming the contact hole 7 is removed (see FIG.
7).

A conductive layer 8 is formed in the contact hole 7 and the dummy interlayer film 5 formed as described above by using, for example, the CVD method (FIG. 18). Then, the conductive layer 8 is etched by dry etching or CMP,
The conductive layer 8 is left only in the contact hole 7, and the lower electrode 9 of the capacitor is formed in the contact hole 7 (FIG. 19).

Next, using the stopper layer 4 as an etching stopper, the dummy interlayer film 5 and the interlayer insulating film 30 are selectively removed using hydrofluoric acid to expose the pillar-shaped lower electrode 9 (FIG. 20). Then, the dielectric film 20 is formed to cover the surfaces of the lower electrode 9 and the stopper layer 4 in the shape of a leaflet.
0-300 Å is formed, and further the upper electrode 19 is formed on the dielectric film 20 by 300-500 Å to complete the capacitor according to the second embodiment (FIG. 21).

According to the method of manufacturing the capacitor according to the second embodiment shown in FIGS. 13 to 21 described above, the dummy interlayer film 5 is formed on the hydrofluoric acid as in the method of manufacturing the capacitor according to the first embodiment. When removed by, the hydrofluoric acid is less likely to soak into the interlayer insulating film 2 than in the method for manufacturing a capacitor according to the above-described first conventional technique.

Specifically, also in the second embodiment,
Interlayer insulating film 2 on the protruding portion 13 of the contact plug 3
The protrusion distance h from the surface 12 is longer than the distance t in the thickness direction of the stopper layer 4. Further, as shown in FIG. 19, since the stopper layer 4 is formed so as to cover the side surface 33 of the projecting portion 13 of the contact plug 3,
The contact distance a between the side surface 33 of the protrusion 13 and the stopper layer 4 is longer than the distance t in the thickness direction of the stopper layer 4.

On the other hand, also in the second embodiment, when the dummy interlayer film 5 formed so as to cover the surface 40 of the stopper layer 4 is etched with hydrofluoric acid, the hydrofluoric acid is formed on the protrusion 13 of the contact plug 3. It penetrates into the interlayer insulating film 2 through the gap between the side surface 33 and the stopper layer 4. That is, the path for the hydrofluoric acid to soak in when the dummy interlayer film 5 is removed is longer than the distance t in the thickness direction of the stopper layer 4.

Therefore, as in the first embodiment, the hydrofluoric acid seepage route in the second embodiment is longer than the hydrofluoric acid seepage route in the first prior art, and the hydrofluoric acid is used as the interlayer insulating film 2. It becomes difficult to soak into. for that reason,
Generation of voids in the interlayer insulating film 2 can be reduced. As a result, it is possible to reduce the deterioration of the contact performance between the lower electrode 9 and the contact plug 3.

Further, in the steps shown in FIGS.
Although a silicon nitride film can be used as the interlayer insulating film 30, since a silicon oxide film is used as the interlayer insulating film 30 in the second embodiment, the silicon nitride film that is difficult to be etched becomes thick. Is preventing. Therefore, the contact hole for the peripheral circuit, which is opened when forming the peripheral circuit of the capacitor, can be formed more easily than in the above-described second conventional technique in which the stopper layer has two layers. In other words, it is possible to reduce the deterioration of the contact performance between the lower electrode 9 and the contact plug 3 with the same thickness as that of the stopper layer 4 of the above-mentioned first conventional technique. As a result, when forming the peripheral circuit of the capacitor,
The contact hole for the peripheral circuit can be opened by the same means as in the first conventional technique.

Further, in the second embodiment, since the upper surface 23 of the protruding portion 13 of the contact plug 3 is located above the surface 12 of the interlayer insulating film 2, similar to the above-described first embodiment. Even if overetching is performed when the contact hole 7 is opened, the interlayer insulating film 2 is less likely to be etched. As a result, deterioration of contact performance between the lower electrode 9 and the contact plug 3 due to overetching can be reduced.

Embodiment 3. 22 to 31 are cross-sectional views showing the manufacturing process of the capacitor according to the third embodiment of the present invention, and one of the capacitors formed in an array shape, as in the above-described first and second embodiments. Focusing on one, the manufacturing process is shown.

First, the interlayer insulating film 2 is formed on the substrate 1,
Inside the interlayer insulating film 2, a contact plug 3 that is in electrical contact with the substrate 1 is formed (FIG. 22). At this time,
The upper surface of the structure obtained in the step shown in FIG. 22 is planarized by the CMP method, and the upper surface 23 of the contact plug 3 is exposed from the interlayer insulating film 2. The upper surface 23 of the contact plug 3 and the surface 12 of the interlayer insulating film 2 are located on substantially the same plane.

Next, the stopper layer 24 is covered with 500 to 10 by covering the surface 12 of the interlayer insulating film 2 and the contact plug 3.
00Å is formed (Fig. 23). Here, the stopper layer 24
Is, for example, a silicon oxide film formed by plasma CVD using TEOS as a raw material. Then, the dummy inter-layer film 15 is covered with the surface 45 of the stopper layer 24.
Approximately 000Å, and further, on the dummy interlayer film 15,
A silicon oxide film 25 serving as a mask material for opening a dummy interlayer film 15 to be described later is formed in a thickness of 500 to 1000 liters (FIG. 24). At this time, the dummy interlayer film 15 is, for example,
It is composed of an organic polymer (polyallyl ether) such as SilK (registered trademark) and FLARE (registered trademark), and these materials are called “low-k materials”. Further, the silicon oxide film 25 is formed by the plasma CVD method using, for example, TEOS as a raw material, similarly to the stopper layer 24. The heat resistance of SilK and FLARE used as the material of the dummy interlayer film 15 is 300 to 400.
Since the temperature is 0 ° C., the silicon oxide film 25 on the dummy interlayer film 15 is formed by the plasma CVD method instead of the low pressure CVD method that is generally performed at a high temperature.

Next, using the photolithography technique,
The silicon oxide film 25 is patterned. Specifically, a resist 6 is formed on the silicon oxide film 25, and the resist 6 is patterned. Then resist 6
The silicon oxide film 25 is etched by using the as a mask to pattern the silicon oxide film 25 (FIG. 25).
Then, the resist 6 is ashed by oxygen plasma, for example, and at the same time, the patterned silicon oxide film 2 is ashed.
5 is used as a mask to open the dummy interlayer film 15 (FIG. 2).
6). Since the dummy interlayer film 15 is made of, for example, an organic polymer, it can be dry-etched with oxygen plasma.

Next, using the opened dummy interlayer film 15 as a mask, fluorine-based plasma is used to form the stopper layer 24.
And a contact hole 7 reaching the contact plug 3 is formed. At the same time when the stopper layer 24 is opened, the silicon oxide film 25 is removed (FIG. 27). In other words, it is a step of opening the contact hole 7 reaching the contact plug 3 in the dummy interlayer film 15 and the stopper layer 24.

A conductive layer 8 is formed in the contact hole 7 and the dummy interlayer film 15 formed as described above, for example, by the CVD method (FIG. 28). Then, the conductive layer 8 is etched by dry etching or CMP to leave the conductive layer 8 only in the contact hole 7 and form the lower electrode 9 of the capacitor in the contact hole 7 (FIG. 29).

Next, using the stopper layer 24 as an etching stopper, the dummy interlayer film 15 is selectively removed by dry etching using oxygen plasma to expose the pillar-shaped lower electrode 9 (FIG. 30). Then, the dielectric film 20 is formed so as to cover the surfaces of the lower electrode 9 and the stopper layer 24 in the shape of a leaflet, and the upper electrode 19 is formed on the dielectric film 20.
Are formed to complete the capacitor (FIG. 31).

According to the method of manufacturing a capacitor according to the third embodiment shown in FIGS. 22 to 31 described above, since the dummy interlayer film 15 is made of, for example, an organic polymer, it is dummy-etched by using oxygen plasma. Interlayer film 15
Can be selectively removed. Therefore, voids in the interlayer insulating film 2 that occur when the dummy interlayer film 15 is removed with hydrofluoric acid do not occur in the method of manufacturing a capacitor according to the third embodiment. As a result, the deterioration of the contact performance between the contact plug 3 and the lower electrode 9 caused by etching the dummy interlayer film 15 can be eliminated.

Fourth Embodiment 32 to 40 are cross-sectional views showing the manufacturing process of the capacitor according to the fourth embodiment of the present invention, and one of the capacitors formed in an array, as in the above-described first to third embodiments. Focusing on one, the manufacturing process is shown.

First, the interlayer insulating film 2 is formed on the substrate 1,
A contact plug 3 that is in electrical contact with the substrate 1 is formed inside the interlayer insulating film 2 (FIG. 32). At this time,
The upper surface of the structure obtained in the step shown in FIG. 32 is planarized by the CMP method, and the upper surface 23 of the contact plug 3 is exposed from the interlayer insulating film 2. The upper surface 23 of the contact plug 3 and the surface 12 of the interlayer insulating film 2 are located on substantially the same plane.

Next, the stopper layer 34 is covered with 500 to 10 by covering the surface 12 of the interlayer insulating film 2 and the contact plug 3.
00Å (Fig. 33). Here, the stopper layer 34
Is, for example, a silicon oxide film formed by plasma CVD using TEOS as a raw material. Then, the dummy interlayer film 25 is formed on the surface 48 of the stopper layer 34 by covering the surface 48.
Form about 000Å (Fig. 34). At this time, the dummy interlayer film 25 is made of, for example, silicon (polysilicon or amorphous silicon) or silicon nitride.

Next, using the photolithography technique,
The contact hole 7 is opened in the dummy interlayer film 25 and the stopper layer 34. Specifically, a resist 6 is formed on the dummy interlayer film 25, the resist 6 is patterned, and the dummy interlayer film 25 and the stopper layer 34 are dry-etched using the resist 6 as a mask to reach the contact plug 3. The hole 7 is opened (FIG. 35).
Then, the resist 6 used for forming the contact hole 7 is removed (FIG. 36).

A conductive layer 8 is formed in the contact hole 7 and the dummy interlayer film 25 formed as described above, for example, by the CVD method (FIG. 37). Then, the conductive layer 8 is etched by dry etching or the CMP method to leave the conductive layer 8 only in the contact hole 7 and form the lower electrode 9 of the capacitor in the contact hole 7 (FIG. 38).

Next, using the stopper layer 34 as an etching stopper, the dummy interlayer film 25 is selectively removed to expose the pillar-shaped lower electrode 9 (FIG. 39). At this time,
If the dummy interlayer film 25 is made of, for example, silicon, the dummy interlayer film 25 is removed by wet etching using a mixed solution of hydrofluoric acid and nitric acid. The dummy interlayer film 25 is removed by wet etching using phosphoric acid. Then, the dielectric film 20 is formed so as to cover the surfaces of the lower electrode 9 and the stopper layer 34 in the shape of a leaflet, and the upper electrode 19 is further formed on the dielectric film 20 to complete the capacitor (FIG. 4).
0).

According to the method of manufacturing a capacitor according to the fourth embodiment shown in FIGS. 32 to 40 described above, since dummy interlayer film 25 is made of, for example, silicon (polysilicon or amorphous silicon), hydrofluoric acid and nitric acid are added. The dummy interlayer film 25 can be selectively removed by wet etching using the mixed solution of.

A mixed solution of hydrofluoric acid and nitric acid is more difficult to etch a silicon oxide film than hydrofluoric acid. Since the interlayer insulating film 2 is, for example, a silicon oxide film, even if the mixed liquid of hydrofluoric acid and nitric acid permeates the interlayer insulating film 2 when the dummy interlayer film 25 is etched, it is more than that when hydrofluoric acid is used. The generation of voids in the interlayer insulating film 2 can be reduced. As a result, it is possible to reduce the deterioration of the contact performance between the contact plug and the lower electrode that occurs when removing the dummy interlayer film 25.

Since the dummy interlayer film 25 is made of, for example, silicon nitride, the dummy interlayer film 2 is formed by using hot phosphoric acid.
5 can be selectively removed by wet etching. Then, like the mixed solution of hydrofluoric acid and nitric acid, hot phosphoric acid is more difficult to etch the silicon oxide film than hydrofluoric acid. Therefore, even if the hot phosphoric acid permeates the interlayer insulating film 2 when the dummy interlayer film 25 is etched, the generation of voids in the interlayer insulating film 2 can be reduced more than in the case where hydrofluoric acid is used. As a result, it is possible to reduce the deterioration of the contact performance between the contact plug and the lower electrode that occurs when removing the dummy interlayer film 25.

[0065]

According to the method of manufacturing a capacitor of the first aspect of the present invention, after the step (e), the dummy interlayer film is usually removed with hydrofluoric acid. Less likely to soak into the insulating film. Specifically, when the protrusion distance of the contact plug from the surface of the interlayer insulating film is longer than the distance in the thickness direction of the stopper layer, the stopper layer covers the side surface of the contact plug protrusion in the present invention. The contact distance between the side surface of the protruding portion of the contact plug and the stopper layer is longer than the distance in the thickness direction of the stopper layer. When the dummy interlayer film formed covering the surface of the stopper layer is removed with hydrofluoric acid, the hydrofluoric acid permeates the interlayer insulating film through the gap between the side surface of the protruding portion of the contact plug and the stopper layer. . Therefore, the permeation path of the hydrofluoric acid is longer than the distance in the thickness direction of the stopper layer. Therefore, the hydrofluoric acid seepage route in the present invention is longer than that in the conventional technique in which the hydrofluoric acid seepage route is the same as the distance in the thickness direction of the stopper layer, so that the hydrofluoric acid is less likely to seep into the interlayer insulating film. Therefore, the generation of voids in the interlayer insulating film can be reduced. As a result, it is possible to reduce the deterioration of the contact performance between the lower electrode and the contact plug.

Further, in the present invention, since the stopper layer which is generally harder to open than the interlayer insulating film is one layer, it is possible to form the peripheral circuit of the capacitor more than the conventional technique in which the stopper layer is two layers. A contact hole for the peripheral circuit to be opened can be easily formed.

According to the method of manufacturing a capacitor of the second aspect of the present invention, after the step (g), the dummy interlayer film is usually removed with hydrofluoric acid. It becomes difficult to soak into. Specifically, when the protruding distance from the surface of the interlayer insulating film in the protruding portion of the contact plug is longer than the distance in the thickness direction of the stopper layer,
Since the stopper layer is formed so as to cover the side surface of the protruding portion of the contact plug, the contact distance between the side surface of the protruding portion of the contact plug and the stopper layer is longer than the distance in the thickness direction of the stopper layer. When the dummy interlayer film formed covering the surface of the stopper layer is removed with hydrofluoric acid, the hydrofluoric acid permeates the interlayer insulating film through the gap between the side surface of the protruding portion of the contact plug and the stopper layer. . for that reason,
The route for the hydrofluoric acid to soak in when removing the dummy interlayer film is
It is longer than the distance in the thickness direction of the stopper layer. Therefore, the hydrofluoric acid seepage route in the present invention is longer than that in the conventional technique in which the hydrofluoric acid seepage route is the same as the distance in the thickness direction of the stopper layer, so that the hydrofluoric acid is less likely to seep into the interlayer insulating film. Therefore, the generation of voids in the interlayer insulating film can be reduced. As a result, it is possible to reduce the deterioration of the contact performance between the lower electrode and the contact plug.

Further, in the present invention, when a material which is easier to etch than the stopper layer is used as the second interlayer insulating film, the peripheral circuit of the capacitor can be formed more easily than the prior art in which the stopper layer has two layers. It is possible to easily form the contact hole for the peripheral circuit which is opened in the.

According to the method for manufacturing a capacitor of the third aspect of the present invention, the protrusion of the contact plug has a protrusion distance from the surface of the interlayer insulating film longer than the distance in the thickness direction of the stopper layer. For the same reason as in the first and second aspects of the invention, it is possible to reliably reduce the generation of voids in the interlayer insulating film. Therefore, the deterioration of the contact performance between the contact plug and the lower electrode is surely reduced.

Further, according to the method of manufacturing a capacitor according to the fourth aspect of the present invention, if, for example, an organic polymer is used as the dummy interlayer film, in the step (f), the dummy etching is performed by dry etching using oxygen plasma. The interlayer film can be selectively removed. Therefore, no voids in the interlayer insulating film are generated when the dummy interlayer film is removed with hydrofluoric acid. As a result, the deterioration of the contact performance between the contact plug and the lower electrode caused by etching the dummy interlayer film can be eliminated.

According to the method of manufacturing a capacitor of the fifth aspect of the present invention, since the dummy interlayer film is made of an organic polymer, the dummy interlayer film is selectively secured by dry etching using oxygen plasma. Can be removed. Therefore, for the same reason as the invention according to claim 4, deterioration of the contact performance between the contact plug and the lower electrode caused by etching the dummy interlayer film is surely eliminated.

According to the method for manufacturing a capacitor of the sixth aspect of the present invention, when, for example, silicon (polysilicon, amorphous silicon) is used as the dummy interlayer film, hydrofluoric acid and nitric acid are generated in the step (f). The dummy interlayer film can be selectively removed by wet etching using the mixed solution of. Further, the mixed solution of hydrofluoric acid and nitric acid is more difficult to etch the silicon oxide film than hydrofluoric acid. Since the interlayer insulating film is usually a silicon oxide film,
Even if the mixed solution of hydrofluoric acid and nitric acid permeates the interlayer insulating film when the dummy interlayer film is etched, it is possible to reduce the generation of voids in the interlayer insulating film as compared with the case where hydrofluoric acid is used. As a result, it is possible to reduce the deterioration of the contact performance between the contact plug and the lower electrode that occurs when the dummy interlayer film is removed.

According to the method of manufacturing a capacitor of the seventh aspect of the present invention, since the dummy interlayer film is made of silicon, the dummy interlayer film is selectively etched by the wet etching in the step (f). Can be removed. Therefore, for the same reason as the invention according to claim 6, it is possible to reliably reduce the generation of voids in the interlayer insulating film, as compared with the case of using hydrofluoric acid. As a result, the deterioration of the contact performance between the contact plug and the lower electrode, which occurs when the dummy interlayer film is removed, is reliably reduced.

According to the method of manufacturing a capacitor of the eighth aspect of the present invention, if, for example, silicon nitride is used as the dummy interlayer film, hot phosphoric acid is used to form the dummy interlayer film in the step (f). It can be selectively removed by wet etching. Further, hot phosphoric acid is more difficult to etch the silicon oxide film than hydrofluoric acid. Since the interlayer insulating film is usually a silicon oxide film, even when hot phosphoric acid permeates the interlayer insulating film when etching the dummy interlayer film, more voids are generated in the interlayer insulating film than when hydrofluoric acid is used. Can be reduced. As a result, it is possible to reduce the deterioration of the contact performance between the contact plug and the lower electrode that occurs when the dummy interlayer film is removed.

Further, according to the method of manufacturing a capacitor of the ninth aspect of the present invention, since the dummy interlayer film is made of silicon nitride, the dummy interlayer film can be selectively removed reliably by wet etching. . Therefore, for the same reason as in the invention according to claim 8, the generation of voids in the interlayer insulating film can be reliably reduced as compared with the case of using hydrofluoric acid. As a result, the deterioration of the contact performance between the contact plug and the lower electrode, which occurs when the dummy interlayer film is removed, is reliably reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a capacitor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the capacitor according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the capacitor according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the capacitor according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the capacitor according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the capacitor according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the capacitor according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the manufacturing process of the capacitor according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the manufacturing process of the capacitor according to the first embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the manufacturing process of the capacitor according to the first embodiment of the present invention.

FIG. 11 is a cross-sectional view showing the manufacturing process of the capacitor according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view showing the manufacturing process of the capacitor according to the first embodiment of the present invention.

FIG. 13 is a cross-sectional view showing the manufacturing process of the capacitor according to the second embodiment of the present invention.

FIG. 14 is a cross-sectional view showing the manufacturing process of the capacitor according to the second embodiment of the present invention.

FIG. 15 is a cross-sectional view showing the manufacturing process of the capacitor according to the second embodiment of the present invention.

FIG. 16 is a cross-sectional view showing the manufacturing process of the capacitor according to the second embodiment of the present invention.

FIG. 17 is a cross-sectional view showing the manufacturing process of the capacitor according to the second embodiment of the present invention.

FIG. 18 is a cross-sectional view showing the manufacturing process of the capacitor according to the second embodiment of the present invention.

FIG. 19 is a cross-sectional view showing the manufacturing process of the capacitor according to the second embodiment of the present invention.

FIG. 20 is a cross-sectional view showing the manufacturing process of the capacitor according to the second embodiment of the present invention.

FIG. 21 is a cross-sectional view showing the manufacturing process of the capacitor according to the second embodiment of the present invention.

FIG. 22 is a cross-sectional view showing the manufacturing process of the capacitor according to the third embodiment of the present invention.

FIG. 23 is a cross-sectional view showing the manufacturing process of the capacitor according to the third embodiment of the present invention.

FIG. 24 is a cross-sectional view showing the manufacturing process of the capacitor according to the third embodiment of the present invention.

FIG. 25 is a cross-sectional view showing the manufacturing process of the capacitor according to the third embodiment of the present invention.

FIG. 26 is a cross-sectional view showing the manufacturing process of the capacitor according to the third embodiment of the present invention.

FIG. 27 is a cross-sectional view showing the manufacturing process of the capacitor according to the third embodiment of the present invention.

FIG. 28 is a cross-sectional view showing the manufacturing process of the capacitor according to the third embodiment of the present invention.

FIG. 29 is a cross-sectional view showing the manufacturing process of the capacitor according to the third embodiment of the present invention.

FIG. 30 is a cross-sectional view showing the manufacturing process of the capacitor according to the third embodiment of the present invention.

FIG. 31 is a cross-sectional view showing the manufacturing process of the capacitor according to the third embodiment of the present invention.

FIG. 32 is a cross-sectional view showing the manufacturing process of the capacitor according to the fourth embodiment of the present invention.

FIG. 33 is a cross-sectional view showing the manufacturing process of the capacitor according to the fourth embodiment of the present invention.

FIG. 34 is a cross-sectional view showing the manufacturing process of the capacitor according to the fourth embodiment of the present invention.

FIG. 35 is a cross-sectional view showing the manufacturing process of the capacitor according to the fourth embodiment of the present invention.

FIG. 36 is a cross-sectional view showing the manufacturing process of the capacitor according to the fourth embodiment of the present invention.

FIG. 37 is a cross-sectional view showing the manufacturing process of the capacitor according to the fourth embodiment of the present invention.

FIG. 38 is a cross-sectional view showing the manufacturing process of the capacitor according to the fourth embodiment of the present invention.

FIG. 39 is a cross-sectional view showing the manufacturing process of the capacitor according to the fourth embodiment of the present invention.

FIG. 40 is a cross-sectional view showing the manufacturing process of the capacitor according to the fourth embodiment of the present invention.

FIG. 41 is a cross-sectional view showing the manufacturing process of the capacitor according to the first conventional technique.

FIG. 42 is a cross-sectional view showing the manufacturing process of the capacitor according to the first conventional technique.

FIG. 43 is a cross-sectional view showing the manufacturing process of the capacitor in the first conventional technique.

FIG. 44 is a cross-sectional view showing the manufacturing process of the capacitor in the first conventional technique.

FIG. 45 is a cross-sectional view showing the manufacturing process of the capacitor in the first conventional technique.

FIG. 46 is a cross-sectional view showing the manufacturing process of the capacitor according to the first conventional technique.

FIG. 47 is a cross-sectional view showing the manufacturing process of the capacitor according to the first conventional technique.

FIG. 48 is a cross-sectional view showing the manufacturing process of the capacitor according to the first conventional technique.

FIG. 49 is a cross-sectional view showing the manufacturing process of the capacitor in the first conventional technique.

FIG. 50 is a cross-sectional view showing a state of voids generated in the interlayer insulating film of the capacitor in the first conventional technique.

FIG. 51 is a cross-sectional view showing the manufacturing process of the capacitor according to the second conventional technique.

FIG. 52 is a cross-sectional view showing the manufacturing process of the capacitor according to the second conventional technique.

FIG. 53 is a cross-sectional view showing the manufacturing process of the capacitor according to the second conventional technique.

FIG. 54 is a cross-sectional view showing the manufacturing process of the capacitor according to the second conventional technique.

[Explanation of symbols]

2,30 Interlayer insulation film, 3 contact plugs, 4,2
4,34 stopper layer, 5,15,25 dummy interlayer film, 7 contact hole, 9 lower electrode, 12,4
0,41,45,48 surface, 13 protrusions, 23,5
0 top, 33 sides.

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 4M104 BB01 BB04 BB06 BB18 CC01                       DD06 DD08 DD16 DD17 DD65                       DD75 EE08 EE14 EE17 FF06                       FF40 GG16 GG19 HH12 HH20                 5F033 JJ04 JJ07 JJ19 JJ33 KK01                       NN19 NN37 PP06 QQ08 QQ09                       QQ10 QQ11 QQ12 QQ19 QQ25                       QQ28 QQ37 QQ48 RR01 RR04                       RR06 RR21 SS04 SS11 SS13                       SS15 TT02 VV10 VV16 XX00                       XX01 XX24                 5F083 AD56 JA39 JA40 MA06 MA18                       NA08 PR40

Claims (9)

[Claims] 1. A step of: (a) forming a contact plug having a protrusion protruding from a surface of an interlayer insulating film in the interlayer insulating film; and (b) a side surface and an upper surface of the protrusion of the contact plug, and Forming a stopper layer to cover the surface of the interlayer insulating film; (c) forming a dummy interlayer film to cover the surface of the stopper layer; (d) the dummy interlayer film and the stopper A method of manufacturing a capacitor, comprising: forming a contact hole in the layer, the contact hole reaching the upper surface of the protruding portion of the contact plug; and (e) forming a lower electrode in the contact hole. 2. A step of: (a) forming a contact plug having a protrusion protruding from the surface of the interlayer insulating film in the interlayer insulating film; and (b) a side surface and an upper surface of the protrusion of the contact plug, and Forming a stopper layer by covering the surface of the interlayer insulating film; (c) forming a second interlayer insulating film by covering the surface of the stopper layer; (d) forming the stopper layer and Removing the second interlayer insulating film to planarize the top surface of the structure obtained in step (c) to expose the top surface of the protrusion of the contact plug; and (e) Forming a dummy interlayer film by covering the surface of the stopper layer obtained in step (d) and the upper surface of the protruding portion of the contact plug; and (f) contacting the dummy interlayer film with the contact. The The method of manufacturing a capacitor comprising the steps of: opening a contact hole reaching the upper surface of the projecting portion of the grayed, and forming a lower electrode (g) the contact hole. 3. The projecting portion of the contact plug,
The method of manufacturing a capacitor according to claim 1, wherein a protrusion distance of the interlayer insulating film from the surface is longer than a distance in the thickness direction of the stopper layer. 4. A step of: (a) forming a contact plug exposed from the interlayer insulating film in the interlayer insulating film; and (b) forming a stopper layer covering the surfaces of the contact plug and the interlayer insulating film. And (c) forming a dummy interlayer film so as to cover the surface of the stopper layer, and (d) forming a contact hole reaching the contact plug in the dummy interlayer film and the stopper layer. , (E) a step of forming a lower electrode in the contact hole, and (f) after the step (e), the dummy interlayer film is selectively removed by dry etching using the stopper layer as an etching stopper. A method of manufacturing a capacitor, comprising: 5. The method of manufacturing a capacitor according to claim 4, wherein the dummy interlayer film is made of an organic polymer. 6. A step of: (a) forming a contact plug exposed from the interlayer insulating film in the interlayer insulating film; and (b) forming a stopper layer covering the surfaces of the contact plug and the interlayer insulating film. And (c) forming a dummy interlayer film so as to cover the surface of the stopper layer, and (d) forming a contact hole reaching the contact plug in the dummy interlayer film and the stopper layer. And (e) a step of forming a lower electrode in the contact hole, and (f) after the step (e), using the mixed solution of hydrofluoric acid and nitric acid, the stopper layer as an etching stopper, and the dummy And a step of selectively removing the interlayer film by wet etching. 7. The dummy interlayer film is made of silicon,
A method for manufacturing the capacitor according to claim 6. 8. A step of: (a) forming a contact plug exposed from the interlayer insulating film in the interlayer insulating film; and (b) forming a stopper layer covering the surfaces of the contact plug and the interlayer insulating film. And (c) forming a dummy interlayer film so as to cover the surface of the stopper layer, and (d) forming a contact hole reaching the contact plug in the dummy interlayer film and the stopper layer. And (e) a step of forming a lower electrode in the contact hole, and (f) after the step (e), wet phosphoric acid is used to etch the dummy interlayer film by using the stopper layer as an etching stopper. The method for manufacturing a capacitor, comprising the step of selectively removing. 9. The method of manufacturing a capacitor according to claim 8, wherein the dummy interlayer film is made of silicon nitride.