JP2003015914A - Method for producing test program for evaluating information processing unit, device and program describing processing therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for precisely evaluating an information processing unit prior to its completion. SOLUTION: An original program execution machine 1 is a computer on which an OS is installed, and executes a given application program. Execution history information 2 represents the execution of an instruction and memory access in the original program execution machine 1 in chronological order. An analysis tool 3 produces basic data 4 of load module format for reproducing the operation of the original program execution machine 1 by analyzing the execution history information 2. Regarding the processing item, among processing items executed with the original program execution machine 1, that a simulator 8 can not execute, correction data 5 are produced. A benchmark program 7 is produced from the basic data 4 and the correction data 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for creating a test program for evaluating an information processing apparatus, and more particularly to a method and apparatus for creating a benchmark program.

[0002]

2. Description of the Related Art Various information processing apparatuses (mainly computers) are usually subjected to various performance evaluations before being shipped. For example, at the time of hardware development, a logic simulator or the like is used to verify the logic of the CPU to be mounted on the information processing apparatus. In addition, when the device is completed, the performance of the entire device is evaluated by measuring the processing time when the device executes a standard program. The latter evaluation is often called "benchmark test", and the program used in the benchmark test is called "benchmark program".

[0003]

However, since the logic simulator has the main purpose of verifying the logic, it does not have a sufficient function for evaluating the performance of the information processing device. For example, an OS (Operat
ing System) cannot be installed, so it is not possible to evaluate the behavior when an application is executed on the OS using a logic simulator. Further, since the logic simulator cannot normally connect an external device such as an external memory, it cannot evaluate an operation including an I / O instruction.

On the other hand, in the benchmark test, a predetermined program (benchmark program) is executed by using the completed information processing apparatus, so that the execution speed and the like can be measured. However, the processing executed in the existing benchmark test is generally relatively simple, and it is difficult to evaluate the performance when the application program to be actually used is executed. Therefore, if you want to accurately evaluate the performance when executing the application program that should actually be used,
It is necessary to actually execute the application program. However, in this case, it is usually necessary to perform the test with the external device connected to the information processing apparatus to be evaluated. For example, when evaluating the operation when a database-type application program is executed, it is necessary to perform a test with the external storage device connected to the information processing device. Therefore, it takes a considerable amount of time and money to perform the above test.

Further, since the benchmark test is performed after the information processing apparatus to be evaluated is completed, if it is found that a certain performance cannot be obtained at that time, it takes much time and effort to change the design. Will end up. That is, the product development time becomes long.

As described above, conventionally, it was not possible to accurately evaluate the performance of an information processing apparatus before it was completed. An object of the present invention is to make it possible to accurately evaluate the performance of an information processing device before it is completed.

[0007]

A method of the present invention is a method for creating a test program for evaluating an information processing apparatus, in which the original program is executed using a computer having a processor and a memory. Detect the instructions executed by the processor and the contents of access to the memory, store the detected information in time series as execution history information, and store the instruction execution sequence executed by the computer based on the execution history information. Create a load module format program to reproduce.

The load module format program includes not only an instruction when the original program is executed, but also memory access contents. Therefore,
When this load module is provided to the information processing device to be evaluated, the device can faithfully reproduce the operation of the computer. Further, if the OS is installed in the computer, the load module also includes the instruction of the OS. Therefore, the operation of the computer can be reproduced even if the OS to be evaluated is not installed in the information processing apparatus.

According to another aspect of the present invention, there is provided a test program creating method, wherein an instruction code corresponding to an instruction executed by the processor when the original program is executed by using a computer including a processor and a memory, and the instruction. Command information, binary data written to or read from the memory, and access information indicating access contents to the memory are detected, and the detected information is stored in time series as execution history information. A program in a load module format is created by analyzing the execution history information in time series and writing the above instruction code based on the above instruction information into the prepared memory space and writing the above binary data based on the above access information. To do.

Also in this method, basically, similar to the above-mentioned method, the operation of the computer is faithfully reproduced in the information processing apparatus to be evaluated. In the above method, when the computer executes the first instruction, which is an instruction that cannot be executed by the device to which the test program is given, a processing routine that substitutes the operation of the computer due to the first instruction. A program may be created and written in the memory space, and an instruction for calling the processing routine program may be written in the memory space instead of the first instruction. In this case, the instruction that cannot be executed by the information processing apparatus to be evaluated is replaced with the processing routine program that can be executed by the information processing apparatus to be evaluated, so that the operation of the computer is faithfully reproduced in the information processing apparatus to be evaluated.

In the above method, a second instruction, which is an instruction that may cause a different operation when executed by the computer and when executed by an apparatus to which the test program is given, is executed by the computer. When executed, the condition referenced by the processor when the second instruction is executed in the computer is written in the memory space, and an instruction for calling the condition instead of the second instruction is issued in the memory space. You may write in. in this case,
Even if the computer and the information processing apparatus to be evaluated have different execution speeds or operating environments from each other, the two are matched, so that the operation of the computer is faithfully reproduced in the information processing apparatus to be evaluated. .

Further, in the above method, the first operation is an operation that cannot be performed by the device to which the test program is given.
When the above operation is performed by the computer, the third instruction, which is an instruction executed near the timing when the first operation is performed in the computer, is replaced with an instruction sequence switching instruction, and the memory space is changed. Alternatively, an instruction for switching the instruction sequence may be linked with the instruction for switching the instruction sequence by creating a processing routine program that substitutes the first operation and writing it in the memory space.
In this case, the operation that cannot be executed by the information processing apparatus to be evaluated is replaced with the processing routine program that can be executed by the information processing apparatus, so that the operation of the computer is faithfully reproduced in the information processing apparatus to be evaluated.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram for explaining an overview of the program creating method of this embodiment. In this embodiment, a test program for evaluating the information processing device is created. Specifically, a test program for evaluating the performance of a computer (mainly computer hardware) is created. Hereinafter, this program is referred to as a "benchmark program".

The original program execution machine 1 has a predetermined operating system (OS).
em) is implemented by a computer that has been installed and executes a given application program. Then, every time each instruction is executed or each time the memory is accessed, the information indicating the operation is accumulated in time series to create the execution history information 2.
A program (including the OS) executed by the original program execution machine 1 may be called an “original program”.

The analysis tool 3 analyzes the execution history information 2 and generates basic data 4 and correction data 5. Here, the basic data 4 is data that reproduces the instruction execution sequence executed by the original program execution machine 1. Further, the correction data 5 is data for correcting the basic data 4. The correction data 5 is processed into an appropriate state by the correction tool 6.

The benchmark program 7 is composed of basic data 4 and correction data 5 processed by the correction tool 6. The benchmark program 7 is a load module that represents the operation of the original program execution machine 1.

The simulator 8 is an alternative device to the information processing device to be evaluated, is provided with the benchmark program 7, and operates according to the benchmark program 7. The simulator 8
May be an unfinished information processing device, a logic simulator, or the like. In addition, the OS does not necessarily have to be installed in the simulator 8. further,
An external device is not connected to the simulator 8.

The benchmark program 7 is a load module and is given to the simulator 8. here,
This load module includes not only the instruction sequence of the application program executed by the original program execution machine 1, but also the instruction sequence of the OS installed in the original program execution machine 1. Therefore, even if the OS is not installed in the simulator 8, when the benchmark program 7 is given, the instruction sequence executed by the original program execution machine 1 is reproduced in the simulator 8. Further, when the operation related to the external device occurs in the original program execution machine 1, the operation is represented in a format that the simulator 8 can process using the correction data 5. Therefore, the operation related to the external device can be evaluated using the simulator 8 to which the external device is not connected.

FIG. 2 is a block diagram of the original program execution machine 1. Original program execution machine 1
Is at least a CPU (Central Processing Unit)
11 and a memory 12.

The CPU 11 executes a program stored in the memory 12 to receive data, perform an arithmetic operation using the data, and provide a series of operations for outputting the arithmetic result. The CPU 11
Has a plurality of registers.

The memory 12 is a storage area accessed by the CPU 11 and stores an OS program 13, an application program 14, and various data. Here, although the OS program 13 is not particularly limited, the same OS as the OS to be installed in the information processing apparatus to be evaluated or a compatible one is used. In addition, the application program 14
Is preferably executed by the information processing device to be evaluated.

The tracer 15 detects the operation of the CPU 11 and the access to the memory 12, and outputs the detection result in time series. Note that the tracer 15 is stored in the memory 12 in the example shown in FIG. 2, but may be provided in another storage area.

The external device 21 is a device connected to the original program execution machine 1, and is, for example,
It is an input device such as an external storage device or a keyboard. Figure 3
3 is a flowchart showing the operation of the tracer 15.
This process is activated, for example, every time the CPU 11 performs some process or whenever the memory 12 is accessed.

In step S1, it is checked whether or not an instruction has been executed by the CPU 11. Here, the “instruction” is not only the instruction of the application program 14 but also the OS.
It also includes instructions for processing. When the CPU 11 executes the instruction, the corresponding instruction record is created in step S2. Here, the instruction record is composed of, for example, the following information. -Instruction code-Instruction storage address (real address, logical address) -Write destination register information-Write destination address (real address, logical address) -Write data length-Reference register information-Reference address (real address, logical address) -Reference The data length “instruction code” is the instruction itself given to the CPU 11, and is expressed in machine language. The instruction code is obtained, for example, by extracting the data string written in the instruction register included in the CPU 11.
The “instruction storage address” is an address where the instruction is stored. The “write destination register information” identifies the register to which the data is written by the instruction. The “write destination address” and the “write data length” are the address at which the data is written and the data length of the data when the data is written to the memory 12 by the instruction, respectively. The “reference register information” identifies a register to which data is to be referred by the instruction.
The “reference address” and the “reference data length” are the address where the data is stored and the data length of the data when the data in the memory 12 is referenced by the instruction, respectively. The method of detecting the “instruction storage address” to the “reference data length” can be realized by existing technology.

In step S3, it is checked whether the register provided in the CPU 11 has been updated. If one or more registers are updated, the corresponding register record is created in step S4. Here, the register record includes, for example, information for identifying the updated register and data (register value) newly written in the register.

In step S5, it is checked whether or not an interrupt to the CPU 11 has occurred. Then, when an interrupt to the CPU 11 occurs, a corresponding interrupt record is created in step S6. Here, the interruption is, in this embodiment, I / O interruption, program interruption, external interruption,
Assume privilege (SVC) interrupts. Below is an example of an interrupt record corresponding to each interrupt. I / O interrupt-PSW value before interrupt generation-Interrupt code program interrupt-PSW value before interrupt generation-Instruction length-Interrupt code-Code for judging exception type-Phenomenon identification code External interrupt-Before interrupt generation PSW value, instruction length, phenomenon identification code privilege (SVC) interrupt, PSW value before interrupt occurrence, PSW value after interrupt occurrence, instruction length, phenomenon identification code In step S7, it is checked whether or not the memory 12 is accessed. . Here, the access includes an operation of writing data in the memory 12 and an operation of referring to the data stored in the memory 12. When the memory 12 is accessed, the corresponding memory data record is created in step S8. Here, the memory data record includes, for example, the following information. -Real address-Memory data-Data length-Access type "Real address" indicates the accessed real address.
“Memory data” is data written in the memory 12 or data read from the memory 12. The “data length” indicates the data length of the data written in the memory 12 or the data read from the memory 12. The “access type” identifies writing or reference.

In step S9, it is checked whether or not an instruction for updating various tables managed by the OS has been executed. Here, it is assumed that it is checked whether or not the instruction to update the address conversion table is executed. In addition,
Information for converting a logical address recognized by the CPU 11 into a real address on the memory 12 is registered in the address conversion table. Then, when the instruction to update the address conversion table is executed, the corresponding table reference record is created in step S10. Here, the table reference record is composed of, for example, the following information.・ Corresponding operation ・ Translated address ・ Table address ・ Data length "Corresponding operation" indicates the operation that requested address conversion.
Identify instruction fetch, data reference, and data write.
The “translation address” is a set of logical address and real address related to the conversion process. The “table address” is an address in which the referred address conversion table is stored. The “data length” is the data length of the data converted by the referenced address conversion table.

In step S11, it is checked whether or not the key information is set. The key information is information for managing each page that constitutes the storage area and is used by the OS. When the key information is set, the corresponding key information record is created in step S12. Here, the key information record includes, for example, the following information. The key information may be derived from the memory record, instruction record, and register value. -Access side key information-Instruction code-Access type (instruction fetch, operand read, operand write, operand number) -Memory access logical address-Memory access real address-Segment table start address-Segment table entry number-Data length , The tracer 15 receives instructions, memory data, when the original program is executed by the CPU 11.
Detect related information and create corresponding records. Then, the records successively created by the tracer 15 are stored in time series as the execution history information 2.

When the CPU 11 executes an instruction, the tracer 15 creates an instruction record corresponding to the instruction. For example, when a memory access occurs due to the instruction, the tracer 15 corresponds to the memory access. A memory data record is also created at the same time. That is, when the CPU 11 executes one instruction, the tracer 15 creates one or a plurality of records corresponding to the instruction.

Further, in the above-mentioned example, when the memory 12 is accessed, the corresponding memory data record is created, but when a certain data stored in the memory 12 is referred (read), it is analyzed. Tool 3 may create a memory data record only when the data is first referenced.

Further, when the memory 12 is updated according to a certain command, if the updated content can be easily guessed, the analysis tool 3 may create another record instead of the memory data record. Good. For example, in the case of a simple load instruction that simply loads the memory data stored in the memory 12 into a register, only the register record may be created instead of creating the memory data record. In this case, the operand address of the load instruction (reference address of the memory 12) is registered in this register record. At this time, the value stored in the load destination register after execution of the load instruction is registered in the register record, and this value matches the memory data stored in the operand address of the load instruction. The update content may be derived from the instruction record.

FIG. 4 shows an example of the execution history information 2.
The execution history information 2 is managed using a record number when it is stored in a file or the like. That is, the tracer 15
Each record created by is given a record number and stored in the order of creation. A record type is given to each record. In this embodiment, "01" and "0" are assigned to "instruction record", "register record" and "memory data record", respectively.
2 ”and“ 03 ”are assigned. Then, the information detected by the tracer 15 is directly stored as the execution information. In this embodiment, for example, the instruction record is stored in the record identified by “record number = 453”. Specifically, "01" is set to the record type of this record, and further, an instruction code detected by the tracer 15, various addresses, a data length, etc. are stored as execution information.

In the above embodiment, the information necessary for creating the execution history information 2 is collected by moving the tracer 15 on the actual machine, but it may be collected by another method. . For example, an architecture simulator may be used to collect the necessary information. Also, the information required to create the execution history information 2 differs depending on the device to be evaluated. That is, the information to be collected is determined depending on the OS installed in the evaluation target device, the instruction architecture of the CPU mounted in the evaluation target device, the system configuration of the evaluation target device, and the like.

The execution history information 2 created as described above is analyzed by the analysis tool 3. The operation of the analysis tool 3 will be described below. The analysis tool 3 sequentially analyzes each record of the execution history information 2 one by one, and writes the result in the initial memory space 30 shown in FIG. The initial memory space 30 is the basic memory space 3
1 and a correction memory space 32. Here, the basic memory space 31 is a storage area having the same size as the real space of the memory 12 included in the original program execution machine 1. The basic data 4 and the correction data 5 shown in FIG. 1 are written in the basic memory space 31 and the correction memory space 32, respectively.

Further, the analysis tool 3 has a register group 3 for reflecting the information registered in the register record.
3 is provided. The register group 33 includes the same number of registers as the CPU 11 of the original program execution machine 1, and is used when writing data to the initial memory space 30.

The analysis tool 3 sequentially writes the results obtained by analyzing each record of the execution history information 2 into the basic memory space 31. For example, when the instruction record is extracted, the analysis tool 3 uses the “instruction code” registered in the record as a key and the “instruction storage address (real address)” registered in the record as a basic memory. Write in the corresponding area in space 31. At this time, if there is data associated with the “instruction code”, that information is written in the area following the “instruction code”. As a result, the original program execution machine 1
The instruction code of the instruction executed by is written in the basic memory space 31. At this time, this instruction code is stored in the memory 12 and the basic memory space 31.
At the same address as each other.

For example, in the example shown in FIG. 6, the store instruction stored in the address "aaaa" of the memory 12 of the original program execution machine 1 is executed, and the instruction record corresponding to it is created. Then, this instruction record is analyzed, and accordingly, the basic memory space 3
The store instruction is written in the address "aaaa" of 1.

When writing the instruction code in the basic memory space 31 as described above, if some data is already stored in the corresponding area, the analysis tool 3
Does not execute the writing process. Here, the function of prohibiting overwriting can be realized by, for example, providing a table that manages the basic memory space 31 in units of bytes, and using the table to manage whether or not data is stored in each area. is there.

Similarly, the analysis tool 3 uses the execution history information 2
When the memory data record is extracted from, the "memory data" registered in the record is written in the corresponding area in the basic memory space 31 using the "real address" registered in the record as a key. As a result, the memory 12 of the original program execution machine 1
And the same memory data exists at the same address in the basic memory space 31.

The other types of records will be described later with reference to the flow chart shown later. In this way, the analysis tool 3 analyzes the execution history information 2 to determine whether the memory 1 of the original program execution machine 1 is to be analyzed.
The contents of 2 are reflected in the basic memory space 31 of the initial memory space 30. In this case, the same result can be obtained by copying the contents of the memory 12 into the basic memory space 31 at an arbitrary time.

By the way, the benchmark test of the present embodiment is intended to examine the performance of the information processing apparatus to be evaluated before it is completed. Therefore, when testing the device to be evaluated, a simulator (simulator 8 shown in FIG. 1) having the same specifications as the device is prepared, and the benchmark program of the present embodiment is executed by the simulator 8. The performance of the target device is estimated. Here, in this simulator 8,
A CPU included in the information processing apparatus to be evaluated or a processor equivalent thereto is mounted, but it is also assumed that the OS is not installed. In addition, the simulator 8
It is also assumed that the external device is not connected to. Therefore, the simulator 8 cannot execute some of the instructions or processes executed by the original program execution machine 1.

In the program creating method of this embodiment, among the instructions / processes executed by the original program execution machine 1, the instructions / processes that the simulator 8 cannot execute are replaced with the instructions / processes that the simulator 8 can execute. Try to solve the problem. Hereinafter, this replacement process may be referred to as “correction”. The correction data 5 shown in FIG. 1 is used for this correction process.

In the following embodiments, an asynchronous interrupt (including an I / O interrupt), an instruction or a process requiring correction,
We pick up I / O commands and commands that refer to dynamic information. Asynchronous Interrupt (No. 1) Here, in the original program execution machine 1, it is assumed that the memory 12 is updated by the I / O interrupt from the external device 21 (when new data is written in the memory 12). .

The asynchronous interrupt occurs regardless of the execution of the OS instruction or the application program instruction. That is, the update of the memory 12 by the I / O interrupt is performed while the job is being executed. At this time, this memory update is I
Recognized by the occurrence of an / O interrupt.

By the way, the I / O interrupt causes the memory 12
Is updated, the tracer 15 creates a corresponding interrupt record and memory data record. Therefore, the analysis tool 3 should basically perform the process of updating the initial memory space 30 according to these records. However, in reality, if the contents of the memory data record are reflected in the initial memory space 30,
The same result as the memory update executed in the original program execution machine 1 should be obtained.

FIG. 7 is a diagram for explaining the processing of the analysis tool 3 when a memory update occurs due to an I / O interrupt.
In this embodiment, in the original program execution machine 1, data A is written from the external device 21 to the address "bbbb" of the memory 12 by the I / O interrupt, and the interrupt record and the memory data record corresponding to the data A are created. In this case, the data A is written in the address "bbbb" of the basic memory space 31 according to the contents of the memory data record.

As described above, in the original program execution machine 1, the data A is written in the address "bbbb" of the memory 12 by the interruption from the external device 21. On the other hand, the data A is written in advance at the address "bbbb" of the basic memory space 31.

Here, the data stored in the initial memory space 30 is finally used as a benchmark program. Specifically, the instructions stored in the basic memory space 31 are sequentially executed by the simulator. At this time, assuming that the initial memory space 30 is created as shown in FIG. 7, at the start of the benchmark test, "b" of the basic memory space 31 is written.
This means that the data A has already been stored in the address "bbb". This state means that the data A has been written in the address "bbbb" regardless of the instruction stored in the basic memory space 31. Equivalent, that is, this state is "bbbb" due to an I / O interrupt from the external device 21.
It is substantially equivalent to writing the data A at the address. Therefore, the memory update by the I / O interrupt is realized by reflecting the contents of the memory data record in the initial memory space 30. That is, even when the external device 21 cannot be connected to the simulator 8, the same result as when the external device 21 is connected can be obtained in the benchmark test. There may be a case where the data A1 different from the data A exists at the address "bbbb" and the data A1 is changed to the data A by an I / O interrupt later. In this case, on the memory 31, the I / O
The above update is reflected when the instruction is issued. I / O instruction Here, it is assumed that the I / O instruction is executed in the original program execution machine 1 and the memory 12 is updated accordingly. This I / O command reads data from the external device 21 and stores it in the memory 1 for example.
2 is a command to write.

When an I / O command is executed in the original program execution machine 1, the tracer 15 causes the I / O command to execute the I / O command.
Create an instruction record corresponding to the / O instruction. Further, when the memory 12 is updated in accordance with this instruction, a memory data record including the updated memory data is created. Furthermore, the information (for example, register value, condition code, etc.) updated by executing the I / O instruction is registered in the corresponding record.

The analysis tool 3 writes the necessary information in the initial memory space 30 based on the above records.
Specifically, the memory data and various information updated by the I / O command are written in the correction memory space 32 as correction data. Further, the analysis tool 3 generates an interrupt attribute instruction instead of the I / O instruction and writes it in the corresponding address in the basic memory space 31. Here, this interrupt attribute command is a command for processing the correction data previously stored in the correction memory space 32.

FIG. 8 is a diagram for explaining the processing of the analysis tool 3 when the memory update by the I / O instruction occurs.
In this example, the original program execution machine 1 executes the I / O instruction stored in the address "cccc" of the memory 12 to write the data B in the address "dddd". At this time, the tracer 15 creates a corresponding record. And the analysis tool 3 first
The data B is written to a predetermined area in the correction memory space 32 using the memory data record. In FIG. 8, only the data B is written in the correction memory space 32, but actually, other related information is also stored together. Subsequently, the analysis tool 3 creates a processing routine program (sub-p) corresponding to the I / O instruction,
It is written in a predetermined area in the correction memory space 32. The following processing is described in this processing routine program. -Data B stored in the correction memory space 32
Is written to the address "dddd" of the basic memory area 31. The processing of updating the registers and the like according to other related information stored in the correction memory space 32. c
Write the interrupt attribute command to the ccc "address, that is, I / O
The interrupt attribute command will be written instead of the command. Here, the interrupt attribute instruction is an instruction having an attribute that causes an interrupt, and can call a processing routine program stored in the correction memory space 32.

When the benchmark program created as described above is given to the simulator 8, the following operations are realized. That is, the simulator 8 sequentially executes the instructions stored in the basic memory space 31. When the interrupt attribute command set in FIG. 8 is executed, the processing routine program stored in the correction memory space 32 is activated. Then, by this processing routine program, the data B stored in the correction memory space 32 is stored in the basic memory area 31.
It is written in the address "dddd" of and the registers are updated. After that, the process returns to the instruction next to the interrupt attribute instruction.

As described above, when the simulator 8 is provided with the benchmark program, the same operation as that caused by the I / O instruction is realized in the original program execution machine 1. Here, in the above benchmark program, the I / O instruction is replaced with the interrupt attribute instruction. Therefore, even if the simulator 8 cannot execute the I / O instruction, the operation corresponding to the I / O instruction is realized using the simulator 8. Instruction for Referencing Dynamic Information Here, it is assumed that the instruction for referencing dynamic information is executed in the original program execution machine 1.
The "dynamic information" is, for example, information about the time when an instruction is executed or the time required to execute a predetermined process. Further, the “instruction for referencing the dynamic information” is an instruction for deriving a different operation depending on the dynamic information. For example, the branch instruction is defined as "jump to address XX if executed within 10 seconds after program startup, and jump to address YY if executed thereafter".

The instruction for referring to the dynamic information as described above (hereinafter referred to as dynamic information reference instruction) is basically the simulator 8
But you can do it. However, the execution speed of the simulator 8 is not always the same as that of the original program execution machine 1. Therefore, when the same program is given to the original program execution machine 1 and the simulator 8, the processing results by the dynamic information reference instruction do not always become the same.

In the program creating method of the present embodiment, in order to solve this problem, when the dynamic information reference instruction is executed by the original program execution machine 1, the instruction is changed to another instruction (for example, a load instruction). And the correction process is performed so that the simulator 8 can realize the same operation.

FIG. 9 is a diagram for explaining the processing of the analysis tool 3 when the dynamic information reference instruction is executed. In FIG. 9, the dynamic information reference instruction is described as “D instruction”.

In the original program execution machine 1, by executing the dynamic information reference instruction stored in the address "eeee" of the memory 12, the dynamic information stored in the address "ffff" is referred to, It is assumed that the subsequent processing is decided according to the value of the dynamic information. Where memory 1
The address "ffff" of 2 is used, for example, as an area for writing the elapsed time from the start of the program.
Then, this elapsed time is used as dynamic information. Further, this dynamic information reference instruction is, for example, "f" in the memory 12.
This is an instruction that loads the dynamic information stored in the address "fff" into a predetermined register and compares it with a predetermined threshold value to determine the subsequent processing.

In this case, the tracer 15 creates the corresponding instruction record and register record. At this time, at least the instruction code for identifying the dynamic information reference instruction, the storage address of the dynamic information reference instruction, and the storage address of the dynamic information are registered in this instruction record. Also,
At least a register value is registered in the register record. Here, this register value is "fff" of the memory 12.
It is the result of comparison between the dynamic information read from the address "f" and the threshold value.

The analysis tool 3 performs the following processing by analyzing the created record. That is, the analysis tool 3 first writes the load instruction to the address "eeee" of the basic memory space 31 based on the instruction record.
This load instruction is an instruction to load the data stored in the address "ffff" into a predetermined register. Further, the analysis tool 3 writes the register value registered in the register record in the address "ffff" of the basic memory space 31.

When the benchmark program created as described above is given to the simulator 8, the following operations are realized. That is, when the load instruction is executed in the simulator 8, the basic memory space 31
The data stored in the address "ffff" is loaded into the specified register. Here, the comparison result when the dynamic information is compared with the threshold value in the original program execution machine 1 is stored in the address "ffff". Therefore, when the load instruction is executed in the simulator 8, the same operation as when the dynamic information reference instruction is executed in the original program execution machine 1 is realized.

In this way, when the above-mentioned benchmark program is given to the simulator 8, the same operation as when the dynamic information reference instruction is executed in the original program execution machine 1 is realized without referring to the dynamic information. . That is, even if the execution speeds or operating environments of the original program execution machine 1 and the simulator 8 are different from each other, the operation of the original program execution machine 1 is reproduced on the simulator 8.

In the example shown in FIG. 9, the same operation is realized in the original program execution machine 1 and the simulator 8 by replacing the dynamic information reference instruction with the load instruction, but the present invention is not limited to this. Not something. That is, for example, when the processing by the dynamic information reference instruction is complicated, or when the instruction is executed a plurality of times and the register value is different each time the instruction is executed, as in the case of the above-described I / O instruction, An interrupt attribute command may be used. That is, the dynamic information reference instruction is replaced with the interrupt attribute instruction, and the processing routine program called when the interrupt due to the interrupt attribute instruction occurs is stored in the correction memory space 32. In this case, the processing routine program describes the processing corresponding to the dynamic information reference instruction. Asynchronous Interrupt ( No. 2) Here, it is assumed that the original program execution machine 1 has generated an I / O interrupt from the external device 21 and executed a process corresponding to the interrupt.

FIG. 10A is a diagram showing an instruction sequence when the above-mentioned interrupt occurs in the original program execution machine 1. Here, the instructions A to F. ． ． It is assumed that the interrupt occurs immediately after the instruction C is executed in the sequence in which Then, the processing routine 41 including the instructions a to d is executed by the interrupt, and then the processing returns to the instruction D.

When the benchmark program of the present embodiment is created, in order to reproduce the operation caused by the asynchronous interrupt in the simulator 8, the instruction immediately before the asynchronous interrupt calls the processing routine 41. Is replaced by In the case of the above example, as shown in FIG. 10B, the instruction C is replaced with an interrupt attribute instruction for calling the processing routine 42. Here, the processing routine 4
2 is in addition to the instructions a to d that form the processing routine 41,
It includes data (emulation data) that emulates the operation caused by the instruction C. In addition, the emulation data of the instruction C includes, for example, a calculation result when the instruction C is executed, information regarding register update, and the like.

In the above example, the instruction immediately before the asynchronous interrupt is replaced by the interrupt attribute instruction, but the instruction immediately before is not necessarily replaced, and the instruction near the timing at which the asynchronous interrupt occurs is not necessarily replaced. Other instructions may be replaced with interrupt attribute instructions. In this case, it is desirable that an instruction that can be easily emulated (for example, an ADD instruction) be replaced with an interrupt attribute instruction.

FIG. 11 is a diagram for explaining the processing of the analysis tool 3 when an asynchronous interrupt occurs. Note that FIG. 11 shows an embodiment corresponding to the example shown in FIG. In the original program execution machine 1, "g" in the memory 12
It is assumed that the asynchronous interrupt occurs immediately after the instruction C stored in the address ggg "is executed, and the processing routine 41 is called by this interrupt. In this case, the tracer 15
An instruction record corresponding to the instruction C, a record corresponding to information updated due to the instruction C, an interrupt record corresponding to an asynchronous interrupt, a record corresponding to an instruction included in the processing routine 41, etc. are created.

The analysis tool 3 performs the following processing based on the created record. That is, the analysis tool 3
First, the emulation data of the instruction C is created by referring to the register record or the like, and the processing routine 42 in which the instruction including the emulation data and passing the processing to the instruction a is finally executed is created. Then, the processing routine 42 is written in a predetermined area of the correction memory space 32. In addition, the analysis tool 3 uses the basic memory space 3
Write the interrupt attribute command to the "gggg" address of 1. This interrupt attribute command is a command for calling the processing routine 42.

When the benchmark program created as described above is given to the simulator 8, the following operations are realized. That is, when the interrupt attribute instruction is executed in the simulator 8, the processing routine 42 is called. As a result, the operation corresponding to the instruction C is realized. Then, the control is passed to the processing routine 41. After the processing routine 41 is executed, the processing returns to the instruction following the instruction C.

As described above, when the above-mentioned benchmark program is given to the simulator 8, the operation equivalent to the operation caused by the asynchronous interrupt in the original program execution machine 1 is reproduced without generating the asynchronous interrupt. . That is, even if the simulator 8 does not have a function of accepting an asynchronous interrupt, the same operation as when an asynchronous interrupt occurs in the original program execution machine 1 is reproduced on the simulator 8.

Although the interrupt instruction is used in the above embodiment, this interrupt instruction is an example of the instruction sequence switching instruction. That is, in FIG. 11, command C
May be replaced with an instruction for switching the instruction sequence. In this case, the processing routine 42 is linked with the instruction for switching the instruction sequence.

FIG. 12 is a flow chart for explaining the operation of the analysis tool 3. As described above, the analysis tool 3 sequentially analyzes each record of the execution history information 2 to create the basic data 4 and the correction data 5 that are the basis of the benchmark program 7. The basic data 4 and the correction data 5 are written in the initial memory space 30.

Step S21 is a process for extracting each record of the execution history information 2 one by one from the beginning. In steps S22 to S27, the attribute of the extracted record is checked. Here, the attribute of the record is identified by the record type shown in FIG.

If the record extracted from the execution history information 2 is the instruction record, the process proceeds to step S31. In step S31, it is checked whether or not an interrupt command is registered in the record. Then, if the interrupt command is registered, in step S32, the information related to the interrupt command is registered in the management list. As shown in FIG. 13A, the management list registers information related to each interrupt command in the order of appearance. When a new interrupt command is registered in this management list, a serial number is given to the interrupt command. At this time, the address information corresponding to the interrupt instruction is added to the interrupt management table shown in FIG. 13 (b). The interrupt management table manages the correspondence relationship between the serial number assigned to each interrupt instruction and the address that stores the processing routine program that describes the processing executed due to the interrupt instruction.

If no interrupt command is registered in the extracted record, the process proceeds to step S33. In step S33, it is checked whether or not "an instruction that can be replaced with another instruction (a candidate for a point that causes an interrupt)" is registered in the extracted record. The "instruction that can be replaced with another instruction" corresponds to, for example, the dynamic information reference instruction shown in FIG. 9 in the above embodiment. Then, when such an instruction is registered in the record, in step S34, the correspondence between the instruction before replacement and the instruction after replacement is registered. Specifically, the instruction ID corresponding to the variable for recording the replacement candidate is registered.

If no "command that can be replaced by another command" is registered in the extracted record, the process proceeds to step S35. In step S35, it is checked whether or not an unexecutable instruction is registered in the extracted record. The non-executable instruction is an instruction that cannot be executed by the simulator 8 and corresponds to, for example, the I / O instruction shown in FIG. 8 in the above embodiment. Then, if the non-executable instruction is registered in the record, step S36.
In, the emulation processing (processing routine program for the emulation processing) is created.

As shown in FIG. 8, when the non-executable instruction is replaced with the interrupt instruction, the interrupt instruction is also registered in the management list shown in FIG. 13 (a). Then, the correspondence relationship between the serial number of the interrupt instruction and the address storing the processing routine program in which the processing executed due to the interrupt instruction is stored is shown in the interrupt management table shown in FIG. 13 (b). Is set.

When a general command is stored in the extracted record (when it is determined as "No" in steps S31, 33, 35), the initial memory space 30 is updated in step S37. This process
For example, it corresponds to the procedure shown in FIG. Also, when the emulation processing is created in step S36, step S37 is executed. This process is performed, for example, in FIG.
In, it corresponds to the procedure of writing the interrupt attribute command and the data B in the initial memory space 30.

If the record extracted from the execution history information 2 is a register record, the process proceeds to step S41. In step S41, the register (register group 3 shown in FIG.
3) is updated.

If the record extracted from the execution history information 2 is an interrupt record, the process proceeds to step S42. In step S42, an interrupt command is generated as necessary and registered in the management list shown in FIG. 13 (a). For example,
In the example shown in FIGS. 10 to 11, since the instruction C is replaced with the interrupt attribute instruction, the interrupt attribute instruction is registered in the management list. In this case, the corresponding information is shown in FIG.
It is set in the interrupt management table shown in (b).

If the record extracted from the execution history information 2 is a memory data record, step S37.
At, the corresponding data is written into the initial memory space 30.

If the record extracted from the execution history information 2 is the table reference record, step S37.
In the memory space 3
Write to 0. Here, an address conversion table for converting a logical address into a real address is assumed. The address conversion table will be described later separately.

When the record extracted from the execution history information 2 is the key information record, the corresponding key information is registered in step S43. The key information is
It is written in the correction memory space 32.

When the processes of steps S21 to S43 are executed for all the records constituting the execution history information 2, the information necessary for calling the corresponding processing routine from each interrupt instruction is set in step S51. It At this time, the interrupt management table shown in FIG. 13B is referred to, and for the interrupt instruction generated by the replacement processing, information (including the instruction) for calling the corresponding processing routine from the correction memory space 32 is included. ) Is set.

As described above, the benchmark program of this embodiment has the initial memory space 30 including the basic memory space 31 and the correction memory space 32.
It is stored in. Then, the instructions executed by the original program execution machine 1 are written in the basic memory space 31. At this time, each instruction is written at the same address as when it was stored in the memory 12 of the original program execution machine 1. When a memory update or memory reference occurs in the original program execution machine 1, corresponding memory data is written in the basic memory space 31. At this time, the memory data is written at the same address as when it was stored in the memory 12 of the original program execution machine 1.

For operations that cannot be performed in the simulator 8, equivalent operations are provided by using the correction memory space 32. For example, when an I / O instruction is executed in the original program execution machine 1, an interrupt instruction is written in the basic memory space 31 instead of the I / O instruction, and the operation resulting from the I / O instruction is executed. Information (correction data) for realizing is written in the correction memory space 32. Then, necessary information is set so that the correction data stored in the correction memory space 32 is called from the interrupt instruction. Also,
When an asynchronous interrupt occurs in the original program execution machine 1, a predetermined instruction to be executed near the timing when the interrupt occurs is replaced with the interrupt instruction. Then, in the same manner, the correction memory space 32
Necessary information is set so that the correction data stored in is called.

Therefore, when the simulator 8 is given the benchmark program, the same instruction sequence as when the application program is executed in the original program execution machine 1 is executed. At this time, of the processes executed by the original program execution machine 1, the processes that cannot be executed by the simulator 8 are rewritten in a format that can be executed by the simulator 8. Therefore, even if the simulator 8 does not have the same function as the original program execution machine 1, the simulator 8 can faithfully reproduce the operation realized in the original program execution machine 1. As a result, highly reliable evaluation can be performed using the simulator 8.

Next, the address conversion table will be described. The address conversion table is a table referred to when converting a logical address recognized by the CPU into a real address, and is stored in a predetermined area in the memory 12 in the original program execution machine 1. However, the correspondence relationship between the logical address and the real address usually changes moment by moment as the instruction sequence is executed. Therefore, the benchmark program also needs to describe the change in the correspondence between the logical address and the real address.

Therefore, while the application program is being executed in the original program execution machine 1, the tracer 15 creates a table reference record containing one set of pre-translation address and post-translation address every time the address translation table is referenced. Create one by one. Then, the analysis tool 3 generates the address conversion table actually referenced in the original program execution machine 1 on the initial memory space 30 based on the created table reference record. Here, in the address conversion table provided in the original program execution machine 1, only a part of the address conversion table is actually referred to when the instruction is executed. That is, the effective information is stored only in part of the address conversion table reproduced in the initial memory space 30. Therefore, the address conversion table reproduced in the initial memory space 30 can be compressed. Below, FIG.
The compression of the address conversion table will be described with reference to FIG.

Here, as shown in FIGS. 14A and 14B, table A converts a predetermined area of the logical address space into addresses 1000 to 2000 of the real address space, and table B converts the logical address. It is assumed that another predetermined area of the space is converted to addresses 3000 to 4000 of the real address space. Tables A and B are shown in FIG.
As shown in 4 (b), it is assumed that only the hatched areas are actually referenced in the original program execution machine 1. In this case, when the table A and the table B are reproduced in the initial memory space 30, the effective conversion information is stored only in the hatched area. Further, as shown in FIG. 14 (b), assuming that the real address spaces managed by the table A and the table B are the same, the real addresses storing valid translation information in these two tables are It does not overlap.

In this case, as shown in FIG. 14B, in the initial memory space 30, the table A and the table B can be merged (integrated) with each other. As a result, the real address spaces managed by the above two tables can also be merged with each other. For example, the data stored in the addresses 1000 to 2000 and 3000 to 4000 before the table A and the table B are merged, as shown in FIG.
It is stored only at addresses 1000 to 2000. As a result, the initial memory space 30 can be reduced.

FIG. 15 is a block diagram of a system for creating and verifying the benchmark program 7. Here, the original program execution machine 1, the execution history information 2, the analysis tool 3, the basic data 4, the correction data 5, and the benchmark program 7 correspond to the units denoted by the same reference numerals in FIG.

In FIG. 15, the monitor source 51 is
A program or the like for processing the correction data 5 is stored. These programs are written in a high level language, for example. FIG. 16 shows one of the programs stored in the monitor source 51.

FIG. 16 is a flow chart showing the procedure for determining the processing corresponding to each interrupt instruction when the benchmark program is executed in the simulator 8. In step S61, first, pre-interruption processing is executed. In this process, for example, a register backup or the like is performed. Succeedingly, in a step S62, it is checked whether or not the generated interrupt needs correction. Then, if the correction is necessary, in step S63, the control variable is used as a search key to search the interrupt management table shown in FIG. Then, extract the corresponding address from the entry with the serial number that matches the control variable,
The processing routine program stored at that address is executed. In step S64, "1" is added to the control variable. In step S65, post-interrupt processing is executed. As a result, the process returns to the interrupt source or the instruction to pass the control.

The object generator 52 uses the correction data 5
And a compiler for compiling the monitor source 51,
And a linker. The output of the object generation unit 52 is a data string to be stored in the correction memory space 32 of the initial memory space 30. The address resolution unit 53 resolves addresses so as to ensure continuity between the data stored in the basic memory space 31 and the data to be stored in the correction memory space 32. Then, the benchmark program 7 is obtained by integrating the basic data 4 generated by the analysis tool 3 and the data whose address is resolved by the address resolution unit 53.

The monitor source 51, the object generating section 52, and the address solving section 53 correspond to the correction tool 6 shown in FIG. The created benchmark program 7 is verified by the architecture simulator 61. At this time, the dynamic analysis tool 62 checks the tracer 15 or the analysis tool 3 for defects based on the execution history information 2 and the simulation result by the architecture simulator 61. Then, the check result is fed back to the tracer 15 and the analysis tool 3 as needed.

By the way, the above-described embodiment is premised on that the execution history information 2 includes all information relating to the operation of the original program execution machine 1. That is, in the above-mentioned embodiment, the tracer 15 operates continuously in parallel with the execution of the application program.

However, the load of the tracer 15 may be heavy depending on the application. In this case, if the tracer 15 is continuously operated, the execution of the application program may be adversely affected. Therefore, the original program execution machine 1 is
5 can be operated intermittently.

FIG. 17 is a diagram for explaining the processing when the tracer 15 is intermittently operated. here,
It is assumed that the cycle composed of the period in which the tracer 15 is operating and the period in which it is stopped is repeated.

The tracer 15 outputs the execution history information during the operation period, but does not output it when stopped. Therefore, in order to create a benchmark program for faithfully reproducing the operation of the original program execution machine 1, the analysis tool 3 estimates the operation of the original program execution machine 1 while the tracer 15 is stopped. There is a need. For example, in cycle n of FIG. 17, the execution history information of times Ta to Tb is output, but the execution history information of times Tb to Tc is not output. In this case, the analysis tool 3 needs to estimate the execution history of the original program execution machine 1 between times Tb and Tc.

The analysis tool 3 executes the original program execution machine 1 at times Tb to Tc as follows.
Estimate the behavior of. However, since it is difficult to completely obtain the operation of the original program execution machine 1, it is assumed here that the update contents of the memory 12 at times Tb to Tc are estimated. Memory 1 from time Tb to Tc
The update content of 2 is represented by the difference between the content of the dynamic memory space at time Tb and the content of the memory space created based on the execution history information after time Tc.
The dynamic memory space is a memory space in which the contents of the memory data record are all reflected in the order of application, and is basically created in a space different from the initial memory space 30. Further, the memory space created based on the execution history information after the time Tc is basically created in a space different from the initial memory space 30.

The analysis tool 3 writes the data corresponding to the initial memory space 30 based on the execution history information of the times Ta to Tb, and then the memory 1 at the times Tb to Tc.
The updated contents of No. 2 are written in the initial memory space 30. After that, the analysis tool 3 repeats the same processing for the subsequent cycles. Thus, even if the tracer 15 operates intermittently, a benchmark program for faithfully reproducing the operation of the original program execution machine 1 is created.

As described above, the benchmark program 7 of this embodiment is a load module for reproducing the instruction sequence when the original program is executed in the original program execution machine 1. At this time,
The benchmark program 7 may be a load module that represents an instruction sequence when only a part of the original program is executed.

The function of creating the benchmark program (load module) 7 is realized by executing the program in which the above sequence is described using a computer. FIG. 18 shows the configuration of the computer 100 that executes the program.

The CPU 101 loads the program describing the processing shown in the above sequence from the storage device 102 into the memory 103 and executes it. The storage device 102 is a mass storage device, and stores the above program.
On the other hand, the memory 103 is, for example, a semiconductor memory, and has a C
It is used as a work area of the PU 101. The initial memory space 30 can be realized by using the memory 103.

The recording medium driver 104 is the CPU 101.
The portable recording medium 105 is accessed in accordance with the instruction.
The portable recording medium 105 is, for example, a semiconductor device (P
C card), a medium for inputting / outputting information by magnetic action (a floppy (registered trademark) disk, a magnetic tape, etc.), and a medium for inputting / outputting information by optical action (optical disc, etc.). The communication control device 106 includes the CPU 1
Data is transmitted / received to / from the network according to the instruction 01.

Here, the benchmark program 7 uses the tracer 15 for extracting the execution history information 2 from the original program execution machine 1 and the analysis tool 3 for analyzing the execution history information 2 (here, it is assumed to include the correction tool 6). Created. Then, the tracer 15 is realized by executing the flowchart of FIG. 3 in the original program execution machine 1. On the other hand, the analysis tool 3 is realized by executing the flowchart of FIG. 12 (including the sequence shown in FIGS. 6 to 11) in the computer 100 shown in FIG. However, the analysis tool 3 does not necessarily have to be implemented by a computer different from the original program execution machine 1 and may be implemented by the original program execution machine 1.

FIG. 19 is a diagram for explaining a method of providing a program for creating a benchmark program.
The program for creating the benchmark program is provided by, for example, any one of the following three methods.

(A) It is provided by being installed in a computer. In this case, the program and the like are pre-installed before shipping, for example. (b) Provided by being stored in a portable recording medium. In this case, the programs and the like stored in the portable recording medium 105 are basically installed in the storage device 102 via the recording medium driver 104.

(C) It is provided from a server on the network. In this case, basically, the computer 100 acquires a program or the like by downloading the program or the like stored in the server.

The created benchmark program may be stored in a portable recording medium such as a CD-ROM and provided to the user, or may be sent to the user terminal via the network.

(Supplementary Note 1) A method for creating a test program for evaluating an information processing apparatus, which is executed by the processor when the original program is executed by using a computer having a processor and a memory. A load module format that detects instructions and access contents to the memory, stores the detected information as execution history information in time series, and reproduces the instruction execution sequence executed by the computer based on the execution history information. A test program creation method characterized by creating a program.

(Supplementary Note 2) A method of creating a test program for evaluating an information processing apparatus, which is executed by the processor while the original program is executed using a computer having a processor and a memory. An instruction code corresponding to an instruction, instruction information related to the instruction, binary data written to or read from the memory, and access information indicating access contents to the memory are detected, and the detected information is an execution history. Information is stored in time series, the execution history information is analyzed in time series, the instruction code is written in a pre-prepared memory space based on the instruction information, and the binary data is written based on the access information. By writing, load module format program Test program creation method according to claim that you create.

(Supplementary Note 3) In the test program creating method according to Supplementary Note 2, the memory space has substantially the same address space as the memory provided in the computer.

(Supplementary Note 4) In the test program creating method according to Supplementary Note 2, in the case where the computer executes the first instruction which is an instruction that cannot be executed by the apparatus to which the test program is given, the first instruction Create a processing routine program that substitutes the operation of the computer caused by the instruction of, and write in the memory space,
An instruction for calling the processing routine program is written in the memory space instead of the first instruction.

(Supplementary Note 5) In the test program creating method according to Supplementary Note 4, the first instruction is an I / O instruction. (Supplementary note 6) The test program creation method according to supplementary note 2, which is an instruction that may cause different operations when executed by the computer and when executed by a device to which the test program is given. When the second instruction is executed by the computer, the condition referred to by the processor when the second instruction is executed by the computer is written in the memory space, and the condition is replaced by the second instruction instead of the second instruction. Write the instruction to call the condition into the memory space.

(Supplementary Note 7) In the test program creating method according to Supplementary Note 2, in the case where the first operation, which is an operation that cannot be performed by the device to which the test program is given, is executed by the computer, A processing routine program that replaces the third operation, which is an instruction executed near the timing when the first operation is executed, with an instruction that switches the instruction sequence, writes the instruction in the memory space, and replaces the first operation An instruction that replaces the instruction sequence created and written in the memory space is linked with the processing routine program.

(Supplementary Note 8) In the test program creating method according to Supplementary Note 7, the first operation is an asynchronous interrupt. (Supplementary Note 9) In the test program creating method according to Supplementary Note 7, the processing routine program includes emulation of the third instruction.

(Supplementary note 10) The test program creating method according to supplementary note 2, wherein the plurality of address conversion tables are used when a logical address is converted into a real address by using a plurality of address conversion tables in the computer. When the is referenced, the reference information indicating the reference content is stored in time series, and based on the stored reference information,
A plurality of tables corresponding to the plurality of address conversion tables are created, and the result of merging the tables is written in the memory space.

(Supplementary note 11) The method for creating a program according to supplementary note 2, wherein the update content of the memory is estimated in a period in which the instruction code, instruction information, binary data, and access information are not detected, and the estimated update content is estimated. To the above memory space.

(Supplementary Note 12) A system for creating a test program for evaluating an information processing apparatus, which is executed by the processor when the original program is executed by using a computer having a processor and a memory. A detection unit that detects an instruction and access contents to the memory; a storage unit that stores the detected information as execution history information in time series; and an instruction execution sequence executed by the computer based on the execution history information. A test program creating system comprising: a creating unit that creates a load module format program to be reproduced.

(Supplementary Note 13) A system for creating a test program for evaluating an information processing apparatus, which is executed by the processor while the original program is executed by using a computer having a processor and a memory. Detecting means for detecting an instruction code corresponding to the instruction, instruction information related to the instruction, binary data written to or read from the memory, and access information indicating access contents to the memory, and the detected information. And a storage means for storing the execution history information in time series, analyzing the execution history information in time series, and writing the instruction code based on the instruction information in a pre-prepared memory space to the access information. By writing the above binary data based on Test program generation system characterized by comprising a generating means for generating de modular program.

(Supplementary Note 14) In order to create a test program for evaluating the information processing apparatus, the computer detected by the other program having a processor and a memory is used. Test program creation for functioning as a creation module for creating a load module format program that reproduces an instruction execution sequence executed by the other computer based on an instruction executed by a processor and access contents to the memory program.

(Supplementary Note 15) In order to create a test program for evaluating an information processing apparatus, a computer is operated by the processor detected when the original program is executed using a computer having a processor and a memory. An analysis means for analyzing an instruction code corresponding to the executed instruction, instruction information related to the instruction, binary data written in or read from the memory, and access information indicating access contents to the memory; A load module format program is created by writing the above instruction code based on the above instruction information and the above binary data based on the above access information in a memory space prepared in advance based on the analysis result by the analyzing means. Creating hands , Test program generation program for functioning as a.

(Supplementary Note 16) In order to create a test program for evaluating an information processing apparatus, an instruction to be executed by a processor of the computer when the original program is executed by the computer. And detecting means for detecting access contents to the memory of the computer, and creating means for creating a program in a load module format for reproducing the instruction execution sequence executed by the computer based on the information detected by the detecting means, Test program creation program to function as.

(Supplementary Note 17) In order to create a test program for evaluating an information processing apparatus, a computer is made to correspond to an instruction executed by the processor while the original program is being executed using the computer. Instruction code, instruction information relating to the instruction, binary data written to or read from the memory, and access information indicating access content to the memory, and detection means for detecting the access information. By writing the instruction code on the basis of the instruction information in the previously prepared memory space based on the information in time series and the binary data on the basis of the access information,
A test program creation program to function as a creation means for creating a load module format program.

(Supplementary Note 18) In order to create a test program for evaluating an information processing apparatus, an instruction to be executed by a processor of the computer while the original program is being executed by the computer. And detecting means for detecting access contents to the memory of the computer, and creating means for creating a program in a load module format for reproducing the instruction execution sequence executed by the computer based on the information detected by the detecting means, A computer-readable recording medium in which a test program creation program for functioning as a computer is recorded.

(Supplementary Note 19) In order to create a test program for evaluating the information processing apparatus, a computer is made to correspond to the instruction executed by the processor when the original program is executed using the computer. Instruction code, instruction information relating to the instruction, binary data written to or read from the memory, and access information indicating access content to the memory, and detection means for detecting the access information. By writing the instruction code on the basis of the instruction information in the previously prepared memory space based on the information in time series and the binary data on the basis of the access information,
A computer-readable recording medium recording a test program creating program for functioning as a creating means for creating a load module format program.

(Supplementary Note 20) A test program for evaluating an information processing apparatus, comprising: an instruction executed by the processor detected when the original program is executed using a computer having a processor and a memory; A load module type test program that reproduces an instruction execution sequence executed by the computer based on access contents to the memory.

[0129]

According to the present invention, the performance of an information processing apparatus can be accurately evaluated before it is completed. Therefore, the development period of the information processing device can be shortened. In addition, it is possible to efficiently change the design to bring it closer to the target characteristic.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an overview of a program creation method according to this embodiment.

FIG. 2 is a configuration diagram of an original program execution machine.

FIG. 3 is a flowchart showing the operation of the tracer.

FIG. 4 is an example of execution history information.

FIG. 5 is a configuration diagram of an initial memory space.

FIG. 6 is an example of a process of writing an instruction code in an initial memory space.

FIG. 7 is a diagram illustrating processing of an analysis tool when a memory update occurs due to an I / O interrupt.

FIG. 8 is a diagram illustrating a process of an analysis tool when a memory update is generated by an I / O instruction.

FIG. 9 is a diagram illustrating a process of an analysis tool when a dynamic information reference instruction is executed.

10A is a diagram showing an instruction sequence when an asynchronous interrupt occurs in the original program execution machine, and FIG. 10B is a diagram explaining a method for realizing the sequence shown in FIG. 10A. Is.

FIG. 11 is a diagram illustrating processing of the analysis tool when an asynchronous interrupt occurs.

FIG. 12 is a flowchart illustrating the operation of the analysis tool.

FIG. 13A is an example of a list for managing interrupt instructions,
(b) is a diagram showing an example of a method of identifying an interrupt instruction.

FIG. 14 is a diagram illustrating compression of an address conversion table.

FIG. 15 is a configuration diagram of a system for creating and verifying a benchmark program.

FIG. 16 is a flowchart showing a procedure for determining a process corresponding to each interrupt instruction when the benchmark program is executed.

FIG. 17 is a diagram for explaining a process when the tracer is intermittently operated.

FIG. 18 is a block diagram of a computer that executes a program describing the functions of the present invention.

FIG. 19 is a diagram illustrating a method of providing a software program or the like according to the present invention.

[Explanation of symbols]

1 Original program execution machine 2 Execution history information 3 analysis tools 4 basic data 5 Correction data 6 correction tools 7 Benchmark program 11 CPU 12 memories 13 OS 14 Application program 15 Tracer 21 External device 30 initial memory space 31 Basic memory space 32 correction memory space

Claims (10)

[Claims] 1. A method for creating a test program for evaluating an information processing apparatus, comprising instructions and instructions executed by the processor when the original program is executed using a computer including a processor and a memory. A load module format program that detects the contents of access to the memory, stores the detected information as execution history information in time series, and reproduces the instruction execution sequence executed by the computer based on the execution history information. A test program creating method characterized by creating. 2. A method of creating a test program for evaluating an information processing apparatus, wherein the instructions executed by the processor are executed when the original program is executed using a computer including a processor and a memory. Corresponding instruction code,
Detects command information related to the command, binary data written to or read from the memory, and access information indicating access contents to the memory, and stores the detected information in time series as execution history information. By analyzing the execution history information in time series and writing the instruction code based on the instruction information and the binary data into the memory space prepared in advance, the load module format can be obtained. A method for creating a test program, which is characterized by creating the above program. 3. The test program creating method according to claim 2, wherein the first instruction, which is an instruction that cannot be executed by a device to which the test program is given, is executed by the computer. A processing routine program for substituting the operation of the computer caused by the instruction is created and written in the memory space, and an instruction for calling the processing routine program is written in the memory space instead of the first instruction. 4. The test program creating method according to claim 2, wherein an instruction that may cause a different operation when executed by the computer and when executed by a device to which the test program is given. When the second instruction is executed by the computer, the condition referred to by the processor when the second instruction is executed by the computer is written into the memory space, and the second instruction is replaced by the second instruction instead of the second instruction. Write an instruction to call the above condition in the memory space. 5. The method for creating a test program according to claim 2, wherein the first operation, which is an operation that cannot be performed by the device to which the test program is given, is executed by the computer. Create a processing routine program that replaces the first operation by replacing the third instruction, which is an instruction executed near the timing at which the first operation is performed, with an instruction that switches the instruction sequence, and writing it in the memory space. Then, the instruction is written in the memory space, and the instruction for switching the instruction sequence and the processing routine program are linked. 6. A system for creating a test program for evaluating an information processing apparatus, comprising: an instruction executed by the processor when the original program is executed using a computer having a processor and a memory; Detecting means for detecting access contents to the memory, storage means for storing the detected information as execution history information in time series, and reproducing instruction execution sequence executed by the computer based on the execution history information A test program creating system comprising: a creating module for creating a program in a load module format. 7. A system for creating a test program for evaluating an information processing apparatus, wherein the instruction executed by the processor is executed when the original program is executed by using a computer including a processor and a memory. Corresponding instruction code,
Detection means for detecting instruction information related to the instruction, binary data written in or read from the memory, and access information indicating access contents to the memory, and the detected information in time series as execution history information. And a storage means for storing the execution history information in time series, and writing the instruction code based on the instruction information and the binary data into the prepared memory space based on the access information. A test program creating system comprising: a creating module for creating a program in a load module format. 8. A computer, in order to create a test program for evaluating an information processing apparatus, by the processor detected when the original program is executed using another computer having a processor and a memory. A test program creation program for functioning as a creation means for creating a load module format program that reproduces an instruction execution sequence executed by another computer based on an instruction to be executed and access contents to the memory. 9. In order to create a test program for evaluating an information processing apparatus, a computer is provided with instructions executed by a processor of the computer when the original program is being executed using the computer, and Functions as detecting means for detecting the contents of access to the memory of the computer, and creating means for creating a load module format program for reproducing the instruction execution sequence executed by the computer based on the information detected by the detecting means. A test program creation program to let you do. 10. A test program for evaluating an information processing apparatus, the instruction executed by the processor and the memory detected when the original program is executed using a computer including a processor and a memory. A load module format test program that reproduces an instruction execution sequence executed by the computer based on access contents to the computer.