JP2003015866A - Processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute a small-sized instruction code without causing an increase in the number of gates and lowering of speed. SOLUTION: A compressed instruction code (24 bit) is stored in a memory, the instruction code is accessed by converting a reading address, the read instruction code is extended to original size (32 bit) and executed by a CPU core. Thus, a RISCCPU core can remain as it is and the small-sized instruction code can be executed without causing the increase of the number of gates and the lowering of the speed.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to RISC (Reduce
d Instruction Set Computer) and the like, and in particular to execution of instruction code compressed and stored in memory.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration example of a conventional RISC processor. RISC CPU core 1
Accesses the main memory 3 through the address bus 7 by the memory controller 2 and sends the instruction code to the data bus 8.
Read through and execute.

The size of the instruction code stored in the main memory 3 affects the amount of memory used and is preferably as small as possible. However, in the RISC CPU core 1, the instruction code is defined as fixed at 32 bits (4 bytes). CIS
The size of the instruction code is larger than that of a processor such as C (Complexed Instruction Set Computer).

[0004]

If the size of the instruction code stored in the main memory 3 is large as described above, the capacity of the main memory 3 must be increased,
Therefore, there is a problem that the device becomes expensive. Therefore, if the capacity of the main memory 3 is set to a normal size, then there is a problem that the amount of stored programs and data is reduced.

In order to deal with these problems, some processors have a mode in which a code of a small size can be executed. However, it is necessary to add a function for that to the CPU core 1, resulting in an increase in the number of gates and a decrease in speed. It was a cause to invite.

The present invention has been made to solve the above-mentioned conventional problems, and its purpose is to increase the size of an instruction code larger than the size of an instruction code to be originally executed without causing an increase in the number of gates and a decrease in speed. Is to store a small instruction code in a memory and provide a processor capable of executing the instruction code.

[0007]

In order to achieve the above object, the first feature of the present invention is to provide a processor in which a CPU core reads a code from a memory via a memory control device and executes the code. An address conversion circuit for converting a read address to be output and a code expansion circuit for expanding the size of the code read from the memory by the memory control device are provided, and the memory control device is converted by the address conversion circuit. Read the code stored in the address from the memory,
The PU core is to execute the code whose size has been converted by the code expansion circuit.

Here, the CPU core is a RISC CPU
The memory is a core, 24-bit instruction code is stored in the memory, the address conversion circuit performs conversion to make the address output from the CPU core 3/4, and the code expansion circuit outputs 24-bit instructions. It is characterized in that the code is expanded into a 32-bit instruction code.

A second feature of the present invention is that in a processor in which a CPU core reads a code from a memory via a memory control device and executes the code, an address conversion circuit for converting a read address output by the CPU core,
A code expansion circuit for expanding the size of the code read from the memory by the memory control device;
A first selection circuit that selects either the read address output by the U core or the address converted by the address conversion circuit and passes it to the memory control device; and the memory control device reads the memory from the memory. Or a code expanded by the code expansion circuit, and a second selection circuit which transfers the selected code to the CPU core, and the memory control device is converted by the address conversion circuit. The code stored at the address or the original read address output by the CPU core is read from the memory, and the CPU core reads the code whose size has been converted by the code expansion circuit or the code read from the memory. To run the original code.

An address decoder for decoding the read address output from the CPU core and generating a control signal for controlling the selection operation of the first and second selection circuits is provided.

Further, the CPU core is a RISC CPU core, the 32-bit and 24-bit instruction codes are mixedly stored in the memory, and the address conversion circuit outputs the address output by the CPU core to 3/3. The conversion to 4 is performed, and the code expansion circuit expands the 24-bit instruction code into a 32-bit instruction code.

According to the present invention, the instruction code is set to a fixed length of 24 bits (3 bytes) by limiting the number of registers to be used, the value of a fixed value in the instruction, and the range of the jump destination address. When it is read, it is expanded to 4 bytes so that it can be executed by the conventional CPU core.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration according to a first exemplary embodiment of a processor of the present invention. However, the same parts as those of the conventional example will be described with the same reference numerals. The processor of this example is a RISC processor, which is a RISC CPU core 1 that executes instruction codes and a main memory 3.
Memory control devices 2 and 2 for controlling access to the memory
A main memory 3 storing a 4-bit instruction code,
It has a code expansion circuit 4 for expanding the read instruction code from 3 bytes to 4 bytes.

Here, the memory controller 2 controls the reading of the code from the main memory 3 by the memory controller 2.
1 and the address issued from RISC CPU core 1,
It has an address 3/4 conversion circuit unit 22 for converting so that the offset based on the start address of the compressed code becomes 3/4.

Next, the operation of this embodiment will be described. First, in the main memory 3 of the present example, as shown in FIG.
As shown in (B), it is stored after being compressed to 24 bits.

Here, the reserved area of the instruction code after compression is omitted with respect to the instruction code before compression, and the register (only Reg1 to Reg3 is shown in the figure, but actually more registers are included). Since there is a smaller number of), it is possible to compress the instruction code.

The RISC CPU core 1 sets the address of the instruction code to be read to the address 3/4 of the memory controller 2.
Output to the conversion circuit 22. Since the address is a multiple of 4, the address 3/4 conversion circuit 22 sets the address to 3 /.
It is converted to 4 and passed to the memory control unit 21. As a result, the memory control unit 21 accesses the area of the main memory 3 at the address converted into 3/4, reads the stored 24-bit instruction code, and outputs it to the code expansion circuit 4.

The code decompression circuit 4 decompresses the input 24-bit instruction code into 32 bits and outputs the RISCCPU.
Pass to core 1. The RISC CPU core 1 executes a 32-bit instruction code.

According to the present embodiment, since the main memory 3 contains a compressed 32-bit instruction code into a 24-bit instruction code, many instructions can be executed without increasing the capacity of the main memory 3. The code can be stored, and a large program or the like can be stored in the memory without making the device expensive.

Since the RISC CPU core 1 executes a 32-bit instruction code, the RISC CPU core 1 may have the conventional configuration.
There is no increase in the number of gates and reduction in processing speed.

In this example, the code expansion circuit 4 and the address 3/4 conversion circuit 22 are added, but since they are simple circuits, they do not increase the cost of the device.

FIG. 3 is a block diagram showing the configuration according to the second embodiment of the processor of the present invention. However, in FIG.
The same parts as those in the first embodiment shown in are denoted by the same reference numerals, and the description thereof will be appropriately omitted.

This example shows a configuration example in which a 32-bit instruction code and a 24-bit instruction code are mixedly stored in the main memory 3. Therefore, the memory control unit 2 selects either the address converted by the address 3/4 conversion circuit 22 or the original address output from the RISC CPU core 1 to select the memory control unit 21.
To the RISC for selecting the 24-bit instruction code read from the memory controller 2 or the 32-bit instruction code from the code decompression circuit 4.
It has a selection circuit 6 to be passed to the CPU core 1, and an address decoder 5 which generates a signal for controlling the selection operation of the selection circuit 6 and the selection circuit 23.

Next, the operation of this embodiment will be described.
First, in the main memory 3 of the present example, as shown in FIG.
As shown in (B), the data is compressed and stored in 24 bits, and the instruction code of 32 bits is also mixed and stored.

The RISC CPU core 1 outputs the address of the instruction code to be read to the memory controller 2. At this time, the address decoder 5 decodes the input address, which is for reading the 32-bit instruction code. If so, the selection circuit 23 selects the original address, and the selection circuit 6 generates a control signal for selecting an instruction code that has not passed through the code expansion circuit 4, and the selection circuit 2
3 and select circuit 6.

Further, the address decoder 5 decodes the input address, and if it is for reading out a 24-bit instruction code, the selection circuit 23 causes the address circuit 3/4.
At the same time as selecting the address passed through the conversion circuit unit 22, the selection circuit 6 generates a control signal for selecting the instruction code passed through the code expansion circuit 4, and outputs it to the selection circuit 23 and the selection circuit 6.

Therefore, when the address for reading the 32-bit instruction code is output from the RISC CPU core 1, this address is not converted by the address 3/4 conversion circuit unit 22 and is passed to the memory control unit 21 as it is,
The main memory 3 is accessed. As a result, the memory control unit 21 reads the 32-bit instruction code from the main memory 3. At this time, the selection circuit 6 selects a 32-bit instruction code that does not pass through the code expansion circuit 4 and outputs it to the RISC CPU core 1. This gives R
The ISC CPU core 1 executes a 32-bit instruction code.

When the address for reading the 24-bit instruction code is output from the RISC CPU core 1, this address is converted by the address 3/4 conversion circuit unit 22 and passed to the memory control unit 21 to be transferred to the main memory. Access 3. As a result, the memory control unit 21 reads the 24-bit instruction code from the main memory 3. At this time, the selection circuit 6 selects the instruction code that has passed through the code extension circuit 4, that is, the instruction code expanded from 24 bits to 32 bits, and outputs it to the RISC CPU core 1. As a result, the RISC CPU core 1 has 3
Executes a 2-bit instruction code.

According to this embodiment, the main memory 3 has two
Even if 4-bit and 32-bit instruction codes are stored in a mixed manner, the RISC CPU core 1 can execute both instruction codes without changing its configuration, and thus without increasing the number of gates and decreasing the speed. You can

The present invention is not limited to the above-described embodiments, and can be implemented in various other modes in specific configurations, functions, actions, and effects without departing from the scope of the invention. .

[0031]

As described in detail above, according to the processor of the present invention, an instruction code having a size smaller than the originally executed size of the instruction code can be stored in the memory without increasing the number of gates or decreasing the speed. Can be stored in and executed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration according to a first exemplary embodiment of a processor of the present invention.

FIG. 2 is a diagram showing a configuration example of a pre-compression code and a post-compression code handled by the apparatus of FIG.

FIG. 3 is a block diagram showing a configuration according to a second exemplary embodiment of a processor of the present invention.

FIG. 4 is a block diagram showing a configuration example of a conventional RISC processor.

[Explanation of symbols]

1 RISC CPU core 2 Memory controller 3 main memory 4 Code expansion circuit 5 Address decoder 6,23 selection circuit 21 Memory controller 22 Address 3/4 conversion circuit section

Claims (5)

[Claims] 1. A processor in which a CPU core reads a code from a memory through a memory control device and executes the code, and an address conversion circuit for converting a read address output by the CPU core; and a memory control device for reading from the memory. A code decompression circuit for decompressing the size of the issued code, wherein the memory control device reads the code stored at the address converted by the address conversion circuit from the memory, and the CPU core A processor that executes code whose size has been converted by a decompression circuit. 2. The CPU core is a RISC CPU core, a 24-bit instruction code is stored in the memory, and the address conversion circuit converts an address output from the CPU core into 3/4. The processor according to claim 1, wherein the code expansion circuit expands a 24-bit instruction code into a 32-bit instruction code. 3. A processor in which a CPU core reads out a code from a memory via a memory control device and executes the code, and an address conversion circuit for converting a read address output by the CPU core, and a read from the memory by the memory control device. A code decompression circuit for decompressing the size of the issued code, a read address output by the CPU core, or an address converted by the address conversion circuit, and the selected one is passed to the memory control device. A selection circuit, and a code read from the memory by the memory control device or a code expanded by the code expansion circuit, and passed to the CPU core;
The memory control device reads the code stored in the address converted by the address conversion circuit or the original read address output by the CPU core from the memory, The processor, wherein the core executes the code whose size has been converted by the code expansion circuit or the original code read from the memory. 4. An address decoder for decoding a read address output from the CPU core to generate a control signal for controlling a selection operation of the first and second selection circuits. Processor described in. 5. The CPU core is a RISC CPU core, 32-bit and 24-bit instruction codes are mixedly stored in the memory, and the address conversion circuit outputs an address output from the CPU core to 3 / 5. The processor according to claim 3, wherein the code decompression circuit decompresses a 24-bit instruction code into a 32-bit instruction code by performing conversion to 4.