JP2002368710A - Multiplex transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiplex transmitter in compliance with the SONET(Synchronous Optical Network) standard and the ITUT-T(International Telecommunication Union-Telecommunication Standardization) standard that can suppress a scale of an idle pattern generating circuit with a large capacity supporting an idle pattern inserted to data when a channel is not in use. SOLUTION: The multiplex transmitter is configured such that an idle pattern generating section 2 divides an idle pattern in the unit of switches of an L×L switch section 101 in the multiplex transmitter and generates fragment patterns a, a' by taking notice that the same patterns are consecutive except basic patterns at the head of the idle pattern to be multiplexed as a property of the idle pattern. A selector section 102 selects a required number of the fragment patterns a, a' and inserts them to data transmitted when a channel is not in use, and a time multiplex section 6 multiplexes and outputs the result as output data 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex transmission apparatus, and more particularly to an idle pattern insertion method for inserting an idle pattern in a time division switch having a multiplexing function.

[0002]

2. Description of the Related Art In a multiplex transmission apparatus of this type, transmission quality is monitored between apparatuses, and an idle pattern is inserted to prevent an unnecessary monitoring alarm from being detected on the receiving side when a line is not used. . Conventionally, a method as shown in FIG. 31 has been used as a method for inserting the idle pattern. FIG. 31 shows a conventional configuration for inserting an idle pattern.

Referring to FIG. 31, in an apparatus for performing time-division exchange of a main signal using an L × L switch (L is an integer of 2 or more), input data 16 is input and time-divided into L data 7. A time-division unit 5, a main signal processing unit 1 which receives L data 7 as input and performs main signal processing to output L data 9, and an output data 17 which receives L data 9 as input
A time multiplexing unit 6 for inserting time multiplexing and OH (overhead) bytes into the data, an idle pattern generating unit 2 for generating an idle pattern to be inserted into the data 9, and an address 14
And a control memory unit 3 that interfaces with the host system 4 using the data 15 and generates the control bus 10 and the control bus 11 for the main signal processing unit 1, and a host system 4 that controls the entire unit at a high order. I have.

In the main signal processing unit 1, a switch unit 1 for selecting one of L input data 7 by a control bus 10 is used.
01 is provided for switching the number of signals L, and a selector 1 for selecting either the data 8 or the pattern A generated by the idle pattern generator by the control bus 11.
02 are provided for the number of idle pattern insertions.

Next, the operation of the configuration shown in FIG. 31 will be described. A line in the output data 17 (for example, #k of data 9)
When the line is used, the host system 4 outputs the address 14 and data 15 for selecting the line #k and the address 14 and data 15 for declaring the line use of the line #k to the control memory unit 3. The control memory unit 3 decodes the address 14 and recognizes that the control is for the line #k, inserts the content of the data 15 for selecting the line #k into the control bus 10, and transfers it to the switch 101. Similarly, data 15 for declaring the use of the line #k is inserted into the control bus 11 and transferred to the selector 102. The switch 101_ # k selects one of the L data 7 by the control bus 10 and outputs the data 8. After that, the selector 102 corresponding to the line #k selects the data 8 by the control bus 11 and outputs the data 9_ # k. Finally, the time multiplexing unit 6 time multiplexes the data 9 and inserts the OH byte to output the data 17.

Next, a line having output data 9 (for example, #
1 to #P) are unused, and the idle pattern A is used instead.
Is inserted, the upper system 4 outputs to the control memory unit 3 an address 14 and data 15 declaring that the lines # 1 to #P are not used. The control memory unit 3 decodes the address 15 to recognize the control of the lines # 1 to #P, and declares that the lines # 1 to #P are not used.
Is inserted into the control bus 11 and transferred to the selector 102.
The selector 102 corresponding to the lines # 1 to #P is connected to the control bus 1
1 to select pattern A and output data 9_ # 1 to #P
Is output. Finally, the time multiplexing unit 6 time multiplexes the data 9 and inserts the OH byte to output the data 17.

In the conventional example shown in FIG. 31, there is only one kind of idle pattern. However, in recent years, high-density multiplexing has been required due to the increase in information capacity and the progress of devices, and the multiplexing rule has been adapted accordingly. Idle patterns of size have been defined. Therefore, it is necessary for the device to support an idle pattern of each size.

FIG. 32 shows a configuration in which a conventional generation circuit supports two types of idle patterns. Main signal is L ×
In a device that switches by an L switch, a time division unit 5 that receives input data 16 as an input and time-divides the data into L data 7, and performs a main signal processing with the L data 7 as input and outputs L data 9. The main signal processing unit 1 receives the L data 9 as an input and time-multiplexes and outputs
A multiplexing unit 6 for inserting H bytes and the like, an idle pattern generation unit 2 for generating an idle pattern to be inserted, a control bus 10 and a control bus for the main signal processing unit 1 by interfacing with the host system 4 by an address 14 and data 15 There is provided a control memory unit 3 for generating an H.11 and an upper system 4 for controlling the entire system at a higher level.

In the main signal processing unit 1, a switch unit 1 for selecting one of L input data 7 by a control bus 10
01 is provided with the number L of signal switches, and the data 8 output from the switch 101 through the control bus 11 is provided.
And M selectors 102 for selecting one of the patterns A generated by the idle pattern A generator 201 in the idle pattern generator 2 are provided for the number of idle patterns inserted.

Further, the selector 102 is controlled by the control bus 11.
There are provided N selectors 103 for selecting either the data 12 output from the I / F or the pattern B generated by the idle pattern B generating unit 202 in the idle pattern generating unit, as many as the number of the idle patterns B inserted.

Next, in the idle pattern generator 2,
An idle pattern A generation unit 201 that generates an idle pattern A by mounting a pattern generator for the size of the idle pattern A, and an idle pattern B that mounts a pattern generator for the size of the idle pattern B
And an idle pattern B generation unit 202 that generates

Next, the operation of FIG. 32 will be described. FIG. 33 shows the bit allocation of data 15 to address 14 controlled by the host system. When a line (for example, #k of data 9) in the output data 17 is used, data 15 corresponding to the address 14 (FIG. 33: address value = k) from the host system 4 (see FIG. 33: when using the line). Is transferred. Further, the address 14 (FIG. 33: address value = L +
k ′ and L + M + k ″) and outputs the data 15 to the control memory unit 3.

The control memory unit 3 decodes the address 14 to recognize the control for the address k, inserts the input data selection control in the data 15 of the address value (k) into the control bus 10 and transfers it to the switch 101. Similarly, the address 14 is decoded to recognize the control for the address L + k ′, and the data 15 of the address value (L + k ′) is inserted into the control bus 11 and transferred to the selector 102. Similarly, the address 14 is decoded, the control for the address L + M + k ″ is recognized, the data 15 of the address value (L + M + k ″) is inserted into the control bus 13 and transferred to the selector 103.

The switch 101_ # k selects one of L input data 7 from the control bus 10 and outputs the data 8. Then, the selector 10 corresponding to the line #k
2 and 103 select the data 8 by the control bus 11 and output the output data # 9. Finally, the time multiplexing unit 6 time multiplexes the data 9 and inserts the OH byte to output the data 9. Here, k ′ is {an integer part of k / (L / M)} +
1, and k ″ is an integer part of ｛k / (L / N)｝ + 1.

Next, the line of data 9 (for example, #k to #k)
(K + (L / M))) and idle pattern A
To insert an address 14 from the host system 4 to the idle pattern A (FIG. 33: address value = L +
k ′) and data 15 are output to address 14 (FIG. 33: address value = L + M + k ″) and data 15 for idle pattern B. Control memory 3 decodes address 14 and decodes address 14 to L + k ′. Recognizing the control, inserting the pattern A selection control of the data 15 of the address value (L + k ') into the control bus 11 and
Transfer to 2.

Similarly, the address 14 is decoded to recognize the control for the address value (L + M + k "), and the control for selecting the data 12 of the data 15 of the address value (L + M + k") is inserted into the control bus 13 and transferred to the selector 103. .
Selector 102 corresponding to #k to # (k + (L / M))
Selects the pattern A by the control bus 11, and similarly, #
The selector 103 corresponding to k selects the data 12 by the control bus 13 and outputs the data 9. Finally, the time multiplexing unit 6
To multiplex the data 9 and insert the OH byte to output the data 17.

Next, the data 9 line (for example, #k to #k)
(K + (L / N))) unused and idle pattern B
Is inserted from the upper system 4 to the idle pattern B (FIG. 33: address value = L +
M + k ″) and data 15 are output to the control memory unit 3. The control memory unit 3 decodes the address 14 and
M + k "is recognized and the address value (L + M +
k ″) pattern 15 selection control of data 15
3 and transferred to the selector 103. #K to # (k
+ (L / N)) is connected to the control bus 1
3 to select pattern B and output data 9. Finally, the time multiplexing unit 6 time multiplexes the data 9 and inserts the OH byte to output the data 17.

[0018]

FIG. 32 shows an example in which two types of idle patterns are supported. Since it is necessary to have a pattern generation circuit including a counter for each normally supported idle pattern, There is a problem that as the number of types increases, the circuit scale of the pattern generation circuit increases. In particular, when the pattern length of the idle pattern is long or when the circuit scale is severely restricted, a serious problem occurs. Also, a selector for switching will be added.

It is anticipated that the demand for higher density multiplexing will be accelerated and idle patterns of larger capacity will be defined. Each time a circuit is added by redevelopment of an LSI or the like, there is a problem that a cost is generated and the cost is increased.

A main object of the present invention is to provide a multiplex transmission apparatus capable of suppressing an increase in the circuit size of a large-capacity idle pattern generation circuit that supports an idle pattern inserted when a line is not used. is there.

Another object of the present invention is to provide a multiplexer capable of flexibly coping with the addition of a large-capacity size idle pattern based on the multiplexing rule with respect to increasing the capacity of the multiplexing rule. .

[0022]

According to the present invention, a switch means for switching L input data (L is an integer of 2 or more) to L output in predetermined bit units; Idle pattern generating means for generating an idle pattern to be inserted into an idle portion of data; L selecting means for receiving one of the L outputs and the idle pattern as inputs and outputting one of them; A multiplexing means for time-multiplexing and outputting the L outputs of the equal selecting means, wherein the idle pattern generating means divides the idle pattern into switching units of the switch means. A multiplex transmission device configured to generate a fragment pattern is obtained.

Each of the L selecting means is configured to receive the plurality of fragment patterns and one of the L outputs as inputs and to output one of them. In addition, when the idle pattern is viewed in the switching unit, except for the first basic pattern, the rest of the pattern is a continuation of the same pattern, and the idle pattern generating means includes the basic pattern and the switching as the fragment pattern. It is characterized by comprising patterns divided in units.

The operation of the present invention will be described. In the multiplex transmission apparatus, in an idle pattern inserted so as not to detect an unnecessary alarm when the line is not used, the common point of each size of the pattern is determined when the pattern is time-divided to a switch switching unit (52 Mb / s). Paying attention to the fact that the basic pattern is at the top of the multiplex and the subsequent pattern is the same pattern, the pattern generator including a counter for each generated idle pattern is not installed, and only the required number of fragment patterns divided in switch units Generate and insert.
Finally, the data is multiplexed by a subsequent interface board so that a desired idle pattern is formed only at that time. Therefore, there is a feature that an idle pattern can be inserted without depending on the size of the idle pattern.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, and the same parts as those in FIGS. 31 and 32 are denoted by the same reference numerals. In an embodiment of the present invention, in a device for performing L × L switching of a main signal, a time division unit 5 that time-divides input data 16 into L data 7 using input data 16 as an input;
A main signal processing unit 1 that receives L data 7 as input and performs main signal processing to output L data 9, and inserts L data 9 as input and time multiplexes and OH bytes into output data 17. A time multiplexing unit 6, an idle pattern generation unit 2 for generating a fragment pattern (a, a ',...) To be inserted into the data 9, an interface 14 with the host system 4 using the address 14 and the data 15, and a main signal processing unit 1 In addition, a control memory unit 3 for generating a control bus 10 and a control bus 11 and a higher-level system 4 for controlling the entire system at a higher level are provided.

In the main signal processing unit 1, the control bus 1
There are L switches 101 that select one of L data 7 from 0 and output data 8 and constitute an L × L switch that switches data in a predetermined bit unit. There are provided L selectors 102 for selecting any one of a total of R data 8 and fragment patterns (a, a ',...) By the control bus 11.

The idle pattern generation section 2 generates a fragment pattern a generation section 201 for generating a fragment pattern a having a switch (approximately 52 Mb / s) unit counter, and generates a fragment pattern a 'having a switch-based counter similarly. And a fragment pattern a ′ generation unit 202 that performs the above.

FIG. 2 shows an idle pattern generation method using fragment pattern multiplexing according to the present invention. The common point between the idle pattern A and the idle pattern B is that when each idle pattern is time-divided into a switch unit, there is a continuous pattern of basic patterns a (1 to p or 1 to q) at the beginning of multiplexing. Is a continuation of the same pattern a ′. Focusing on this feature, in order to support each idle pattern, a required number of fragment patterns per switch (two types of fragment patterns a and fragment patterns a 'in FIG. 2) are provided.

The operation of the configuration shown in FIG. 1 will be described below. First, the input data 16 is input, time-divided by the time division unit 5, and L data 7 are output to the main signal processing unit 1. FIG. 3 shows an example of bit allocation of an address 14 controlled by the host system 4 and data 15 corresponding to the address.

When a line (for example, #k of data 9) in the output data 17 is used, an address 14 and data 15 are output from the host system 4 to the control memory unit 3. The control memory unit 3 includes a switch 10
The selection control for 1_ # k is inserted and transferred to the switch 101. Also, the line use control is inserted into the control bus 11 and transferred to the selector 102. The switch 101_ # k receives the control bus 10, selects one of the L input data 7 and outputs the data 8. The selector 102_ # k receives the control bus 11, selects the data 8 from the data 8 and various fragment patterns, and outputs the data 9_ # k. Finally, the time multiplexing unit 6 time-multiplexes the data 9 and inserts an OH byte to output data 17.

Next, a line having output data 9 (for example, #
The operation when (k + 1) to # (k + P)) are unused and the idle pattern A is inserted instead will be described. The host system 4 outputs the address 14 and the data 15 to the control memory unit 3. The control memory unit 3 inserts the pattern a selection control into the control bus 11 and transfers it to the selectors 102 _ # (k + 1) to # (k + p).
Similarly, selectors 102 _ # (k + p + 1) to # (k + p + 1)
For P), the pattern a 'selection control is inserted into the control bus 11 and transferred. Selector 102 _ # (k + 1) to #
(K + p) receives the control bus 11, selects and outputs the fragment pattern a, and selects the selectors 102 _ # (k + p + 1) to # (k
+ P) receives the control bus 11 and selectively outputs the fragment pattern a '. Data 9 _ # (k + 1) to # generated above
(K + P) is time multiplexed by the time multiplexing unit 6 at the subsequent stage, an OH byte is inserted, and an idle pattern A is generated in the output data 17.

Next, a line having output data 9 (for example, #
The operation when (k + 1) to # (k + Q)) are not used and the idle pattern B is inserted instead will be described. The host system 4 outputs the address 14 and the data 15 to the control memory unit 3. The control memory unit 3 inserts the pattern a selection control into the control bus 11 and transfers it to the selectors 102 _ # (k + 1) to # (k + q).
Similarly, selectors 102 _ # (k + q + 1) to # (k +
For Q), the pattern a 'selection control is inserted into the control bus 11 and transferred. Selector 102 _ # (k + 1) to #
(K + q) receives the control bus 11, selects and outputs the fragment pattern a, and selects the selectors 102 _ # (k + q + 1) to # (k
+ Q) receives the control bus 11 and selectively outputs the fragment pattern a '. Data 9 _ # (k + 1) generated above
# (K + Q) is time multiplexed by the time multiplexing unit 6 at the subsequent stage, an OH byte is inserted, and the idle pattern B
Is generated.

When the main signal processing execution state is read from the host system 4, in the setting method of the present invention, only the hardware execution state (fragment pattern type and line unused) is read, and the idle pattern type and section are not read. Cannot be read. Therefore, an idle pattern type identification bit is added to a vacant bit generated when an idle pattern is inserted.
Can be read out, the execution state can be read out in the same manner as in the conventional idle pattern setting method.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. In this embodiment, the main signal is switched by a 768 × 768 switch. Referring to FIG. 4, a time-division unit 5 that time-divides input data 16 into 768 pieces of data 7 as input, and a main signal that performs main signal processing with 768 pieces of data 7 as input and outputs 768 pieces of data 9 A processing unit 1; a time multiplexing unit 6 which time-multiplexes 768 pieces of data 9 as input to output data 17; and an idle pattern generation unit 2 which generates fragment patterns (1 ′, 2 ′..., 7 ′) to be inserted. , An address 14 and data 15 to interface with the host system 4 and the main signal processing unit 1
A control memory unit 3 for generating a control bus 10 and a control bus 11, and a higher-level system 4 for controlling the entire system at a higher level
Are provided.

In the main signal processing unit 1, there are 768 switches 101 for selecting one out of 768 data 7 by the control bus 10 and outputting the data 8, and the control bus 11 controls the data 8 and this device. "1" fixed AIS (alarm indicator signal) inserted downstream when abnormal
And 768 selectors 102 for selecting any of the fragment patterns (1 ′, 2 ′..., 7 ′). In the idle pattern generator 2, fragment pattern generators 201 to 2 for generating seven types of fragment patterns for each switch are provided.
07 is present.

The idle patterns supported in FIG.
In order to support different standards as well as different sizes, a total of 15 types of idle patterns are supported as described below.

SONET (Synchronous Optical Network)
k) Standards (1) STS (Synchronous Transport Signal) -1 size idle pattern (about 52 Mb / s) (2) STS-3c size idle pattern (about 155)
Mb / s) (3) STS-12c size idle pattern (about 62
(4) STS-48c size idle pattern (approximately 2.
4 Gb / s) (5) STS-192c size idle pattern (about 9.6 Gb / s).

ITU-T standard (6) STM (Synchronous Transfer Mode) -0 [V
C (Virtual Container) 3] size idle pattern (about 52 Mb / s) (7) STM-1 [VC4] size idle pattern (about 155 Mb / s) (8) STM-4 [VC4-4c] size idle pattern (about (622 Mb / s) (9) STM-16 [VC4-16c] size idle pattern (about 2.4 Gb / s) (10) STM-64 [VC4-64c] size idle pattern (about 9.6 Gb / s).

Domestic specifications (11) STM-0 [VC3] size idle pattern (about 52 Mb / s) (12) STM-1 [VC4] size idle pattern (about 155 Mb / s) (13) STM-4 [VC4- 4c] size idle pattern (about 622 Mb / s) (14) STM-16 [VC4-16c] size idle pattern (about 2.4 Gb / s) (15) STM-64 [VC4-64c] size idle pattern (about 9) .6 Gb / s).

The above 15 types are all switched (approximately 5
Considering the fragment pattern divided into 2 Mb / s), FIG.
12 to 26 using the seven types of fragment patterns of FIGS.
All 15 types of idle patterns can be generated by the multiplexing method. Therefore, only seven types of fragment pattern generation circuits are mounted in the idle pattern generation unit.

The operation of this embodiment shown in FIG. 4 will be described below. First, the input data 16 is input to the time division unit 5.
And 768 pieces of data 7 are output to the main signal processing unit 1 by time division. FIG. 27 shows the bit assignment of the data 15 corresponding to the address 14 controlled by the host system 4.

When a certain line (for example, #k of data 9) in the output data 17 is used, the address 14 (address value = k) and the data 15 (line use b
It (b10) = 1 and input data 7_ # k are output to the control memory unit 3. After the control memory unit 3 decodes the address 14 and recognizes that the control is for the line #k, the control memory unit 3 inserts the selection control bit of the switch 101 — #k in the data 15 into the control bus 10 and transfers it to the switch 101.

Similarly, a data value (data 8 is selected) is inserted into the control bus 11 from the line use bit of the data 15 and transferred to the selector 102. The switch 101 — #k receives the control bus 10 and receives one of the 768 input data 7.
A book is selected and data 8 is output. The subsequent selector 102_ # k receives the control bus 11 and receives data 8, AI
S, selects data 8 from the nine fragment patterns and outputs output data #k. Finally, the time multiplexing unit 6 time multiplexes the data 9 and inserts the OH byte to output the data 17.
Next, a setting method and the like when the line (for example, # 1) of the output data 9 is unused and each idle pattern is inserted will be described. FIG. 28 shows a truth table of the selector 102.

First, the SONET of (1) is applied to a certain line (for example, # 1 of data 9) in the output data 17.
When the standard STS-1 idle pattern is to be inserted, the address 14 (address value = 1) and the data 15 (line use bit (b10) = 0 and pattern selection bit (b2-0) = 001) are transmitted from the host system 4 to the control memory. Part 3
Output to The control memory unit 3 decodes the address 14 and recognizes that it is the control for # 1.
2_ Insert the fragment pattern 1 'selection control for # 1 into the control bus 11 and transfer it. The selector 102_ # 1 receives the control bus 11, selects the fragment pattern 1 ', and outputs the output data 9_ # 1. Finally, the time multiplexing unit 6 time multiplexes the data 9 and inserts the OH byte to output the data 17.

Next, for a certain line (for example, # 1 to # 3 of data 9) in the output data 17, the SONET of (2)
If you want to insert the standard STS-3c idle pattern,
Address 14 (address value = 1) and data 15 (line use bit (b10) = 0 and pattern selection bit (b2-0) = 001) are sent from upper system 4 to address 1
4 (address value = 2, 3) and data 15 (line use bi)
t (b10) = 0 and the pattern selection bit (b2-
0) = 010) is output to the control memory unit 3. The control memory unit 3 decodes the address 14 and recognizes it as the control for # 1 to # 3, and inserts the fragment pattern 1 ′ selection control for the selector 102_ # 1 into the control bus 11 and transfers it. Similarly, fragment pattern 2 ′ selection control for the selector 102_ # 2 # 3 is inserted into the control bus 11 and transferred.
The selector 102_ # 1 receives the control bus 11, selects the fragment pattern 1 ', and similarly selects the selectors 102_ # 2 to # 3.
Receives the control bus 11, selects the fragment pattern 2 ', and outputs the output data 9. Finally, the time multiplexing unit 6 time-multiplexes # 1 to # 3 of the data 9 and inserts an OH byte to generate the idle pattern (2) in the data 17.

Next, for a certain line (for example, # 1 to # 12 of data 9) in the output data 17, the SONE of (3)
When it is desired to insert the T standard STS-12c idle pattern, the upper system 4 sends the address 14 (address value =
1) and data 15 (line use bit (b10) = 0 and pattern selection bit (b2-0) = 001), address 14 (address value = 2 to 12) and data 15 (line use bit (b10) = 0) And pattern selection bit
(B2-0) = 010) to the control memory unit 3. The control memory unit 3 decodes the address 14 and
To # 12 and recognizes that the selector 102_ # 1
Is inserted into the control bus 11 and transferred. Similarly, selectors 102_ # 2 to # 12
Is inserted into the control bus 11 and transferred. The selector 102_ # 1 receives the control bus 11 and selects the fragment pattern 1 '.
2_ # 2 to # 12 receive the control bus 11, select the fragment pattern 2 ', and output the output data 9. Finally, the time multiplexing unit 6 time-multiplexes # 1 to # 12 of the data 9 and inserts an OH byte to generate the idle pattern (3) in the data 17.

Next, for a certain line (for example, # 1 to # 48 of data 9) in the output data 17, the SONE of (4)
When it is desired to insert the T standard STS-48c idle pattern, the host system 4 sends the address 14 (address value =
1) and data 15 (line use bit (b10) = 0 and pattern selection bit (b2-0) = 001), address 14 (address value = 2-48) and data 15 (line use bit (b10) = 0) And pattern selection bit
(B2-0) = 010) to the control memory unit 3. The control memory unit 3 decodes the address 14 and
~ # 48 and the selector 102_ # 1
Is inserted into the control bus 11 and transferred. Similarly, selectors 102_ # 2- # 48
Is inserted into the control bus 11 and transferred. The selector 102_ # 1 receives the control bus 11 and selects the fragment pattern 1 '.
2_ # 2 to # 48 receive the control bus 11, select the fragment pattern 2 ', and output the output data 9. Finally, the time multiplexing unit 6 time-multiplexes # 1 to # 48 of the data 9 and inserts an OH byte to generate the idle pattern (4) in the data 17.

Next, the SON of (5) is performed for a certain line (for example, # 1 to # 192 of data 9) in the output data 17.
When the ET standard STS-192c idle pattern is to be inserted, the address 14 (address value = 1) and the data 15 (line use bit (b10) = 0 and pattern selection bit (b2-0) = 001) are sent from the host system 4. Address 14 (address value = 2 to 192) and data 15
(Line use bit (b10) = 0 and pattern selection b
It (it (b2-0) = 010) is output to the control memory unit 3. The control memory unit 3 decodes the address 14 and recognizes that it is the control for # 1 to # 192, and
_ Fragment pattern 1 'selection control for # 1 is controlled by control bus 1.
Insert in 1 and transfer. Similarly, selectors 102_ # 2-
The fragment pattern 2 'selection control for # 192 is inserted into the control bus 11 and transferred. The selector 102_ # 1 receives the control bus 11 and selects the fragment pattern 1 '. Similarly, the selectors 102_ # 2 to # 192 receive the control bus 11 and select the fragment pattern 2' and output the output data 9. Finally, the time multiplexing unit 6 time-multiplexes # 1 to # 192 of the data 9 and inserts an OH byte to generate an idle pattern (5) in the data 17.

Next, for a certain line (for example, # 1 of data 9) in the output data 17, the ITU-T standard S of (6)
When it is desired to insert a TM-0 idle pattern, the host system 4 sends an address 14 (address value = 1) and a data 1
5 (line use bit (b10) = 0 and pattern selection bit (b2-0) = 011) are output to the control memory unit 3. The control memory unit 3 decodes the address 14 and recognizes that it is the control for # 1, and then selects the selector 102_ #
The fragment pattern 3 ′ selection control for 1 is inserted into the control bus 11 and transferred. The selector 102_ # 1 is connected to the control bus 11
Received, the fragment pattern 3 'is selected and the output data 9_ #
Outputs 1. Finally, the time multiplexing unit 6 time multiplexes the data 9 and inserts the OH byte to output the data 17.

Next, for a certain line in the output data 17 (for example, # 1 to # 3 of data 9), the ITU-T of (7)
When a standard STM-1 idle pattern is to be inserted, the address 14 (address value = 1) and the data 15 (line use bit (b10) = 0 and pattern selection bit (b2-0) = 011) are sent from the upper system 4. 14
(Address value = 2, 3) and data 15 (line use bit)
(B10) = 0 and pattern selection bit (b2-0)
= 100) to the control memory unit 3. The control memory unit 3 decodes the address 14 and recognizes it as the control for # 1 to # 3, and inserts the fragment pattern 3 ′ selection control for the selector 102_ # 1 into the control bus 11 and transfers it.
Similarly, the fragment pattern 4 ′ selection control for the selectors 102_ # 2 to # 3 is inserted into the control bus 11 and transferred. The selector 102_ # 1 receives the control bus 11 and selects the fragment pattern 3 '. Similarly, the selectors 102_ # 2 and # 3 receive the control bus 11 and select the fragment pattern 4' and output the output data 9. Finally, the time multiplexing unit 6 # of the data 9
Time multiplexing of 1 to # 3 and insertion of OH byte
The idle pattern of (7) is generated in 7.

Next, for a certain line (for example, # 1 to # 12 of data 9) in the output data 17, the ITU-
If you want to insert T standard STM-4 idle pattern,
Address 14 (address value = 1) and data 15 (line use bit (b10) = 0 and pattern selection bit (b2-0) = 011) are sent from upper system 4 to address 1
4 (address value = 2 to 12) and data 15 (line use b)
it (b10) = 0 and the pattern selection bit (b2-
0) = 100) is output to the control memory unit 3. The control memory unit 3 decodes the address 14 and # 1 to # 12
, And the fragment pattern 3 ′ selection control for the selector 102_ # 1 is inserted into the control bus 11 and transferred. Similarly, the fragment pattern 4 ′ selection control for the selectors 102_ # 2 to # 12 is inserted into the control bus 11 and transferred. The selector 102_ # 1 receives the control bus 11, selects the fragment pattern 3 ', and similarly selects the selector 102_ # 2.
To # 12 receive the control bus 11, select the fragment pattern 4 ', and output the output data 9. Finally, the time multiplexing unit 6 time-multiplexes the data # 1 to # 12 and inserts an OH byte to generate an idle pattern (8) in the data 17.

Next, for a certain line (for example, # 1 to # 48 of data 9) in the output data 17, the ITU-
When it is desired to insert a T-standard STM-16 idle pattern, the host system 4 sends an address 14 (address value =
1) and data 15 (line use bit (b10) = 0 and pattern selection bit (b2-0) = 011), address 14 (address value = 2-48) and data 15 (line use bit (b10) = 0) And pattern selection bit
(B2-0) = 100) is output to the control memory unit 3. The control memory unit 3 decodes the address 14 and
~ # 48 and the selector 102_ # 1
Is inserted into the control bus 11 and transferred. Similarly, selectors 102_ # 2- # 48
Is inserted into the control bus 11 and transferred. The selector 102_ # 1 receives the control bus 11 and selects the fragment pattern 3 '.
2_ # 2 to # 48 receive the control bus 11, select the fragment pattern 4 'and output the output data 9. Finally, the time multiplexing unit 6 time-multiplexes # 1 to # 48 of the data 9 and inserts an OH byte to generate an idle pattern (9) in the data 17.

Next, with respect to a certain line in the output data 17 (for example, # 1 to # 192 of data 9), the IT of (10)
When it is desired to insert a UTM standard STM-64 idle pattern, the host system 4 sends an address 14 (address value =
1) and data 15 (line use bit (b10) = 0 and pattern selection bit (b2-0) = 011), and address 14 (address value = 2 to 192) and data 15 (line use bit (b10) = 0) And pattern selection bit
(B2-0) = 100) is output to the control memory unit 3. The control memory unit 3 decodes the address 14 and
To # 192, and the selector 102_ #
The fragment pattern 3 ′ selection control for 1 is inserted into the control bus 11 and transferred. Similarly, selectors 102_ # 2 to # 1
Control of the fragment pattern 4 ′ selection for the control bus 11
And transfer. The selector 102_ # 1 is the control bus 1
1, the selector 102_ # 2 to # 192 similarly receive the control bus 11, select the fragment pattern 4 'and output the output data 9. Finally, the time multiplexing unit 6 time-multiplexes data # 1 to # 192 of the data 9 and inserts an OH byte to generate an idle pattern (10) in the data 17.

Next, for a certain line (for example, # 1 of data 9) in the output data 17, the domestic specification STM of (11)
When it is desired to insert a −0 idle pattern, the higher system 4 sends the address 14 (address value = 1) and the data 15
(Line use bit (b10) = 0 and pattern selection b
It (it (b2-0) = 101) is output to the control memory unit 3. The control memory unit 3 decodes the address 14 and recognizes that it is the control for # 1, and then selects the selector 102_ # 1.
Is inserted into the control bus 11 and transferred. The selector 102_ # 1 receives the control bus 11, selects the fragment pattern 5 ', and outputs the data 9_ # 1.
Is output. Finally, the time multiplexing unit 6 time multiplexes the data 9 and inserts the OH byte to output the data 17.

Next, for a certain line (for example, # 1 to # 3 of data 9) in the output data 17, (12) the domestic specification S
When a TM-1 idle pattern is to be inserted, the address 14 (address value = 1) and the data 1
5 (line use bit (b10) = 0 and pattern selection bit (b2-0) = 101) are converted into address 14 (address value = 2, 3) and data 15 (line use bit (b1
0) = 0 and pattern selection bit (b2-0) = 11
0) is output to the control memory unit 3. Control memory unit 3
Decodes the address 14 and recognizes it as the control for # 1 to # 3, inserts the fragment pattern 5 ′ selection control for the selector 102_ # 1 into the control bus 11, and transfers it. Similarly, the fragment pattern 6 ′ selection control for the selectors 102_ # 2 to # 3 is inserted into the control bus 11 and transferred. The selector 102_ # 1 receives the control bus 11 and selects the fragment pattern 5 '. Similarly, the selectors 102_ # 2 and # 3 receive the control bus 11 and select the fragment pattern 6' and output the output data 9. Finally, the time multiplexing unit 6 sets the data # 1
# 3 is time multiplexed and data 17
The idle pattern of (12) is generated.

Next, when a domestic specification STM-4 idle pattern of (13) is to be inserted into a certain line (for example, # 1 to # 12 of data 9) in the output data 17, the higher system 4 sends the address 14 ( Address value = 1) and data 15 (line use bit (b10) = 0 and pattern selection bit (b2-0) = 101) are stored in address 14
(Address value = 2 to 4) and data 15 (line use bit)
(B10) = 0 and pattern selection bit (b2-0)
= 111) to address 14 (address value = 5 to 12)
And data 15 (line use bit (b10) = 0 and pattern selection bit (b2-0) = 110) are output to the control memory unit 3. The control memory unit 3 stores the address 14
Is decoded and recognized as control for # 1 to # 12, and fragment pattern 5 ′ selection control for selector 102_ # 1 is inserted into control bus 11 and transferred. Similarly, selector 102
_ Insert the fragment pattern 7 'selection control for # 2 to # 4 into the control bus 11 and transfer it. Similarly, the selector 102_
The fragment pattern 6 'selection control for # 5 to # 12 is inserted into the control bus 11 and transferred. The selector 102_ # 1 receives the control bus 11 and selects the fragment pattern 5 '. Similarly, the selectors 102- # 2 to # 4 receive the control bus 11 and selects the fragment pattern 7', and similarly the selector 102_ # 5.
To # 12 receive the control bus 11, select the fragment pattern 6 ', and output the output data 9. Finally, the time multiplexing unit 6 time-multiplexes the data # 1 to # 12 and inserts an OH byte to generate an idle pattern (13) in the data 17.

Next, when it is desired to insert the STM-16 idle pattern of the domestic specification (14) into a certain line (for example, # 1 to # 48 of data 9) in the output data 17, the host system 4 sends the address 14 ( Address value = 1) and data 15 (line use bit (b10) = 0 and pattern selection bit (b2-0) = 101) are stored in address 14
(Address value = 2 to 16) and data 15 (line use bi)
t (b10) = 0 and the pattern selection bit (b2-
0) = 111) with address 14 (address value = 17 to
48) and data 15 (line use bit (b10) = 0 and pattern selection bit (b2-0) = 110) are output to the control memory unit 3. The control memory unit 3 decodes the address 14 and recognizes it as the control for # 1 to # 48, and inserts the fragment pattern 5 ′ selection control for the selector 102_ # 1 into the control bus 11 and transfers it. Similarly, the fragment pattern 7 'selection control for the selectors 102_ # 2 to # 16 is inserted into the control bus 11 and transferred. Similarly, the fragment pattern 6 ′ selection control for the selectors 102_ # 17 to # 48 is inserted into the control bus 11 and transferred. Selector 12
_ # 1 receives the control bus 11 and selects the fragment pattern 5 ′. Similarly, the selectors 102_ # 2 to # 16
1, the selector 102_ # 17 to # 48 similarly receive the control bus 11, select the fragment pattern 6 ', and output the output data 9. Finally, the time multiplexing unit 6 time multiplexes the data # 1 to # 48 and
The idle pattern of (14) is generated in the data 17 by inserting H bytes.

Next, when it is desired to insert the domestic specification STM-64 idle pattern of (15) into a certain line (for example, # 1 to # 192 of data 9) in the output data 17,
Address 14 (address value = 1) and data 15 (line use bit (b10) = 0 and pattern selection bit (b2-0) = 101) are sent from host system 4 to address 1
4 (address value = 2 to 64) and data 15 (line use b)
it (b10) = 0 and the pattern selection bit (b2-
0) = 111) with the address 14 (address value = 65-65).
192) and data 15 (line use bit (b10) = 0)
And the pattern selection bit (b2-0) = 110) are output to the control memory unit 3. The control memory unit 3 decodes the address 14 and recognizes it as the control for # 1 to # 192, and the fragment pattern 5 ′ for the selector 102_ # 1.
The selection control is inserted into the control bus 11 and transferred. Similarly, the fragment pattern 7 'selection control for the selectors 102_ # 2 to # 64 is inserted into the control bus 11 and transferred. Similarly, the fragment pattern 6 ′ selection control for the selectors 102_ # 65 to # 192 is inserted into the control bus 11 and transferred. The selector 102_ # 1 receives the control bus 11 and selects the fragment pattern 5 '. Similarly, the selectors 102_ # 2 to # 64 receive the control bus 11 and selects the fragment pattern 7', and similarly, the selectors 102_ # 65 to # 192 receives the control bus 11, selects the fragment pattern 6 ', and outputs the output data 9. Finally, the time multiplexing unit 6 time multiplexes the data # 1 to # 192 and inserts an OH byte into the data 17 (1
The idle pattern of 5) is generated.

In the method of setting the fragment pattern, when the execution state of the main signal processing unit 1 (or the control memory unit 3) is read from the host system, only the fragment pattern type is readable, so the head position and pattern size of the idle pattern are read. Can not do. Therefore, when an idle pattern is inserted as shown in FIG. 29, there are unused bits that are not used by hardware. An execution state equivalent to setting a pattern can be read.

Finally, as an effect, as shown in FIG.
When the counter is converted to 1, the conventional example requires 768, whereas the configuration of the present invention can be configured with only 7 so that the circuit can be greatly reduced. It should be noted that the present invention is not limited to the above-described embodiment, and it is obvious that the embodiment can be appropriately modified within the scope of the technical idea of the present invention.

[0061]

According to the present invention, the circuit size of the pattern generator circuit including the counter can be reduced with respect to the idle pattern generation circuit, and it is extremely effective especially when a large capacity size idle pattern is supported. The reason is that, conventionally, a pattern generator is mounted for each idle pattern, and the circuit scale increases when a large number of types of idle patterns are supported, but in the present invention, the switch unit (52 Mb / s) By combining and multiplexing the fragment patterns divided into
Since only a few types of small-capacity pattern generator circuits are required, the effect of greatly reducing the circuit scale can be obtained.

Further, it is easy to add support for each large capacity idle pattern. The reason is that, conventionally, a unique pattern generator was mounted for each idle pattern, so that the addition of an idle pattern required hardware redevelopment of an LSI or the like. Is shared and combined and multiplexed. Since the combination is controlled only by setting the number of multiplexes to be increased from the host system, it is possible to flexibly respond to the addition of an idle pattern by software.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an idle pattern insertion circuit according to the present invention.

FIG. 2 is a diagram showing a method of generating an idle pattern by fragment pattern multiplexing in FIG. 1;

FIG. 3 shows data 15 for address 14 in FIG.
FIG. 4 is a diagram showing bit allocation of the.

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a diagram showing a fragment pattern 1 'in the embodiment of FIG.

FIG. 6 is a diagram showing a fragment pattern 2 ′ in the embodiment of FIG.

FIG. 7 is a diagram showing a fragment pattern 3 ′ in the embodiment of FIG.

FIG. 8 is a diagram showing a fragment pattern 4 ′ in the embodiment of FIG.

FIG. 9 is a diagram showing a fragment pattern 5 'in the embodiment of FIG.

FIG. 10 is a diagram showing a fragment pattern 6 'in the embodiment of FIG.

11 is a diagram showing a fragment pattern 7 'in the embodiment of FIG.

FIG. 12 is a diagram showing a SONET standard STS-1 idle pattern and a multiplexing method in the embodiment of FIG. 4;

FIG. 13 is a diagram showing a SONET standard STS-3c idle pattern and a multiplexing method in the embodiment of FIG. 4;

FIG. 14 is a diagram showing an idle pattern and a multiplexing method of the SONET standard STS-12c in the embodiment of FIG. 4;

FIG. 15 is a diagram showing an SONET standard STS-48c idle pattern and a multiplexing method in the embodiment of FIG. 4;

FIG. 16 is a diagram showing a SONET standard STS-192c idle pattern and a multiplexing method in the embodiment of FIG. 4;

FIG. 17 is a diagram showing an ITU-T standard STM-0 idle pattern and a multiplexing method in the embodiment of FIG. 4;

18 is a diagram showing an ITU-T standard STM-1 idle pattern and a multiplexing method in the embodiment of FIG. 4;

FIG. 19 is a diagram showing an ITU-T standard STM-4 idle pattern and a multiplexing method in the embodiment of FIG. 4;

FIG. 20 is a diagram showing an ITU-T standard STM-16 idle pattern and a multiplexing method in the embodiment of FIG. 4;

21 is a diagram showing an ITU-T standard STM-64 idle pattern and a multiplexing method in the embodiment of FIG. 4;

FIG. 22 is a diagram showing a domestic specification STM-0 idle pattern and a multiplexing method in the embodiment of FIG. 4;

FIG. 23 is a diagram showing a domestic specification STM-1 idle pattern and a multiplexing method in the embodiment of FIG. 4;

FIG. 24 is a diagram showing a domestic specification STM-4 idle pattern and a multiplexing method in the embodiment of FIG. 4;

25 is a diagram showing a domestic specification STM-16 idle pattern and a multiplexing method in the embodiment of FIG. 4;

FIG. 26 is a diagram showing a domestic specification STM-64 idle pattern and a multiplexing method in the embodiment of FIG. 4;

FIG. 27 is a diagram showing bit allocation of data 6 to address 5 in the embodiment of FIG.

FIG. 28 is a diagram illustrating the operation of the selector 102 in the embodiment of FIG. 4;

FIG. 29 is a diagram showing bit allocation in consideration of reading from the upper system in the embodiment of FIG. 4;

FIG. 30 is a diagram showing an effect of the embodiment of FIG. 4 as compared with a conventional example.

FIG. 31 is a block diagram showing a conventional idle pattern insertion circuit.

FIG. 32 is a block diagram showing a case where various types of idle patterns in FIG. 31 are supported.

FIG. 33 shows data 6 for address 5 in FIG.
FIG. 4 is a diagram showing bit allocation of the.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main signal processing part 2 Idle pattern generation part 3 Control memory part 4 Host system 5 Time division part 6 Time multiplex part 7-9,15 Data 10,11 Control bus 14 Address 16 Input data 17 Output data 101 Switch 102 Selector 201 Fragment Pattern a generator 202 Fragment pattern a 'generator

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Katsunobu Shimanuki, Inventor 3-18-21, Shibaura, Minato-ku, Tokyo Inside NEC Engineering Co., Ltd. (72) Yoshikazu Nishioka 3-18-21, Shibaura, Minato-ku, Tokyo No. NEC Engineering Corporation F term (reference) 5K028 AA07 KK01 MM04 TT01 5K069 AA16 BA02 CB01 CB08 DB11 EA07 EA11 FD00

Claims (3)

[Claims] 1. A switch for switching L input data (L is an integer of 2 or more) to L output in predetermined bit units, and an idle pattern to be inserted into an idle portion of the data. And an idle pattern generating means for generating one of the L outputs and the idle pattern as inputs and outputting one of them.
A multiplexing transmission device comprising: a plurality of selection units; and a multiplexing unit that multiplexes and outputs the L outputs of the selection units. The idle pattern generation unit converts the idle pattern into the switch unit. A multiplex transmission apparatus configured to generate a plurality of fragment patterns divided into switching units. 2. The apparatus according to claim 1, wherein each of the L selection means is configured to receive the plurality of fragment patterns and one of the L outputs as inputs and to output one of them. The multiplex transmission apparatus according to claim 1. 3. The idle pattern, when viewed in the switching unit, is a continuation of the same pattern except for the first basic pattern, and the idle pattern generating means outputs the basic pattern as the fragment pattern. 3. The multiplex transmission apparatus according to claim 2, wherein the multiplex transmission apparatus comprises a pattern divided by the switching unit.