JP2002368092A - Programmable logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent loss of connection information of a programmable logic circuit caused by power-off and eliminate the need of rewriting the connection information when power is on again. SOLUTION: A non-destructively readable ferroelectric memory is used for holding connection information. Transfer gates 21 are disposed on intersections of longitudinal and transversal transmission lines for transferring logic signals between a plurality of logic circuit blocks and their on- and off-states are determined by outputs of ferroelectric capacitors 51, 52 constituting the ferroelectric memory connected to the transfer gates 21. The voltages applied to the capacitors 51, 52 are in a range where their polarization returns to original displacements, and hence the connection information of the ferroelectric memory cells is never lost but the non-destructive read is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic circuit using an output of a ferroelectric memory as connection information of a logic circuit.

[0002]

2. Description of the Related Art Programmable logic circuits are known as circuits that allow a user to write logic functions at hand.

In this system, many logic circuits and the like are arranged on a chip in advance, and the logic circuits and the like are connected to each other via a programmable switch. Therefore, a desired logic function can be realized by the user switching these many switches according to a predetermined pattern.

FIG. 7 is a block diagram of a programmable logic circuit according to the prior art.

In FIG. 7, a plurality of logic blocks 12 having an arbitrary logic function or programmable are arranged, and a plurality of vertical transmission lines 15 and a plurality of horizontal transmission lines 16 are provided between the logic blocks 12. Each logic block 12 is connected to a nearby vertical transmission line 15 or horizontal transmission line 16 by a vertical input / output line 13 and a horizontal input / output line 14.

The switching of transmission signals between logical blocks is performed by a switch matrix 11 at the intersection of a vertical transmission line 15 and a horizontal transmission line 16.

[0008] That is, as shown in FIG. 8, each logical block is determined by the connection state in the switch matrix of whether or not each intersection 17 of the vertical transmission line 15 and the horizontal transmission line 16 is electrically connected. One logic circuit as a whole is constructed.

A vertical transmission line 15 and a horizontal transmission line 16
Is determined by an output of a circuit as shown in FIG. 8, for example.

FIG. 9 is a circuit diagram showing a connection circuit at a certain intersection in a switch matrix of a conventional programmable logic circuit.

Referring to FIG. 9, N-type pass transistor 22
And the P-type pass transistor 23 are connected in parallel with each other. The first terminal 24 of the transfer gate 21 is connected to one of the vertical transmission lines 15 and the second terminal 25 is connected to one of the horizontal transmission lines 16. Connecting. Transfer gate 21
Is connected to a data terminal 29 via a select transistor 28 connected to a bit line 60. The gate of the selection transistor 28 is connected to a gate selection signal line 30. The data terminal 29 and the gate selection signal line 30 are connected to a buffer circuit and an address recorder as peripheral circuits, respectively.

Here, the first terminal 24 and the second terminal 25
Electrical connection or non-connection is determined by the state of the flip-flop 27 in which a pair of complementary outputs are connected to respective gates of the N-type pass transistor 22 and the P-type pass transistor 23. For example, the first data terminal 4
When 0 is high potential and the second data terminal 41 is low potential,
The transfer gate 21 is in a connected state.

Referring to FIG. 9, the state of the flip-flop 27 can be programmed by the following method.

For example, to program the bit line 60 to a high potential, when the gate selection signal line 30 is set to a high potential while the data terminal 29 is set to a high potential, the voltage of the data terminal 29 is transmitted to the flip-flop 27. The first data terminal 40 has a high potential and the second data terminal 41 has a low potential. As a result, the transfer gate 21 is connected.

FIG. 10 shows one transfer gate 21.
FIG. 3 is a circuit diagram showing a case where a plurality of flip-flops 27 are connected in parallel. Each flip-flop forms one memory cell by providing two select transistors 48, and here shows a case where nine memory cells are connected in parallel.

As shown in FIG. 10, a first data terminal 40 and a second data terminal 4 of each flip-flop 27 are provided.
Numerals 1 are connected in parallel to the gates of the N-type pass transistor 22 and the P-type pass transistor 23 via the selection transistor 48, respectively.

The selection of each memory cell (33-39) is performed by setting an arbitrary address selection line 50 connected to the gate of the selection transistor 48 of each memory cell (33-39) to a high potential, and setting the transfer gate 21 to the connection state. It is performed by becoming.

For example, to program the first data terminal 40 of the first memory cell 33 to a high potential, the third data terminal 42 is set to a high potential, and the fourth data terminal 43 is set to a low potential. When the selection line 50 (WL1) is set to a high potential, the voltage of the third data terminal 42 is transmitted to the flip-flop 27 of the first memory cell 33, and the first data terminal 40 is set to the high potential and the second data terminal 41 has a low potential.

Next, when the first data terminal 40 of the first memory cell 33 is kept at a high potential and the second data terminal 41 is kept at a low potential, the address selection line 50 (WL
When 1) is set to a high potential, the third data terminal 42 is set to a high potential, and the fourth data terminal 43 is set to a low potential, and the address selection line 50 (WL1) is set to a high potential. The gates of the P-type pass transistors 23 become high potential and low potential, respectively,
Is in the connected state.

As described above, by selecting any address from the address selection lines 50WL1 to WLn, the state of the corresponding flip-flop 27 can be transmitted to the transfer gate 21.

In this way, once the flip-flop 27
Is programmed, the state of the transfer gate 21 is maintained by the flip-flop 21. As described above, the flip-flop 27 holds the connection information of the intersection of the vertical transmission line 15 and the horizontal transmission line 16.

[0021]

As described above, according to the prior art, if the state of the flip-flop 27 is programmed, the state of the transfer gate 21 is maintained by the flip-flop 27. When the power supply is turned off, the connection information at the intersection of the vertical transmission line 15 and the horizontal transmission line 16 is lost.

Therefore, after the power is turned on again, the connection information at each intersection of the vertical transmission line 15 and the horizontal transmission line 16 must be transferred from outside the programmable logic circuit and reprogrammed. In general,
It is necessary to prepare a device other than the programmable logic circuit, for example, a read-only memory (ROM) or the like, and store the connection information therein.

Also, since the connection information at each intersection is maintained only by the flip-flop, the configuration (connection) of the entire logic circuit cannot be changed during the operation of the programmable logic circuit, and a series of operations is temporarily stopped. After that, it is necessary to newly transmit different connection information from the external device to each intersection, and reprogram the connection.

[0024]

In order to solve the above-mentioned problems, a programmable logic circuit according to the present invention comprises a vertical transmission line and a horizontal transmission line for transmitting a logic signal between a plurality of logic circuit blocks. A transfer gate is arranged at each intersection of the lines, and electrical connection or disconnection of each intersection is performed by the ON or OFF state of the transfer gate, and the ON or OFF state of the transfer gate is connected to each transfer gate. The voltage applied to the ferroelectric capacitors constituting each ferroelectric memory cell is determined by the output of the ferroelectric memory cell when a voltage is applied to the ferroelectric memory cell. After that, the polarization of the ferroelectric capacitor is in a range in which the polarization returns to the original deviation.

According to this configuration, even when the power is turned off, the connection information at each intersection can be retained. In the case where the output of the ferroelectric memory cell is obtained, the voltage applied to the ferroelectric capacitor is a range in which the polarization of the ferroelectric capacitor returns to the original deviation after removing the voltage. Therefore, since the connection information of the ferroelectric memory cell is not damaged by the output, non-destructive reading becomes possible.

According to a second aspect of the present invention, in the programmable logic circuit of the first aspect, the output of each ferroelectric memory cell is connected to each transfer gate via a flip-flop. It is a feature.

According to this configuration, since the state of the transfer gate is determined by the state of the flip-flop, the connection information of the ferroelectric memory cell can be stably maintained by the flip-flop.

According to a third aspect of the present invention, in the programmable logic circuit of the second aspect, the flip-flop is connected to a plurality of ferroelectric memory cells to which addresses are assigned, Is determined by the output of the ferroelectric memory cell whose address is specified.

According to this configuration, since the state of the flip-flop is determined by the output of the ferroelectric memory cell whose address is specified, the connection information can be changed by specifying the address.

According to a fourth aspect of the present invention, in the programmable logic circuit according to the first or second aspect, an output signal from the ferroelectric memory cell is input to a gate of a transistor, and It is characterized in that an amplified signal corresponding to the signal is output to a transfer gate.

According to this structure, the output from the ferroelectric memory cell is amplified and given to the flip-flop.

According to a fifth aspect of the present invention, in the programmable logic circuit according to the first, second or third aspect, the ferroelectric memory cell is constituted by a pair of ferroelectric capacitors. ,
Each of the two complementary inputs and outputs of the flip-flop is
The ferroelectric capacitor is connected to each of the pair of ferroelectric capacitors.

According to this structure, the output from the ferroelectric memory cell is amplified and given to the flip-flop.

According to a sixth aspect of the present invention, there is provided the programmable logic circuit according to the fifth aspect, wherein a pair of output signals from the ferroelectric memory cell are input to the gates of a pair of transistors, respectively. And two complementary inputs / outputs of the flip-flop are provided as a pair of outputs of an amplified signal corresponding to the signal of the gate.

According to this configuration, the state of the flip-flop can be more reliably determined.

A programmable logic circuit according to a seventh aspect of the present invention is the programmable logic circuit according to the first aspect, wherein the output of each ferroelectric memory cell is connected to each transfer gate via a sense amplifier. It is a feature.

According to this configuration, the state of the transfer gate is determined by the state of the sense amplifier.
The connection information of the ferroelectric memory cell can be stably maintained by the sense amplifier.

The programmable logic circuit according to claim 8 of the present invention is the programmable logic circuit according to claim 7, wherein a plurality of ferroelectric memory cells to which addresses are assigned are connected to the sense amplifier. Is determined by the output of the ferroelectric memory cell whose address is specified.

According to this configuration, since the state of the sense amplifier is determined by the output of the ferroelectric memory cell whose address is specified, the connection information can be changed by specifying the address.

According to a ninth aspect of the present invention, in the programmable logic circuit of the first or seventh aspect, an output signal from the ferroelectric memory cell is input to a gate of a transistor, and It is characterized in that an amplified signal output corresponding to the signal is supplied to a transfer gate.

According to this structure, the output from the ferroelectric memory cell is amplified and given to the sense amplifier.

According to a tenth aspect of the present invention, in the programmable logic circuit according to the first or seventh or eighth aspect, the ferroelectric memory cell comprises a pair of ferroelectric capacitors. , Each of the two complementary inputs and outputs of the sense amplifier
The ferroelectric capacitor is connected to each of the pair of ferroelectric capacitors.

According to this configuration, the output from the ferroelectric memory cell is amplified and given to the sense amplifier.

According to a eleventh aspect of the present invention, there is provided the programmable logic circuit according to the tenth aspect, wherein a pair of output signals from the ferroelectric memory cell are input to the gates of a pair of transistors, respectively. And two complementary inputs and outputs of the sense amplifier are provided as a pair of outputs of an amplified signal corresponding to the signal of the gate.

According to this configuration, it is possible to more reliably determine the state of the sense amplifier.

[0046]

Embodiments of the present invention will be described below.

(Embodiment 1) FIG. 1 is an equivalent circuit diagram showing a connection circuit at a certain intersection in a switch matrix of a programmable logic circuit according to Embodiment 1 of the present invention.

In FIG. 1, one electrode of a first ferroelectric capacitor 51 and one electrode of a second ferroelectric capacitor 52 are respectively written via a first selection transistor 58 and a second selection transistor 59. It is connected to the SET line and / SET line which are read lines. The first selection transistor 58 and the second selection transistor 5
9 is connected to the block selection line BS.

The other electrodes of the ferroelectric capacitors 51 and 52 are connected to the gates of a first read transistor 53 and a second read transistor 54, respectively. Are connected to the reset transistor 56. The first read transistor 53 and the first reset transistor 55 connected to the ferroelectric capacitor 51 are connected to the reset line RST, and the second read transistor 54 connected to the other ferroelectric capacitor 52. And the second reset transistor 5
6 is connected to the reset line / RST. Further, the first reset transistor 55 and the second reset transistor 56 are connected to the read selection line / RE. Also,
The first read transistor 53 and the second read transistor 54 are each a third select transistor 2
8, the bit line BL via the fourth selection transistor 29
60, connected to the bit line / BL61,
L60 and / BL61 are the third data terminals 42,
It is connected to the fourth data terminal 43. This data terminal 4
2, 43 are connected to a power supply for charging the bit line BL60 and the bit line / BL61 or a ground line for discharging. The bit lines BL60, / B
The third selection transistors 2 connected to L61 respectively
The eighth and fourth selection transistors 29 are connected to a gate selection signal line 30, and this gate selection signal line 30 is connected to an address recorder as a peripheral circuit.

The bit lines BL60 and / BL61 have an N-type pass transistor 22 and a P-type pass transistor 22 for connecting the flip-flop 27 that holds the potentials of the bit lines BL60 and / BL61 complementarily and the intersection 17 of the switch matrix. A transfer gate 21 in which the transistor 23 and the transistor 23 are connected in parallel to each other is connected. Transfer gate 2
The first terminal 24 and the second terminal 25 of FIG.
, The vertical transmission line 15 of the programmable logic circuit,
Connected to horizontal transmission line 16.

First, a method of writing complementary data to be written in the pair of ferroelectric capacitors 51 and 52 for holding the connection information of the transfer gate 21 in the equivalent circuit configured as described above will be described.

In order to write a different downward polarization to the ferroelectric capacitor 51 and an upward polarization to the ferroelectric capacitor 52, first, the BS line and the / RE line are set to a high potential and the first selection transistor 58 and the second , The first reset transistor 55 and the second reset transistor 56 are all turned on. Then, SET
The line and the / RST line may be set to a high potential, and the / SET line and the RST line may be set to a low potential. After that, when the BS line and the / RE line are set to a low potential, different downward polarizations are induced in the ferroelectric capacitor 51 and upwards in the ferroelectric capacitor 52, and the complementary data is held. Written.

To transmit the state held by the pair of ferroelectric capacitors to the connection information of the transfer gate 21, the third data terminal 42 and the fourth data terminal 43 are set to the power supply voltage (VDD) in advance. Therefore, the gate selection signal line 30 is set to a high potential, the first selection transistor 28 and the second selection transistor 29 are turned on, and the bit lines 60 and 61 are connected to VDD.
Charge until As soon as this charging is completed, the gate selection signal line 30 is set to a low potential to disconnect the bit lines 60 and 61 from the power supply. As a result, the complementary data written in the pair of ferroelectric capacitors is transferred to the transfer gate 21.
Is transmitted to the connection information.

Next, a method of reading connection information to be transmitted to the transfer gate 21 will be described.

Subsequently, when an appropriate same potential is applied to the SET line and the / SET line, the potential of the SET line is distributed and maintained by the ferroelectric capacitor 51 and the gate capacitance of the first read transistor 53. On the other hand, the potential of the / SET line is distributed and maintained by the ferroelectric capacitor 52 and the gate capacitance of the second read transistor 54.

At this time, the first ferroelectric capacitor 51
Is small due to the downward polarization, and that of the second ferroelectric capacitor 54 is large due to the upward polarization.
Therefore, the potential applied to the gate of the second read transistor 54 is higher than the potential applied to the gate of the first read transistor 53. Therefore, the potential applied to the second ferroelectric capacitor 52 is lower than the potential applied to the first ferroelectric capacitor 51. At this time, the potentials applied to the SET line and the / SET line are the coercive voltages of the respective ferroelectric capacitors, which are respectively distributed to the first ferroelectric capacitor 51 and the second ferroelectric capacitor 52. , Non-destructive readout without polarization inversion can be realized.

The principle on which the nondestructive read is possible will be specifically described below.

When the first ferroelectric capacitor 51 is small due to the downward polarization and the second ferroelectric capacitor 52 is large due to the upward polarization, the first ferroelectric capacitor 51 is induced. The electric charge applied to the second ferroelectric capacitor 52 has a relatively weak voltage dependence like a locus of 110 as shown in FIG. It shows a relatively strong voltage dependency like the locus of 111.

Therefore, when reading the data held in the memory cell by applying the voltage of VSET to each of the SET line and the / SET line, a unit area per unit area induced in the first ferroelectric capacitor 51 is read. Polarization charge Q
Is a load line 1 determined from the origin 100 of the QV plane in FIG.
21, the polarization charge Q per unit area induced in the second ferroelectric capacitor 52 is shown in FIG.
Moves from the origin 100 on the QV plane to the intersection 102 with the load line 121 determined by the capacitance of the gate of the second read transistor 54.

As a result, the first read transistor 5
The voltage VG2 applied to the gate of the second read transistor 54 is higher than the voltage VG1 applied to the gate of No.3. At this time, the voltages applied to the SET line and the / SET line are the voltages respectively distributed to the first ferroelectric capacitor 51 and the second ferroelectric capacitor 52, that is, VSET-VG1 and VSET-VG2. Are set so as not to exceed the coercive voltage of each ferroelectric capacitor. Then, by grounding the SET line and the / SET line, the load line determined by the capacitance of the gate of the first read transistor 53 in FIG. 2 returns to the position indicated by the broken line 120 in FIG. The polarization charge Q of the body capacitor 51 returns to the origin 100 from the point 101 on the QV plane, and the polarization charge Q of the second ferroelectric capacitor 52 becomes the second read transistor 54 in FIG.
The load line determined by the capacitance of the gate of FIG.
Since it is pulled back to the position represented by 03, it moves from point 102 to point 103 on the QV plane.

Subsequently, when the / RE line is set to a high potential and the gate of the second read transistor 54 is grounded, the polarization charge Q of the second ferroelectric capacitor 52 becomes Q in FIG.
The point 103 returns to the origin 100 from the point 103 on the -V plane. As a result of the above-described series of read operations, the polarization charge Q of the first ferroelectric capacitor 51 and the polarization charge Q of the second ferroelectric capacitor 52 both return to the origin 100 on the QV plane. However, non-destructive reading that is the same as before reading can be realized.

FIG. 4 shows the results of an experiment that has realized this nondestructive readout. FIG. 4 shows that different polarizations are written downward on the ferroelectric capacitor 51 and upward on the ferroelectric capacitor 52, the bit lines BL60 and / BL61 are respectively connected to a power supply voltage of 5 V via resistors, and the potentials repeatedly read out. Is read out, the voltages appearing on the bit lines BL60 and / BL61 are shown. At this time, the voltage VG2 applied to the gate of the second read transistor 54 is higher than the voltage VG1 applied to the gate of the first read transistor 53,
A difference occurs between the conductance of the first read transistor 53 and the conductance of the second read transistor 54, and the potential of the bit line / BL61 drops more rapidly than that of the bit line BL60. Therefore, in this experiment, bit line B
A voltage of about 3.6 V is applied to the bit line / BL6
It can be seen that a voltage of about 3.4 V is output to 1 every time, and that the values are kept almost constant even when the number of readings exceeds 10 ¹² . That is, even if the read operation is repeated, the magnitude of the polarization (data) held does not change, and it can be seen that nondestructive read can be realized.

As described above, the non-destructive read of data causes a difference in the conductance between the first read transistor 53 and the second read transistor 54, and the potential of the bit line 61 is rapidly increased as compared with that of the bit line 60. descend. As a result, in the configuration of FIG. 1, the bit line / BL61 is fixed at a low potential and the bit line BL60 is fixed at a high potential by the flip-flop 27. Therefore, the transfer gate 21 is in a connected state, and the first terminal 2
4 and the second terminal 25 conduct.

(Embodiment 2) FIG. 5 is an equivalent circuit diagram showing a connection circuit at a certain intersection in a switch matrix of a programmable logic circuit according to Embodiment 2 of the present invention.

The second embodiment is different from the first embodiment in that the ferroelectric capacitor for holding the connection information of the transfer gate 21 via the flip-flop 27 is a pair of ferroelectric capacitors in the first embodiment. Where it is composed of one memory cell having a dielectric capacitor,
The second embodiment is characterized in that a plurality of memory cells each having the pair of ferroelectric capacitors are connected in parallel.

That is, as shown in the equivalent circuit diagram of FIG. 5, a first ferroelectric capacitor 51 and a second ferroelectric capacitor 52 are paired with a selection transistor 48, respectively. Is configured. In this memory cell, a plurality of n memory cells from the first memory cell 33 to the n-th memory cell 39 are connected in parallel to the bit lines 60 and 61. One end of the pair of bit lines 60 and 61 is connected to the transfer gate 21.

Complementary data holding connection information of the transfer gate 21 is written in a pair of ferroelectric capacitors in each memory cell. These pieces of information can hold arbitrary connection information for each memory cell.

First, a method of writing complementary data written in a pair of ferroelectric capacitors 51 and 52 for holding the connection information of the transfer gate 21 in the equivalent circuit configured as described above will be described.

In order to write different downward and upward polarizations to the ferroelectric capacitor 51 and the ferroelectric capacitor 52, first, the address selection line 50 (WL1) corresponding to the first memory cell is set to a high potential. Next, BS line and / R
The E line is set to a high potential, and the two select transistors, the first select transistor 58 and the second select transistor 59, and the first reset transistor 55 and the second reset transistor 56 are all turned on. Then, SET
The line and the / RST line may be set to a high potential, and the / SET line and the RST line may be set to a low potential. After that, if the BS line and the / RE line are set to a low potential and the address selection line 50 (WL1) is set to a low potential, the ferroelectric capacitor 51 has different downward polarization and the ferroelectric capacitor 52 has different upward polarization. It is held in the induced state and complementary data is written.

Next, in order to transmit the state held by the pair of ferroelectric capacitors of the first memory cell 33 to the connection information of the transfer gate 21, the third data terminal 42 and the fourth data The terminal 43 is set to, for example, VDD, the gate selection signal line 30 is set to a high potential, the selection transistor 28 is turned on, and the bit lines 60 and 61 are charged to VDD. As soon as this charging is completed, the gate selection signal line 30 is set to a low potential and the bit lines 60 and 61 are set.
Disconnect from the power supply.

Next, a method of reading connection information to be transmitted to the transfer gate 21 will be described.

Subsequently, the address selection line 50 (WL1) corresponding to the first memory cell is set to a high potential to turn on the selection transistor 48, and then the same appropriate potential is applied to the SET line and / SET line. The potential of the SET line is determined by the ferroelectric capacitor 51 and the first read transistor 53.
And the gate capacitance is maintained. On the other hand, the potential of the / SET line is distributed and maintained by the ferroelectric capacitor 52 and the gate capacitance of the second read transistor 54. At this time, the capacitance of the first ferroelectric capacitor 51 is small due to the downward polarization, and that of the second ferroelectric capacitor 52 is large due to the upward polarization. Therefore, from the potential applied to the gate of the first read transistor 53,
The potential applied to the gate of the second read transistor 54 is higher. At this time, the SET line and / SET
The potentials applied to the lines are set so that the potentials respectively distributed to the first ferroelectric capacitor 51 and the second ferroelectric capacitor 52 do not exceed the coercive voltage of each ferroelectric capacitor. Thus, non-destructive reading without polarization inversion can be realized.

As a result, a difference occurs between the conductance of the first read transistor 53 and the conductance of the second read transistor 54, and the potential of the bit line 61 decreases more rapidly than that of the bit line 60. As a result, the bit line 61 is fixed at a low potential and the bit line 60 is fixed at a high potential by the flip-flop 27. Therefore, the transfer gate 21 is in the connected state, and the first terminal 24 and the second terminal
Terminal 25 conducts.

As described above, the connection information held by a desired memory cell is transmitted to the transfer gate 21 one after another only by performing the operation of designating the address.
The connection state can be changed. For example, after one logical operation is executed by one step through the switch matrix of interest, the memory cell is immediately switched to another address, and a different logical operation can be executed in the next logical operation. That is, it is not necessary to newly take in the connection information from outside the programmable logic circuit in order to change the connection information.

(Embodiment 3) FIG. 6 is an equivalent circuit diagram showing a connection circuit at a certain intersection in a switch matrix of a programmable logic circuit according to Embodiment 3 of the present invention.

The third embodiment is different from the second embodiment in that the ferroelectric capacitor for holding the connection information of the transfer gate 21 is different from the memory having the pair of ferroelectric capacitors in the second embodiment. Embodiment 3 When a plurality of cells are connected in parallel, the third embodiment
In the second embodiment, a plurality of memory cells each having one ferroelectric capacitor are connected in parallel, and the ferroelectric capacitor for holding the connection information of the transfer gate 21 is a flip-flop in the second embodiment. 27, the third embodiment
Is that a reference cell is used.

That is, as shown in the equivalent circuit diagram of FIG. 6, the first ferroelectric capacitor 51 includes a selection transistor 48 to form a set of memory cells.
In this memory cell, a plurality of n memory cells from the first memory cell 33 to the n-th memory cell 39 are connected to the bit line 60 in parallel. The bit line 60 is connected to the sense amplifier 70
The other input of the sense amplifier 70 is connected to a REF power supply that generates a reference voltage that is intermediate between complementary potentials corresponding to connection information output from the selected memory cell to the bit line 60. Connected.

The bit line 60 connected to the sense amplifier 70 is connected to the gate of the N-type pass transistor of the transfer gate 21, and the gate of the P-type pass transistor 22, which is the other end of the transfer gate 21,
Connected to sense amplifier 70. The first terminal 2 of the transfer gate 21 in which the N-type pass transistor 22 and the P-type pass transistor 23 are connected in parallel with each other.
4 is connected to one of the vertical transmission lines 15 and the second terminal 25 is connected to one of the horizontal transmission lines 16.

First, a method of writing data to be written in the ferroelectric capacitor 51 holding the connection information of the transfer gate 21 in the equivalent circuit configured as described above will be described.

Each memory cell comprises a first ferroelectric capacitor 51 and a selection transistor 48, and holds arbitrary connection information. For example, in order to induce downward polarization in the ferroelectric capacitor 51 in the first memory cell 33, first, the address selection line 50 (WL1) corresponding to the first memory cell is set to a high potential, and then the BS line is set. When/
The RE line is set to a high potential to turn on both the selection transistor 58 and the first reset transistor 55. continue,
What is necessary is just to make the SET line high potential and the RST line low potential. After that, when the BS line and the / RE line are set to a low potential and the address selection line 50 (WL1) is set to a low potential, the ferroelectric capacitor 51 is held in a state where downward polarization is induced.

Next, in order to transmit the state held by the first ferroelectric capacitor 51 of the first memory cell 33 to the connection information of the transfer gate 21, the third data terminal 42 is previously connected to, for example, VDD. Then, the gate selection signal line 30 is set to a high potential, the selection transistor 28 is turned on, and the bit line 60 is charged to VDD. As soon as the charging is completed, the gate selection signal line 30 is set to a low potential to disconnect the bit line 60 from the power supply.

Next, a method of reading the connection information transmitted to the transfer gate 21 will be described.

The address select line 50 (WL1) corresponding to the first memory cell is set to a high potential to select transistor 48.
Is turned on, and then the same potential is applied to the SET line, the potential of the SET line becomes equal to the ferroelectric capacitor 51 and the first potential.
And the gate capacitance of the read transistor 53. At this time, the potential applied to the gate of the first read transistor 53 takes a certain value depending on the direction of polarization of the first ferroelectric capacitor 51. By setting the potential applied to the SET line so that the potential distributed to the first ferroelectric capacitor 51 does not exceed the coercive voltage of the ferroelectric capacitor, non-destructive reading without polarization inversion can be realized. .

As a result, a difference occurs in the conductance of the first read transistor 53 depending on the polarization, and the potential of the bit line 60 starts to decrease.

On the other hand, the other input of the sense amplifier 70 is connected to a reference voltage having a bit line 61 and a REF line. This reference voltage is lower than the potential applied to the bit line 60 when the polarization of the memory cell is downward, and higher than the potential applied to the bit line 60 when the polarization of the memory cell is upward. Therefore, at a timing after the potential of the bit line 60 starts to decrease, the sense amplifier 70
Is activated, the potentials of the bit line 60 and the bit line 61 are compared, and differential amplification is performed.

As a result, when the polarization of the memory cell is downward, the bit line 60 is fixed at a high potential, and when the polarization of the memory cell is upward, the bit line 60 is fixed at a low potential. The potential of the bit line 61 is in a complementary state. Therefore,
For example, when the polarization of the first ferroelectric capacitor 51 of the selected memory cell is downward, the transfer gate 21 is connected, and the first terminal 24 and the second terminal 25 conduct.

As described above, the connection information held by the desired memory cell is transmitted to the transfer gate 21 one after another only by performing the operation of designating the address.
The connection state can be changed. For example, after one logical operation is executed by one step through the switch matrix of interest, the memory cell is immediately switched to another address, and a different logical operation can be executed in the next logical operation. That is, it is not necessary to newly take in the connection information from outside the programmable logic circuit in order to change the connection information.

In the first and second embodiments,
Although flip-flops are used to determine the potential of a pair of bit lines, they may be replaced with sense amplifiers as described in the third embodiment.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing a connection circuit at a certain intersection in a switch matrix of a programmable logic circuit according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing voltage dependence of electric charge induced in the first ferroelectric capacitor 51 when the first ferroelectric capacitor 51 is polarized downward.

FIG. 3 is a diagram showing the voltage dependence of the charge induced in the second ferroelectric capacitor when the second ferroelectric capacitor is polarized upward;

FIG. 4 is a diagram showing the number-of-readings dependency of a potential read to bit lines BL60 and / BL61.

FIG. 5 is an equivalent circuit diagram showing a connection circuit at a certain intersection in a switch matrix of the programmable logic circuit according to the second embodiment of the present invention;

FIG. 6 is an equivalent circuit diagram showing a connection circuit at a certain intersection in a switch matrix of the programmable logic circuit according to the third embodiment of the present invention;

FIG. 7 is a block diagram of a programmable logic circuit.

FIG. 8 is a diagram showing a main part of a switch matrix at an intersection of a vertical transmission line and a horizontal transmission line of a programmable logic circuit;

FIG. 9 is an equivalent circuit diagram showing a connection circuit at a certain intersection in a switch matrix of the programmable logic circuit;

FIG. 10 is an equivalent circuit diagram showing a connection circuit at a certain intersection in a switch matrix of the programmable logic circuit;

[Explanation of symbols]

 Reference Signs List 11 switch matrix 12 logic block 21 transfer gate 27 flip-flop 28 selection transistor 29 data terminal 30 gate selection signal line 33 first memory cell 39 nth memory cell 48 selection transistor 50 address selection line (WL1 to WLn) 51 first Ferroelectric capacitor 52 second ferroelectric capacitor 53 first read transistor 54 second read transistor 55 first reset transistor 56 second reset transistor 58 first select transistor 59 second select transistor 60 Bit line (BL) 61 Bit line (/ BL) 70 Sense amplifier SET Set line RST Reset line BS Block select line / RE Read select line WL1 to WLn Address select line

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Takayoshi Yamada 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. CA07 CA15 CA20 DA04

Claims (11)

[Claims] 1. A transfer gate is disposed at each intersection of a vertical transmission line and a horizontal transmission line for transmitting a logic signal between a plurality of logic circuit blocks, and electrical connection or disconnection of each intersection is determined by the transfer gate. The ON or OFF state of the transfer gate is determined by the output of the ferroelectric memory cell when a voltage is applied to the ferroelectric memory cell connected to each transfer gate. The voltage applied to the ferroelectric capacitors constituting each of the ferroelectric memory cells is within a range in which the polarization of the ferroelectric capacitors returns to the original deviation after the removal thereof. Programmable logic circuit. 2. The programmable logic circuit according to claim 1, wherein the output of each ferroelectric memory cell is connected to each transfer gate via a flip-flop. 3. A plurality of ferroelectric memory cells to which an address is assigned are connected to the flip-flop, and a state of the flip-flop is determined by an output of the ferroelectric memory cell to which an address is designated. The programmable logic circuit according to claim 1, wherein: 4. A programmable logic circuit according to claim 1, wherein an output signal from the ferroelectric memory cell is input to a gate of the transistor, and an amplified signal corresponding to the signal of the gate is output to a transfer gate. . 5. The ferroelectric memory cell includes a pair of ferroelectric capacitors, and two complementary inputs and outputs of a flip-flop are connected to the pair of ferroelectric capacitors, respectively. The programmable logic circuit according to claim 1, 2, or 3, wherein 6. A pair of output signals from a ferroelectric memory cell are input to the gates of a pair of transistors, respectively.
6. The programmable logic circuit according to claim 5, wherein an amplified signal corresponding to the signal of the pair of gates is provided as a pair of outputs to two complementary inputs and outputs of the flip-flop. 7. The programmable logic circuit according to claim 1, wherein an output of each ferroelectric memory cell is connected to each transfer gate via a sense amplifier. 8. A plurality of ferroelectric memory cells to which an address is assigned are connected to the flip-flop, and a state of the flip-flop is determined by an output of the ferroelectric memory cell to which an address is specified. The programmable logic circuit according to claim 7, wherein: 9. The programmable logic circuit according to claim 7, wherein an output signal from the ferroelectric memory cell is input to a gate of the transistor, and an amplified signal output corresponding to the signal of the gate is supplied to a transfer gate. 10. The ferroelectric memory cell includes a pair of ferroelectric capacitors, and each of two complementary inputs / outputs of a sense amplifier is connected to the pair of ferroelectric capacitors. 9. The programmable logic circuit according to claim 1, wherein the programmable logic circuit comprises: 11. A pair of output signals from a ferroelectric memory cell are respectively input to gates of a pair of transistors, and amplified signals corresponding to the signals of the pair of gates are output as a pair of outputs to provide two complementary signals of a sense amplifier. 11. The programmable logic circuit according to claim 10, which is applied to an input / output.