JP2002353083A - Method of manufacturing semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To materialize the rise of the manufacture efficiency of an LSI or the reduction of manufacture cost, by integrating and utilizing the information about both design division and a manufacture division. SOLUTION: A computer unit (60) receives the input of the element property information of a semiconductor element from manufacture divisions (10-12) and also receives the input of design information of a semiconductor integrated circuit from manufacturing divisions (13-16) via a network, and creates the response information requested by a request source concerned, based on the above input information, in response to the request from the supply source of the above design information, and returns the created response information to the above request source. For example, the response information is the forecast yield information, at the time of having supposed that the semiconductor integrated circuit is constituted, making use of the element specified by the element property information. Hereby, the design division can be previously informed of the yield of products at the time of having placed an order with the manufacture division with products, and it becomes possible to properly select the manufacture division. The enhancement of the manufacture efficiency of LSI or the reduction of manufacture cost can be materialized by using the properly selected manufacture division.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit (LSI), and more particularly, to integrating information (knowledge) held by a design department for designing a semiconductor integrated circuit and a manufacturing department for manufacturing a semiconductor integrated circuit. And technology used for manufacturing LSIs.

[0002]

2. Description of the Related Art The present inventor relates to the manufacture of semiconductor integrated circuits.
The technique described in the publication No. 0-106695 was proposed. The former proposes a method of generating intermediate data from measured device characteristics (such as IV characteristics) and extracting model parameters for circuit simulation from the data. The latter proposes a method of extracting model parameters for circuit simulation from the measured saturation current and threshold value of the MOS transistor.

[0003] Further, regarding the manufacture of a semiconductor integrated circuit, a technique for manufacturing a semiconductor integrated circuit which converts a feature amount corresponding to a defect into a parameter of a manufacturing machine and feeds it back (Japanese Patent Laid-Open No.
No. 2019946), the measurement results are collected and analyzed, and in accordance with the results, the cause equipment is specified and the new condition is calculated (JP-A-6-333791).
No.) have been proposed.

[0004]

SUMMARY OF THE INVENTION The present inventor has further advanced the point of view of individual technologies relating to the manufacture of semiconductor integrated circuits,
The knowledge management technology that integrates the knowledge held by each of the design department and the manufacturing department of I, generates useful information for both, and applies the information to the manufacture of LSI.

First, in general, manufacturing a semiconductor integrated circuit (LSI) requires a large-scale production facility, and it is not uncommon that the manufacturing department is divided into units such as a production factory for each LSI type or process. In addition, the LSI design department
There is a tendency for details to be reduced according to the type or process of SI. Moreover, due to economic or human factors,
The design department and the manufacturing department are not always adjacent,
They may be scattered in geographically remote locations. Therefore, it is advisable to use a closed network such as an intranet for such a knowledge management technology.

As a specific necessity of such knowledge management, the present inventor has determined, for example, which manufacturing department (manufacturing department) is optimal to produce an LSI under development by a design department. It has been found that it is convenient to make a judgment if it is possible to obtain information necessary for judging which manufacturing section of a manufacturing line to make a manufacturing request for in terms of cost and time. As described above, it is expected that there are many cases where it is advantageous for the other to know one piece of information. In addition, it is sometimes better for the design department to consider the relationship with device characteristics in order to reduce costs and achieve QTAT (Quick Turn Around Time) in product development. It should be easily or immediately available. In addition, if the design department can easily or immediately obtain the device characteristics necessary for determining device parameters for circuit simulation used in circuit design from the manufacturing department, if a device from a manufacturing factory that is a candidate for manufacturing request is used, Circuit simulation becomes possible. In some cases, it is better for manufacturing plants to consider measures to increase the yield in consideration of the relationship with the circuit characteristics.
It is preferable that the information of the benchmark circuit can be obtained in advance.

Further, the present inventor has noticed that there are cases where it is not sufficient for the manufacturing department and the design department to obtain one piece of information from each other simply as it is. That is, it takes time and cost to process or convert the obtained information, and the necessary information cannot be obtained in a timely manner.

An object of the present invention is to provide a semiconductor which can organically integrate information of an LSI design department and a manufacturing department, and use the information to improve manufacturing efficiency, reduce manufacturing cost, and improve performance. An object of the present invention is to provide a method for manufacturing an integrated circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[1] (Ln, Dg → KMS → Ln) First
In a method for manufacturing an LSI according to an aspect, a first computer device (KMS) such as a knowledge management server is LS
I. Information is input from the second computer device (Ln) of the manufacturing department and the third computer device (Dg) of the LSI design department, and response information generated based on the information is returned to the second computer device (Ln). Used for the manufacture of

In short, in the LSI manufacturing method, the first computer device (KMS) inputs device characteristic information of a semiconductor device from a second computer device (Ln) of a manufacturing section having a semiconductor integrated circuit manufacturing facility via a network. And a first computer unit (Dg) of a design department for designing a semiconductor integrated circuit via a network.
A process in which the computer device inputs design information of the semiconductor integrated circuit; a process in which the second computer device requests a service from the first computer device; Generating response information based on the input element characteristic information and design information, and returning the generated response information to the requesting second computer device; and a second computer device receiving the response information. Manufacturing a semiconductor integrated circuit using manufacturing equipment corresponding to the above.

In a more specific aspect, in the generation of the response information, the first computer device responds to the service request and transmits the response information required by the request source to the semiconductor integrated circuit using the device characteristic information. Generated on the assumption that a specified semiconductor element is used.

Since an LSI can be manufactured by reflecting the content obtained from such response information, it is possible to expect an improvement in LSI manufacturing efficiency, a reduction in LSI manufacturing cost, and an improvement in LSI performance.

(Wafer unit price) The response information is calculated by the predicted yield information assuming that the semiconductor integrated circuit is configured using the element specified by the element characteristic information and the design information supply source of the semiconductor integrated circuit. Wafer unit price information generated based on the chip unit price information. As a result, the manufacturing department can know the wafer unit price that matches the balance of the chip unit price desired by the design department. Therefore, the process for manufacturing the semiconductor integrated circuit may be a process that satisfies the wafer unit price specified by the wafer unit price information.

(Lot input timing) The response information includes time-series element characteristic information (device variation data, wiring variation data, foreign matter data) of the semiconductor element, and the necessity of the semiconductor integrated circuit given from the supply source of the design information. It may include information on a lot delivery time and a lot delivery time which is formed based on the quantity and the manufacturing delivery time and which satisfies the delivery time and the number of the semiconductor integrated circuits with a small number of wafers. As a result, the manufacturing department can manufacture the required number of wafers with a small number of wafers, which contributes to cost reduction. Therefore, it is preferable that the process for manufacturing the semiconductor integrated circuit is a process that satisfies the lot input timing specified by the information about the lot input timing.

Since an LSI is manufactured using an appropriate manufacturing section in terms of the unit cost of a wafer and the timing of lot introduction, the LSI
It is possible to realize an improvement in the production efficiency and a reduction in the production cost.

[2] (Ln, Dg → KMS → Dg) Second
In the method for manufacturing an LSI according to the aspect, the first computer device (KMS) includes a second computer device (Ln) in an LSI manufacturing section and a third computer device (D) in an LSI design section.
g), the response information generated based on the information is returned to the third computer device (Dg), and the
Used for the manufacture of

In short, an LSI manufacturing method includes a process in which a first computer device inputs element characteristic information of a semiconductor device from a second computer device in a manufacturing section having a semiconductor integrated circuit manufacturing facility via a network; A process in which a first computer device inputs design information of a semiconductor integrated circuit from a third computer device of a design department for designing a circuit via a network, a process of requesting a service from the third computer device to the first computer device; The first computer device generates response information required by the requestor in response to the service request based on the input element characteristic information and design information, and generates the generated response information by the third requester of the requestor. Processing to be returned to the computer device, and manufacture specified by the third computer device to which the response information has been returned It is capable of executing a process of manufacturing a semiconductor integrated circuit using Bei.

In a more specific aspect, in the generation of the response information, the response information required by the request source in response to the service request is stored in the semiconductor integrated circuit by the semiconductor characteristic specified by the element characteristic information. The generated response information is generated on the assumption that an element is used, and the generated response information is returned to the third computer device that has made the request.

(Product Yield) The response information includes predicted yield information when it is assumed that the semiconductor integrated circuit is configured using the element specified by the element characteristic information input from the second computer device. Good. As a result, the design department can know in advance the product yield when ordering the product to each manufacturing department, and can appropriately select the manufacturing department. Therefore, the third computer device may specify a manufacturing facility whose yield specified by the predicted yield information is relatively high. With this, LSI
Can improve the production efficiency.

(Chip Unit Price) The response information may include chip unit price information generated based on the predicted yield information and desired wafer unit price information provided from the second computer device. As a result, the design department can confirm the characteristics or performance when requesting each manufacturing department to manufacture a product by performing circuit simulation using device parameters, and it is possible to manufacture products that meet performance specifications It is possible to select a suitable manufacturing department. Therefore, the third computer device may specify a manufacturing facility whose unit price specified by the chip unit price is relatively low. This makes it possible to reduce the manufacturing cost of the LSI.

(Yield Improving Measure: FIG. 6) The response information indicates a defect due to a device structure, a process condition, and a foreign substance with respect to a semiconductor integrated circuit for reducing variation in circuit characteristics of a benchmark circuit provided from the third computer. It may include information about the layout structure to reduce. Thus, the design department can review the layout design so that the yield can be improved with reference to the improved layout. Therefore, the third
The computer device may designate a manufacturing facility for manufacturing a semiconductor integrated circuit having a layout modified based on the information on the layout structure. This can contribute to an improvement in the performance of the LSI.

(Line arranging: FIG. 8) The response information includes chip unit price information obtained from predicted yield information of the semiconductor integrated circuit and desired wafer unit price information given from the third computer unit, and the second computer. The information may include information on the congestion state of the manufacturing equipment and the timing of completion of the required wafer obtained based on the throughput of the manufacturing equipment, which is given from the apparatus together with the element characteristic information of the semiconductor element. As a result, the design department can select a manufacturing department that can manufacture a product at an appropriate price and with a desired delivery date. Therefore, the third computer device may designate a manufacturing facility which is completed earlier at a relatively lower cost than the information on the chip unit price and the completion time. As a result, it is possible to improve the manufacturing efficiency of the LSI and reduce the manufacturing cost of the LSI.

[3] (Ln → KMS → Dg) The method of manufacturing an LSI according to the third embodiment is based on the first computer device (KM
S) inputs information from the second computer device (Ln) in the manufacturing department, and returns response information (device parameters, pre-silicon device parameters) generated based on the information to the third computer device (Dg) in the design department. , L
Used for manufacturing SI.

In short, the LSI manufacturing method includes a process in which a first computer device inputs element characteristic information of a semiconductor device from a second computer device in a manufacturing section having a semiconductor integrated circuit manufacturing facility via a network; A process of requesting a service from the third computer device of the design department for designing the circuit to the first computer device, and the first computer device responding to the service request by changing the element characteristic specified by the input element characteristic information. A process of generating device parameters for simulation and returning the generated device parameters to the third computer to the request source; a process of the third computer performing a circuit simulation using the device parameters;
Manufacturing a semiconductor integrated circuit using manufacturing equipment designated by the computer device. As a result, the design department can confirm the characteristics or performance at the time of requesting the manufacturing department to manufacture the product by performing a circuit simulation using the device parameters, and can appropriately manufacture the product that satisfies the performance specifications. It becomes possible to select a manufacturing department. As a result, it is possible to contribute to an improvement in the performance of the LSI and an improvement in the manufacturing efficiency of the LSI.

Also, in the method of manufacturing an LSI, the first computer device may use a network from a second computer device in a manufacturing section having a semiconductor integrated circuit manufacturing facility to transmit device characteristic information of a semiconductor device and device conditions of an unknown semiconductor device. A process of inputting a request, a process of requesting a service from a third computer device of a design department for designing a semiconductor integrated circuit to the first computer device, and the device characteristic information input by the first computer device in response to the service request. And generating a pre-silicon device parameter for simulating the device characteristics of the unknown semiconductor device based on the device condition, and returning the generated pre-silicon device parameter to the request source; and Process of performing circuit simulation using device parameters and Including a process of fabricating a semiconductor integrated circuit by using the manufacturing equipment third computer system it has been designated. This allows the design department to perform circuit simulations using device parameters before the manufacturing department develops the device, and to check the performance of the characteristics at the early stage when the manufacturing department receives an order for product manufacturing. It is possible to appropriately select a manufacturing department capable of manufacturing a product satisfying the performance specifications. With this, LSI
, And the manufacturing efficiency of the LSI.

[4] (Ln → KMS → Ln) The method of manufacturing an LSI according to the fourth embodiment is based on the first computer device (KM
S) is the second computer device (Ln) of the LSI manufacturing department
And the response information generated based on the information is returned to the second computer device (Ln).
Used for the manufacture of

In short, the LSI manufacturing method is based on a method in which a first computer device is connected via a network from a second computer device in a manufacturing section having a semiconductor integrated circuit manufacturing facility to a device using a benchmark circuit using the device characteristic information of a semiconductor device. A process of inputting information; a process of requesting a service from the second computer device to the first computer device; and a process in which the first computer device responds to the service request by using the element specified by the element characteristic information. A process of generating response information obtained assuming that a benchmark circuit is configured, and returning the generated response information to the request source;
A process of manufacturing a semiconductor integrated circuit using manufacturing equipment corresponding to the second computer device to which the response information has been returned;
including.

(Yield Improvement Measure: FIG. 5) The response information may include information on a process condition and a device structure for a semiconductor element for reducing a variation in circuit characteristics of the benchmark circuit. As a result, the manufacturing department can increase yield and reduce defective products, which leads to an increase in sales. Therefore, the process of manufacturing the semiconductor integrated circuit may be performed using a manufacturing facility reflecting the information on the process conditions and the device structure.

Since an LSI can be manufactured using the manufacturing section in which the yield improvement measures and the like are implemented, the LS
It is possible to improve the manufacturing efficiency of I and reduce the manufacturing cost.

[5] Next, an LSI manufacturing method is roughly classified for each type of response information.

(Estimated Yield Information) The method for manufacturing an LSI according to the present invention uses a first computer device in a manufacturing section having facilities for manufacturing semiconductor integrated circuits via a network.
A process in which a computer device inputs element characteristic information of a semiconductor element, a process in which a first computer device inputs design information of a semiconductor integrated circuit via a network from a third computer device of a design department for designing a semiconductor integrated circuit, A process in which the first computer device generates predicted yield information of the product based on the input device characteristic information and design information, assuming that the product required by the design department is manufactured by the manufacturing department. A process in which the third computer device specifies a manufacturing facility having a relatively high yield specified by the predicted yield information; and a process in which a manufacturing department manufactures a semiconductor integrated circuit using the specified manufacturing facility. ,including.

(Wafer unit price information) The first computer unit may further generate wafer unit price information based on the predicted yield information and chip unit price information provided from a third computer unit of the design department. . Thus, the process of manufacturing the semiconductor integrated circuit may satisfy the unit cost of the wafer specified by the unit cost information.

(Chip Unit Price) The first computer unit may further generate chip unit price information based on the predicted yield information and wafer unit price information presented from the second computer unit of the manufacturing section. Thereby, the process of specifying the manufacturing equipment specifies the manufacturing equipment in which the yield specified by the predicted yield information is relatively high and the chip unit price specified by the chip unit price information is relatively low. Any processing may be used.

(Line arranging) The process may further include a process of estimating a completion time of a required wafer based on a manufacturing equipment congestion state and a manufacturing equipment throughput inputted from the second computer device of the manufacturing section. Accordingly, in the process of specifying the manufacturing equipment, the yield specified by the predicted yield information is relatively high, the chip unit price specified by the chip unit price information is relatively low, and the delivery date is satisfied. What is necessary is just to specify the manufacturing equipment.

(Lot input timing) Time-series element characteristic information (device variation data, wiring variation data,
Based on the foreign matter data), the required quantity of the semiconductor integrated circuit and the delivery date of the semiconductor integrated circuit input from the third computer device of the design department, information on the delivery date of the semiconductor integrated circuit and the lot input timing that satisfies the small number of wafers is generated. Processing may further be included. Accordingly, it is optimal if the process of manufacturing the semiconductor integrated circuit is performed according to the lot input timing indicated by the information on the lot input timing.

(Device Parameter) L of Still Another Embodiment
An SI manufacturing method includes a process in which a first computer device inputs element characteristic information of a semiconductor element via a network from a second computer device in a manufacturing section having semiconductor integrated circuit manufacturing equipment, and the input device characteristic information A first computer device for generating device parameters necessary for circuit simulation for performing circuit design based on the first computer device; and a third computer device of a design department for designing a semiconductor integrated circuit performs circuit simulation using the device parameters. And a process of manufacturing a semiconductor integrated circuit using manufacturing equipment designated by the third computer device.

(Pre-Silicon Device Parameter) In still another embodiment, a method of manufacturing an LSI is described in which a second computer device in a manufacturing section having a semiconductor integrated circuit manufacturing facility has a first computer device.
A process in which a computer device inputs element characteristic information of an existing semiconductor element and element conditions of an unknown semiconductor element via a network, and simulates a blocking characteristic of the unknown semiconductor element based on the input element characteristic information and the element conditions input A first computer device for generating pre-silicon device parameters for performing the operation, a third computer device of a design department for designing a semiconductor integrated circuit performing a circuit simulation using the pre-silicon device parameters, and a third computer. Manufacturing a semiconductor integrated circuit using manufacturing equipment designated by the apparatus.

(Yield Improvement Measure: FIG. 6) LS of Still Another Embodiment
The method of manufacturing I includes a process of inputting element characteristic information of a semiconductor element via a network from a second computer device of a manufacturing section having a semiconductor integrated circuit manufacturing facility, and a third computer of a design section for designing a semiconductor integrated circuit. A first computer device inputs design information of a semiconductor integrated circuit from a device via a network, and the first computer device executes a benchmark circuit included in the design information based on the input device characteristic information and design information. Generating the improvement measure information on the device structure and the process conditions for reducing the variation in the circuit characteristics and the layout structure for reducing the defect due to the foreign matter; A procedure for designating a manufacturing facility for manufacturing a semiconductor integrated circuit having a modified layout. Includes a process of manufacturing a semiconductor integrated circuit with the specified manufacturing equipment.

(Yield Improvement Measure: FIG. 5) LS of Still Another Embodiment
In the method of manufacturing I, a first computer device inputs, via a network, a second computer device of a manufacturing section having a semiconductor integrated circuit manufacturing facility, the device characteristic information of a semiconductor element and benchmark circuit information using the semiconductor element. Based on the input device characteristic information and the benchmark circuit information,
In response to a request from a computer device, a process of generating improvement information on a process condition and a device structure for a semiconductor element for reducing a variation in circuit characteristics of the benchmark circuit; A process of providing improvement measure information; and a process of manufacturing a semiconductor integrated circuit by reflecting a process condition and a device structure according to the improvement measure information in a manufacturing facility corresponding to the second computer apparatus to which the improvement measure information is provided. Including.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS << System Configuration >> FIG. 1 illustrates a design / manufacturing system for implementing an LSI manufacturing method according to the present invention. The design / manufacturing system refers to an organization such as a semiconductor integrated circuit division belonging to one semiconductor integrated circuit maker or one company, and includes a plurality of representative manufacturing departments (Fb) 10, 11, and 12. And several design departments (F
l) It has 13, 14, 15, and 16.

The manufacturing departments 10 to 12 mean a manufacturing department of a manufacturing factory for manufacturing a semiconductor integrated circuit (LSI) incorporated in the organization, and include an LSI manufacturing facility for an LSI product or a prosense unit. The manufacturing units 10 to 12 receive design data such as circuit design data or layout pattern data of an LSI to be manufactured, and
I is manufactured. Although an illustration of an LSI manufacturing process is omitted, the LSI is manufactured through, for example, a known wafer processing step, a wafer inspection step, an aging step, and the like. An LSI manufacturing facility is a set of manufacturing equipments that are organically linked to each other to realize an LSI manufacturing process, and the components thereof have relativity that varies depending on the type of product to be manufactured. According to FIG. 1, each of the manufacturing sections 10 to 12 is an LSI manufacturing line 2.
0 to 22, measuring devices 30 to 32, and line data servers 40 to 42. Here, the production lines 20 to
Although not particularly limited, 22 is positioned as a set of manufacturing equipment for performing a wafer process. The measuring device 30-
32 is the LS manufactured in the corresponding manufacturing line 20-22
Devices included in I (eg MOS transistors)
Means for measuring the characteristics of The line data servers 30 to 32 implement a second computer device that holds and manages device characteristics and the like measured by the measuring devices 30 to 32 as line data.

The design departments 13 to 16 refer to design departments of LSIs incorporated in the organization. The design departments 13 to 16 have design data servers 50 to 53 for storing and managing LSI data designed in the organization. The design data servers 50 to 53 implement a third computer device.

The line data servers 40 to 42 and the design data servers 50 to 53 are connected via a network 18 such as an intranet.
0 is connected. This knowledge management server (KMS) 60 implements a first computer device.

The knowledge management server 60 includes:
From the line data servers 40 to 42 to the manufacturing departments 10 to 12
And the information of the LSI chips to be designed by the design departments 13 to 16 are obtained from the design data servers 50 to 53. Each of the servers 40 to
42, 50 to 53, and 60 are realized by a computer device such as a personal computer or an engineering workstation having an Internet connection function, an information processing function, and an information storage function.

The knowledge management server 60 includes:
It manages information obtained from the manufacturing departments 10 to 12 and the design departments 13 to 16, integrates information from both sides to generate or process information that is effective for both sides, and manufactures and processes the generated information and processed information. Departments 10 to 12 and Design Departments 13 to
The service provided in response to the request from P.16 is performed.

This service is provided by the manufacturing departments 10 to 12
And one of the design departments 13 to 16 processing and providing one of the information to the other in an effective form.
And integrating information obtained from both the design departments 13 to 16 and generating and providing effective information to the other in consideration of one situation. For example, in FIG. 1, the knowledge management server 60 performs a process of providing product yield information SV.
1. Providing process SV2 for providing a proper wafer and chip unit price, providing process SV3 for providing device parameters for circuit design, providing process SV4 for providing pre-silicon device parameters for circuit design, providing process SV5 for providing a measure for improving line yield, SV6 for providing a line, And lot input timing data provision processing SV
7 is performed.

The process SV1 for providing product yield information includes device information obtained from the line data servers 40-43 of the manufacturing departments 10-12 and design data obtained from the design data servers 50-53 of the design departments 13-16. From the above, the products required by the design departments 13 to 16 are supplied to the manufacturing departments 10 to 12.
This is a process of generating product yield information when it is assumed that the product is manufactured in the above-described manner and providing the same to service request sources in the design departments 13 to 16 (design data servers 50 to 53).

Proper wafer and chip unit price providing process SV2
Is a process for generating and providing information on a wafer price or a chip price when the manufacturing departments 10 to 12 manufacture an LSI.

The process SV3 for providing device parameters for circuit design is performed by generating device parameters for circuit simulation required by the design departments 13 to 16 for circuit design based on the data of the line data servers 40 to 42. This processing is provided to service request sources in the departments 13 to 16 (data servers 50 to 53).

The provision process SV4 of the pre-silicon device parameters for circuit design is performed by the line data servers 40 to 42.
From the data of the design departments 13 to 16 (design data servers 50 to 53). This is the process provided to the service requester.

The process SV5 for providing a line yield improvement measure is a process for generating and providing a device improvement measure for increasing the product yield required by the design departments 13 to 16.

The line recruitment process SV6 is performed by the design department 13 to
The manufacturing departments 10 to 12 or the manufacturing departments 10 that satisfy the required delivery date conditions for the processes and products required by 16
12 lines are searched, and the design data servers 50 to 53 are searched.
This is a process to be provided to the service request source.

Provision processing of lot input timing data SV7
Are line data servers 40-4 of the manufacturing departments 10-12
2 provides time-series device variation data, wiring variation data, foreign matter data, etc., and the design departments 13 to 16
From the required number of products and the delivery date, data relating to the lot delivery time for satisfying the delivery date and the number of the products with a small number of wafers is generated. This is the process provided to the service requester.

The knowledge management server 60 includes:
A service is provided in which the technical knowledge of the LSI manufacturing departments 10 to 12 and the design departments 13 to 16 are integrated to generate or process effective information for both. When the manufacturing departments 10 to 12 and the design departments 13 to 16 become able to use such a knowledge management server 60, the design departments 13 to 16 request any one of the manufacturing departments 10 to 12 to manufacture a product in terms of cost. Also, it is possible to judge whether it is good in terms of time, and cost reduction and QTAT (Quick Turn Around Time) of product development can be achieved. Further, the manufacturing departments 10 to 12 can obtain information for increasing the yield, and the design departments 13 to 16 determine which manufacturing department 1 as an LSI manufacturing line for ordering products.
Since it is possible to receive guidance on which of the manufacturing lines 0 to 12 is better, it is expected that the manufacturing efficiency of the LSI is also improved.

FIG. 2 exemplifies the relationship between the service providing processes by the knowledge management server 60. That is, an example shows when or at what timing the knowledge management server 60 is used to provide a service.

Which of the manufacturing departments 10 to 16
12 when weighing whether to request LSI manufacturing,
As one guideline, a service request source among the design departments 13 to 16 requests product yield information for each of the manufacturing departments 10 to 12 (S6). In response, the knowledge management server 60 executes a process of providing product yield data (SV
1). The service request source in the design departments 13 to 16 is based on the obtained product yield data,
Is determined to be equal to or less than the target value (S
7) The service request source in the design departments 13 to 16 can request the knowledge management server 60 to provide a process for improving the line yield (SV5) and take measures. In this way, the yield improvement measures given to the design departments 13 to 16 relate to device design layouts and the like that contribute to yield improvement, such as layouts.

Manufacturing departments 10 to 12 are design departments 13 to 16
There is a case where it is desired to determine whether or not the wafer unit price is appropriate for the desired chip unit price. At this time, a service request source among the manufacturing departments 10 to 12 (line data servers 40 to 43) requests the knowledge management server 60 for wafer unit price data (S1). The knowledge management server 60 includes manufacturing departments 10 to 12
In response to the request (S1) from the service request source, the product yield and chip unit price (unit price desired by the manufacturing department)
A process for obtaining a more appropriate wafer unit price (unit price per wafer) is performed (SV2). Manufacturing department 10 of service requester
In steps S12 to S12, it is determined whether the wafer manufacturing cost is too high (the wafer cost is higher than the budget) with respect to the appropriate wafer cost (S2). Provision of improvement measures (S
V5) can be requested to take countermeasures. The yield improvement measures given at this time are related to device manufacturing, such as device structure and process conditions. The process of providing a line yield improvement measure (SV5) may be performed in response to a request for a yield improvement measure alone from a service request source among the manufacturing departments 10 to 12 (S3).

Design departments 13 to 16 are manufacturing departments 10 to 12
There is a case where it is desired to determine whether or not the chip unit price matches the balance of the desired wafer unit price. At this time, the service request source in the design departments 13 to 16 (design data servers 50 to 53) is the knowledge management server 60.
Request for chip unit price data (S4). The knowledge management server 60 responds to the request (S4) from the service request source in the design departments 13 to 16,
A process for determining an appropriate chip unit price from the product yield and the wafer unit price is performed (SV2). When the chip unit price exceeds the budget (S5), the design departments 13 to 16 requesting the service request the knowledge management server 60 to provide a line yield improvement measure provision processing (SV5) and take measures. Can be. The yield improvement measures given at this time are related to device design layout or the like that contributes to the yield improvement.

The circuit design device parameter providing process (SV3), the circuit design pre-silicon device parameter providing process (SV4), the line mediation process (SV6), and the lot input timing data providing process (SV7) ) Are the design departments 13-1 of the service requester, respectively.
6 or a corresponding request from the manufacturing departments 10 to 12 is executed (S10 to S13).

<< Service Contents and Information Input / Output >> FIG. 3 shows an example of information input / output relating to processing for providing product yield data, wafer unit price, and chip unit price.

[0063] The knowledge management server 60 includes the line data servers 40 to
42 is accessed to capture typical device characteristics, device variation data, wiring variation data, and foreign matter data. Typical device characteristics are characteristic measurement data of various average devices such as Vds-Ids characteristics and Vgs-Ids characteristics of MOS transistors. The device variation data may be variation due to test result data of a wafer probe test for various LSIs manufactured in the past, such as variation in threshold voltage or saturation current of a MOS transistor obtained from past performance. Data. The wiring variation data is the variation data of the wiring capacitance and the wiring resistance of various wiring layers of various materials such as tungsten and aluminum similarly obtained from past results. The foreign substance data is, for example, information on the defect density for each wiring layer. Device variation data and wiring variation data are information that affects device performance, and foreign matter data is information that affects the LSI failure rate.

The knowledge management server 60
Accesses the design data servers 50 to 53 of the target design departments 13 to 16 to obtain benchmark circuits, layout data, product specifications (product specifications), chip unit cost, wafer unit cost,
And information such as the number of chips per wafer. The benchmark circuit is a netlist for circuit simulation relating to a circuit portion that represents the performance of a target LSI.

The knowledge management server 60 performs the following information generation processing using the accessed information.
[1] Performance variations (circuit characteristic variations) relating to benchmark circuits provided by the design departments 13 to 16 are obtained from the device and wiring variation data provided by the manufacturing departments 10 to 12. In short, by the simulation using the benchmark circuit, it is possible to obtain variations in circuit characteristics (variations in circuit performance) according to variations in devices and wiring. [2] A yield (characteristic yield) in terms of performance is obtained from the circuit characteristic variation and product specifications.
[3] The yield (foreign matter yield) due to the foreign matter is obtained from the foreign matter data provided by the manufacturing departments 10 to 12 and the layout data provided by the design departments 13 to 16. [4] A product yield of the target LSI is obtained from the characteristic yield and the foreign matter yield (for example, as a product of both). The product yields obtained in this way are, as a result of the requirements,
The service request source among the 16 design data servers 50 to 53 is obtained. [5] Further, the knowledge management server 60 obtains a wafer unit price appropriate for the balance from the product yield and the chip unit price desired by the design departments 13 to 16. This wafer unit price is a factor of 10
To 12 are acquired. [6] Also, the knowledge management server 60 obtains a chip unit price that matches the balance from the product yield and the wafer unit price desired by the manufacturing departments 10 to 12. The chip unit price is obtained by a service request source among the design departments 13 to 16 as a result of the request.

FIG. 4 shows an example of information input / output relating to the process of providing device parameters for circuit design.

The knowledge management server 60 includes the line data servers 40 to
42, the typical device characteristics, device variation data, and wiring variation data are fetched in the same manner as described above, and the benchmark circuits related to these devices are accessed. The benchmark circuit is a netlist for circuit simulation relating to a circuit portion that represents the performance of a target device.

The knowledge management server 60 uses the accessed information to generate [7] device parameters and [8] wiring parameters. The device parameter is a parameter used when performing a circuit simulation at the time of circuit design, and is, for example, a set of coefficients for representing characteristics of a MOS transistor. Regarding the generation of the parameters, the worst, best, and typical (Worst, Best, Typical)
Acquisition in a mode. The parameters obtained in this way are acquired by the service request source in the design departments 13 to 16 (design data servers 50 to 53) as a result of the request.

FIG. 5 shows a first information input / output example relating to the process of providing a line yield improvement measure. This information input / output is positioned as corresponding to the flow of steps S1, S2, and S3 in FIG.

The knowledge management server 60 includes the line data servers 40 to
42 to access the typical device characteristics and the device variation data along with process conditions,
Then, a benchmark circuit for those devices is accessed.

The knowledge management server 60 uses the information accessed in response to a request from the manufacturing departments 10 to 12,

[9] When it is assumed that the benchmark circuit is manufactured based on the performance and process conditions of the accessed device, a process for obtaining process conditions and a device structure for improving the device performance or reducing variations in device characteristics is performed. Do. In short, this process is performed for a plurality of process conditions while considering circuit characteristics such as whether to operate at high speed based on the benchmark circuit.
The goal is to optimize device structures and process conditions. Line data server 40 of the manufacturing departments 10 to 12
Optimum process conditions as a yield improvement measure given to the service requester among 43 to 43 are, for example, the amount of implanted impurities, ion implantation energy, implantation angle, and the like. Device conditions as a yield improvement measure are, for example, MO
The conditions include the channel length of the S transistor, the oxide film thickness, and the like. That is, the line yield improvement measures given in this process are:
It is about device manufacturing.

FIG. 6 shows a second information input / output example relating to the processing for providing a line yield improvement measure. This information input / output is positioned as corresponding to the flow of steps S4, S5, S6, and S7 in FIG.

The knowledge management server 60 includes the line data servers 40 to
42 to access the typical device characteristics and the device variation data along with process conditions,
Then, line data (data on a line data server) relating to the defect density is accessed. This access information is the same as the access information described in FIG.

Also, the knowledge management server 60
Accesses the design data servers 50 to 53 of the target design departments 13 to 16 and acquires information such as benchmark circuits, layout data, and circuit performance specifications (circuit performance specifications) relating to the target LSI. The benchmark circuit is a netlist for circuit simulation relating to a circuit portion that represents the performance of a target LSI.

It is assumed that the knowledge management server 60 responds to a request from the manufacturing departments 10 to 12 and, based on the accessed information, [10] creates the benchmark circuit based on the performance and process conditions of the accessed device. At this time, a process for obtaining a device-designed layout structure for improving the device performance or reducing device characteristic variations is performed. In short, this process proposes a layout structure that can optimize circuit characteristics while considering circuit characteristics such as whether to operate at high speed based on the benchmark circuit. In other words, process conditions,
The present invention proposes a device structure and a layout structure for reducing defects due to foreign matter.

FIG. 7 shows an example of information input / output relating to the pre-silicon parameter providing process. The pre-silicon parameter (pre-silicon device parameter) means a device parameter generated by predicting a device under other conditions and a device of a next-generation process from a device parameter extracted from an existing device.

The knowledge management server 60 includes the line data servers 40 to
42 to access the typical device characteristics, process variations,
And information on wiring variation (wiring capacitance, wiring resistance) is accessed. Further, information on a device having another target condition or a condition (target device condition) relating to a device of a next-generation process is accessed. The target device conditions include, for example, in the case of a MOS transistor, a gate length (Lg), a gate oxide film thickness (Tox), a relationship between a gate length and a threshold voltage (Lg-Vth), and the like. Further, the knowledge management server 60 accesses the target line data servers 40 to 42 of the manufacturing departments 10 to 12 to acquire information of the benchmark circuit. The benchmark circuit may be a netlist of circuits that can be evaluated by performing a simulation assuming that a circuit designed with an existing device is configured with a target device.

The knowledge management server 60 performs [11] generation of pre-silicon device parameters and [12] generation of pre-silicon wiring parameters using the accessed information. With respect to the generation of the pre-silicon parameter, the worst, best, and typical (Worst, Best, Typical) modes are obtained using the benchmark circuit. The parameters obtained in this way are acquired by the service request source in the design departments 13 to 16 (design data servers 50 to 53) as a result of the request. The service requester in the design departments 13 to 16 can use the obtained pre-silicon device parameters for the target device to perform circuit design while performing simulation before the manufacturing departments 10 to 12 develop a device. Will be possible. As a result, the design department 1
For 3 to 16, it is possible to advance the order of LSI design.

FIG. 8 shows an example of information input / output relating to the process of providing line mediation. This processing is performed by the design departments 13 to 16
This is a process for obtaining information on which manufacturing departments 10 to 12 should be requested, and naturally relates to the yield of the manufacturing departments. Therefore, similarly to the case of FIG. ~ 16 design data servers 50
Target L required by the service requester out of ~ 53
As information necessary for obtaining the SI product yield, the line data servers 40 to 4 of the target manufacturing departments 10 to 12 are used.
2 to access typical device characteristics, device variation data, and foreign matter data, and access and acquire information on benchmark circuits, layout data, and product specifications from the design departments 13 to 16 of the request source. Further, the knowledge management server 60 accesses the target line data servers 40 to 42 of the manufacturing departments 10 to 12 as information necessary for performing the line mediation based on the product yield of the target LSI, and From the requesting design departments 13 to 16, information such as a wafer unit cost budget, a required process, a required number of chips, and a required number of chips obtained from one wafer is acquired.

The knowledge management server 60 uses the accessed information to perform [13] target LS
The product yield of I is obtained, and [14] The unit price per chip is obtained from the product yield and the wafer unit cost budget. In addition, the knowledge management server 60 [15] manufacturing departments 10-1
In each of the two cases, the completion time of a product requested by a service request source in the design departments 13 to 16 is estimated based on the throughput of the production line and the congestion state of the production line. The service request source in the design departments 13 to 16 is the production department 10 to
12 based on the product completion time and chip unit price,
The manufacturing departments 10 to 12 to be requested are selected. In this way, an optimal production section is arranged for producing a product.

FIG. 9 shows an example of information input / output relating to the process of providing lot input timing data. In this process, when a request for a product order and a delivery date is received from the design department to the manufacturing department, information is provided to the manufacturing department in consideration of a periodic change in the status of the manufacturing line of the manufacturing department. That is,
The knowledge management server 60 accesses the line data servers 40 to 42 of the target manufacturing departments 10 to 12 to obtain time-series data on device variation and wiring variation in the manufacturing department described with reference to FIG. In addition, the knowledge management server 60 acquires one lot of manufacturing period and foreign matter data from the target manufacturing department. The knowledge management server 60 also receives the same data from the design data servers of the design departments 13 to 16 as in FIG.
Benchmark circuit, layout data, design specifications,
And information on the tip unit cost budget. Further, the knowledge management server 60 acquires information on the requested delivery date and the required number of chips of the target LSI from the order request source in the design departments 13 to 16 (design data servers 50 to 53) that have requested the manufacturing department.

The knowledge management server 60 performs the following processing using the accessed information. [16] From the time-series device variation data and wiring variation data provided by the manufacturing departments 10 to 12, the characteristic variation of the circuit provided by the order request source in the design departments 13 to 16 is obtained. In short, a simulation by the benchmark circuit obtains a variation in circuit characteristics (variation in circuit performance) according to a variation in device and wiring. [17] A yield (characteristic yield) relating to performance is obtained for each period and period from the product specifications. [18] Foreign matter data provided by the service requester of the manufacturing departments 10 to 12 and the design departments 13 to 16
The yield (foreign matter yield) due to the foreign matter is obtained from the layout data provided by the order request source. [19] From the characteristic yield and the foreign matter yield, obtain a product yield for each time and period for the target product. [20] Design department 13-
In order to manufacture the number requested by the order requester out of 16 by the required delivery date, it is required to determine from which time and for how long the lot of the product is to be flown. The data of the lot input timing and the lot input period obtained as a result are acquired by the service request source in the manufacturing departments 10 to 12 as a result of the request.

<< Manufacturing Processing Method >> FIG. 10 exemplifies a data flow of the product yield calculation according to [1] to [4] described in FIG. In the figure,> Fb means information given to the manufacturing department, Fb> means information given from the manufacturing department, and> Fl means information given to the design department. , Fl> means information given from the design department.

First, device parameters (also referred to as model parameters) are extracted from typical device characteristics obtained from the manufacturing departments 10 to 12 (line data servers 40 to 42) (T1) to perform circuit simulation. Generate typical device parameters. Generated device parameters and manufacturing departments 10-1
Using the device variation data obtained from the second (line data servers 40 to 42), statistical device parameter extraction is executed (T2) to generate process variation data. FIG. 33 shows statistical device parameter extraction (T
2) An outline of the process is illustrated, and based on typical device parameters and device variation data,
For example, process variations such as an oxide film thickness (Tox), a gate length (Lg), a channel dose (Nch), and a short channel effect suppression implant dose (Nlx) of a MOS transistor are generated.

The generated process variation data, wiring resistance and capacitance variation data obtained from the manufacturing departments 10 to 12 (line data servers 40 to 42), and the design departments 13 to 16 (design data servers 50 to 53) The circuit characteristic variation analysis is performed using the benchmark circuit netlist, the power supply voltage specification, and the temperature specification obtained from the service request source (T3), and characteristic variation data is generated. FIG. 35 illustrates a state of the circuit characteristic variation analysis. Using the model parameters, the netlist, and the process variations, variations in circuit characteristics such as variations in the threshold Vth and the drain / source current Ids and variations in the delay time can be obtained.

The obtained characteristic variation data and the design section 1
The characteristic yield calculation process is executed using the circuit performance specification obtained from the service request source in 3 to 16 (design data servers 50 to 53) (T4) to obtain the characteristic yield. FIG. 36 shows an example of the characteristic yield calculation. According to this, the characteristic yield is obtained by the product of the yield for each characteristic obtained from the circuit specifications.

The criticality is determined by using the defect density for each wiring layer obtained from the manufacturing departments 10 to 12 (line data servers 40 to 42) and the layout data obtained from the service request source in the design departments 13 to 16. The area analysis is executed (T5) to obtain the foreign matter yield. The product yield is calculated from the characteristic yield and the foreign matter yield (T6), and the yield of the product is obtained.

Thus, the service request source in the design departments 13 to 16 can know in advance the product yield when ordering the product to each of the manufacturing departments 10 to 12, and select the manufacturing departments 10 to 12. You can do it properly. Since an LSI is manufactured using a manufacturing section appropriately selected in terms of product yield, improvement in LSI manufacturing efficiency or reduction in manufacturing cost can be realized.

FIG. 11 exemplifies a data flow for obtaining an appropriate unit price of a wafer described with reference to FIG. The wafer price is calculated from the product yield obtained as described above, the budget of the chip unit price obtained from the design departments 13 to 16 (design data servers 50 to 53), and the number of chips obtained from one wafer. A unit price is obtained (T7).

As a result, the manufacturing department of the service requester among the manufacturing departments 10 to 12 can know the wafer unit price suitable for the balance with respect to the chip unit price desired by the design departments 13 to 16. By manufacturing the LSI so that the manufacturing department satisfies the unit cost of the wafer, the manufacturing cost of the LSI can be reduced.

FIG. 12 shows an example of a data flow for obtaining the proper unit price of the chip described with reference to FIG. The chip unit price is calculated from the product yield obtained as described above, the wafer unit price obtained from the manufacturing departments 10 to 12 (line data servers 40 to 42), and the number of chips obtained from one wafer, and the appropriate unit price of the chip is calculated. (T8).

As a result, the design departments 13 to 16 can know in advance the cost of ordering the product from each of the manufacturing departments 10 to 12 from the chip unit price.
The cost can be reduced and the profit can be increased by selecting an appropriate manufacturing department from the two. Since an appropriate manufacturing section can be designated in terms of the unit cost of the chip, the manufacturing cost of the LSI can be reduced.

FIG. 13 shows a data flow for generating the device parameters for design described with reference to FIG. Device parameters are extracted from typical device characteristics obtained from the manufacturing departments 10 to 12 (line data servers 40 to 42) (T1), and typical device parameters for circuit simulation are generated.
Using the generated device parameters and device variation data obtained from the manufacturing departments 10 to 12, statistical device parameter extraction is executed (T2) to generate process variation data. Generated process variation data, manufacturing departments 10 to 12 (line data server 4
0 to 42), the variation data of the resistance and capacitance of the wiring obtained from the design departments 13 to 16 (design data servers 50 to 5).
The circuit characteristic variation analysis is executed using the netlist of the benchmark circuit obtained from the service request source in (3) (T3) to generate characteristic variation data. A process of generating worst and best parameters for circuit design from the obtained characteristic variation data is executed (T9), and the obtained device and wiring worst and best parameters are determined by the design departments 13 to 16. (Design data servers 50 to 53). FIG. 37 shows an example of worst and best parameter generation processing. A characteristic with a small delay and a large cutoff current is adopted as a best parameter, and a characteristic with a large delay and a small drain-source current is worst. It is adopted as a parameter.

By the processing of FIG. 13, the design departments 13 to 16
Service requester performs circuit simulation using device parameters, thereby making each manufacturing department 1
It is possible to confirm the characteristics or performance when the manufacture of the product is requested from 0 to 12, and to select an appropriate manufacturing department capable of manufacturing a product satisfying the performance specifications. Improvements in the performance of the manufactured LSI can also be expected.

FIG. 14 is a data flow for seeking a yield improvement measure described with reference to FIG. Device parameters are extracted from typical device characteristics obtained from the manufacturing departments 10 to 12 (line data servers 40 to 42) (T1), and typical device parameters for circuit simulation are generated. Statistical device parameter extraction is executed using the generated device parameters and device variation data obtained from the manufacturing departments 10 to 12 (line data servers 40 to 42) (T
2) Generate process variation data. In addition, device robust processing is executed based on typical device characteristics and device process conditions (T10), and optimum process conditions in the sense of small variations are obtained and provided to the manufacturing department. Figure 4 shows the provided process conditions.
The contents are as shown in FIG. Further, the device characteristic and process variation obtained here and the circuit characteristic variation analysis are performed using the netlist of the benchmark circuit provided by the service requester in the manufacturing departments 10 to 12 (line data servers 40 to 42). Execute (T11)
Provide the manufacturing department with the optimal device structure.

As a result, the service requester in the manufacturing departments 10 to 12 can increase the yield and reduce defective products, which leads to an increase in sales.

FIG. 15 illustrates a data flow for seeking a yield improvement measure exclusively for products of the design department described with reference to FIG. Device parameters are extracted from typical device characteristics obtained from the manufacturing departments 10 to 12 (line data servers 40 to 42) (T1), and typical device parameters for circuit simulation are generated. Statistical device parameter extraction is executed using the generated device parameters and device variation data obtained from the manufacturing departments 10 to 12 (line data servers 40 to 42) (T
2) Generate process variation data. Further, device robust processing is executed based on the characteristics of the typical device and the process conditions of the device (T10), and the service request source in the manufacturing departments 10 to 12 (line data servers 40 to 42) is searched for the optimum process conditions. To provide. Further, a circuit characteristic variation analysis is performed using the device characteristics and process variation obtained here and a netlist of benchmark circuits provided by the design departments 13 to 16 (design data servers 50 to 53) (T11).
The variation in characteristics and the optimum device structure are obtained and provided to service request sources in the manufacturing departments 10 to 12 (line data servers 40 to 42). Furthermore, the design departments 13-16
The characteristic yield of the product is calculated using the specification of the circuit performance obtained from the (design data servers 50 to 53), the characteristic variation obtained above, and the improved device structure (T4). On the other hand, the design departments 13 to 16 (design data servers 50 to 5)
The defect density for each wiring layer obtained from 3) is calculated from the design department 13 to
The critical area analysis is performed using the layout data obtained from the design data servers 16 (design data servers 50 to 53) to obtain the foreign material yield (T5). The product yield is calculated from the characteristic yield and the foreign matter yield (T6), and the yield of the product is obtained.

The product yield obtained by the product yield calculation (T6) is expected to be a yield improvement that can be expected for the manufacturing departments 10 to 12 by improving processes and device structures (improved process conditions and improved device structures). Will have been. In short, the service requester in the manufacturing departments 10 to 12 can increase the yield of the products ordered by the design departments 13 to 16 and reduce the defective products. Therefore, when the sales price of one chip is fixed,
Among them, the service requester can sell one wafer at a higher price, and when the trade price of one wafer is fixed, the cost per chip can be reduced, which leads to an increase in profit.

Critical area analysis processing (T
The improved layout obtained in 5) is the design department 13-16
(Design data servers 50 to 53). Thereby, the service request source in the design departments 13 to 16 can review the layout design so that the yield can be improved. By manufacturing an LSI whose layout configuration has been reviewed, it is expected that the performance of the manufactured LSI will be improved.

FIG. 16 exemplifies a data flow for generating pre-silicon device parameters for circuit design described with reference to FIG. Device parameters are extracted from typical device characteristics obtained from the manufacturing departments 10 to 12 (line data servers 40 to 42) (T1), and typical device parameters for circuit simulation are generated. Pre-silicon device parameter generation processing is executed using the generated device parameters and the channel length dependence of the target device channel length, oxide film thickness, and threshold value (T12) to generate typical pre-silicon device parameters. Manufacturing department 10
The circuit characteristic variation analysis is executed by using the process variation obtained from the line data servers 40 to 42 (variation data of the resistance and the capacitance of the wiring) and the netlist of the benchmark circuit obtained from the foundry (T).
3) Generate characteristic variation data. A process for generating the worst and best parameters for circuit design from the obtained characteristic variation data is executed (T9), and the obtained devices and wiring worst and best pre-silicon parameters are set in the design departments 13 to 16 (design data server). 50 ~
53) to the service request source.

Thus, the service request source in the design departments 13 to 16 can perform a circuit simulation using the device parameters before the manufacturing departments 10 to 12 develop the device. It is possible to check the performance of the characteristics at the time of receiving an order for the manufacture of a product at an early stage, and it is possible to appropriately select a manufacturing department capable of manufacturing a product satisfying the performance specifications.

FIG. 17 shows the design section 1 described with reference to FIG.
An example of a data flow when mediating a production line to a service request source out of 3 to 16 is illustrated. A product request process obtained from a service request source in the design departments 13 to 16,
Requested number and design departments 13 to 16 (design data server 50
５３53), the delivery date of the product is calculated from the throughput of the line and the order status obtained from (T13), and the design department 13-1
6 (design data servers 50-53) to provide information to service request sources, and the design departments 13-16 (design data servers 50-53) that meet the delivery date requirements from the service request sources. Mediate 10-12. The order receiving situation is given as information as exemplified in FIG. At the same time, the product yield and the wafer unit price obtained from the manufacturing departments 10 to 12 (line data servers 40 to 42) and the design departments 13 to 16 (design data server 50).
５３53), calculate the chip unit price from the chip size obtained (T8), provide it to the service requester in the design departments 13 to 16 (design data servers 50 to 53), and design the product in consideration of the product delivery date and the chip unit price. The manufacturing departments 10 to 12 that meet the request from the service request source in the departments 13 to 16 (design data servers 50 to 53) are mediated.

As a result, the design departments 13 to 16 can select a production department that can manufacture a product at an appropriate price and with a desired delivery date. In addition, for the manufacturing departments 10 to 12, it is possible to increase the operating rate of the line, and it is possible to expect an improvement in LSI manufacturing efficiency and an increase in sales.

FIG. 18 exemplifies a data flow for obtaining the lot input timing of the product described in FIG. The device parameters are extracted from the typical device characteristics obtained from the service request source in the manufacturing departments 10 to 12 (line data servers 40 to 42) (T1),
Typical device parameters for circuit simulation are generated. The generated device parameters and the manufacturing departments 10 to 12 (line data servers 40 to 4)
Statistical device parameter extraction is executed using the time-series variation data of the device obtained in 2) (T
2), process variation data is generated. Generated process variation data, manufacturing departments 10-12
(Line data servers 40-42), time-series wiring resistance and capacitance variation data obtained from service request sources, design departments 13-16 (design data servers 50-5)
The circuit characteristic variation analysis is performed using the benchmark circuit netlist, power supply voltage specification, and temperature specification obtained from the order request source in (3) (T3), and time-series characteristic variation data is generated. You. The characteristic yield calculation process is executed using the obtained characteristic variation data and the circuit performance specifications obtained from the order request source in the design departments 13 to 16 (design data servers 50 to 53) (T
4) A time-series characteristic yield is required. The defect density for each wiring layer obtained from the service request source in the manufacturing departments 10 to 12 (line data servers 40 to 42) and the order request in the design departments 13 to 16 (design data servers 50 to 53) A critical area analysis is performed using the layout data obtained from the beginning (T5), and a foreign matter yield is obtained. A product yield is calculated from the characteristic yield and the foreign matter yield (T6), and a time-series yield of the product is obtained. From the chronological yield, the number of good products obtained from one lot is calculated, and from what time and for how long it is necessary to put the product into the line to produce the required quantity by the required delivery date, That is, the lot input timing is obtained (T14).

The device characteristics manufactured on the line are shown in FIG.
As shown in FIG. 8, the frequency fluctuates periodically at the timing of cleaning the production line. By determining the lot input timing using this information, the service request source in the manufacturing departments 10 to 12 (the line data servers 40 to 42) depends on the product specifications. It is possible to allocate the production time according to the product performance, such as introducing the product at a time when the characteristic is high and supplying a medium-speed product or a low-speed product at another time. Further, as illustrated in FIG. 39, when the yield of the high-speed product A fluctuates in synchronization with the cleaning cycle of the manufacturing line, if the required delivery date of the high-speed product A is early, the lot can be input even at a low yield. Will be needed. On the other hand, if the required delivery date is late, a production lot of the product A is put in only at a high yield period, and another product (a low-speed product, a medium-speed product) with a higher yield than the product A during other periods. May be allocated to the production lot. Therefore, the required number can be manufactured with a small number of wafers, and the manufacturing departments 10 to 12 (the line data servers 40 to 4) can be manufactured.
For the service requester of 2), the cost is reduced.

FIG. 19 shows a device parameter extraction (T
The processing method 1) is exemplified from the viewpoint of data flow.
This method is a method of extracting a device parameter expression used for device parameters (model parameters) of static characteristics of the BSIM3 model developed by UCB, that is, a device parameter set 106.

First, the storage device 10 such as a hard disk
From the device characteristics measurement data 101 of the Vds-Ids characteristics and Vgs-Ids characteristics stored in 1, device characteristics such as a short channel effect, a narrow channel effect, a substrate effect, a sub-threshold swing characteristic, and a surface punch-through characteristic of the device are obtained. The intermediate data 103 is generated and stored in a storage device such as a hard disk as an intermediate file. In the intermediate data generation processing 102, the model parameters are hierarchically grouped from the viewpoint of the threshold value, the current, and the like, and the intermediate data 103 of the device characteristics such as the short channel effect and the narrow channel effect are generated.

Next, the intermediate data 103 of the device characteristics stored in the intermediate file and the separately measured MOS data such as the channel length, the oxide film thickness, and the profile stored in the storage device in the hard disk or the like. A parameter extraction process 105 extracts each parameter of the BSIM3 model from the device structure data 104 related to the device
06 is obtained. The device characteristic data and the device structure data are separately measured in advance by a known device characteristic measuring device such as a curve tracer or a tester, or a known analyzing device such as a scanning electron microscope (SEM).

FIG. 20 illustrates the device parameter extraction processing T1 from the viewpoint of the processing procedure. Step S2
In step S22, the device parameters relating to the actual channel length, oxide film thickness, mobility, and saturation speed are determined.
Then, device parameters relating to the execution channel length are extracted. The values of the device parameters for determining the threshold value are set in the order of steps S23 to S27, that is, the substrate effect, the sub-threshold swing characteristic, the surface punch-through characteristic,
The device parameters are extracted in the order of the short-channel effect and the narrow-channel effect. Further, the values of the device parameters relating to the current are set in the order of steps S28 to S30, that is,
The device parameters are extracted in the order of bulk charge effect, parasitic resistance, and effective channel width. In short, device parameters are extracted for each physical phenomenon.

The method for extracting the device parameters described with reference to FIG. 19 is described in detail in, for example, Japanese Patent Application Laid-Open No. 2000-322456.

FIG. 21 illustrates the method of the statistical device parameter extraction processing T2 from the viewpoint of data flow. This method uses the UCB from a large number of MOS characteristic measurement data.
This is a method of extracting a part of the device parameters (model parameters) of the static characteristics of the BSIM3 model, that is, a statistical device parameter set.

First, device information data 111 stored in a storage device such as a hard disk is input, and M
The processing of the netlist generation function unit 112 for performing the circuit simulation of the OS alone is executed, and the obtained netlist 113 is stored as an intermediate file in a storage device such as a hard disk.

The circuit simulation function unit 115 receives the generated netlist 113 and a set of device parameter sets 114 extracted from a specific MOS as inputs.
Is executed, and the output results of the saturation current and the threshold value obtained by the simulation are stored as a circuit simulation output result 116 in a storage device such as a hard disk. The circuit simulator used here is a commonly used SPIC
E-compliant simulator (The Design's
Guide to SPICE &# 38 SPECTRE, Kenneth S. Kundert
Author, Academic Publishers).

Output result 116 of the simulation
And the measurement data 11 of the saturation current and the threshold obtained from the measurement
7 and the convergence determination condition data 118 are input, and the convergence determination function unit 119 compares the two data to determine whether the difference between the saturation current and the threshold obtained by the simulation satisfies the convergence determination condition. .

If the convergence condition is not satisfied, partial device parameters related to the process at this time (device parameters representing oxide film thickness, channel dose, short channel effect suppression implant dose, channel length, channel width) 120 And search range data 1 for each parameter
With 21 as an input, the parameter search function unit 122 changes a parameter value within the search range to determine a new parameter value, and changes a device parameter set and a netlist value. When the convergence condition is satisfied, the device parameter value at that time is stored as a statistical device parameter set 123 in a storage device such as a hard disk.

FIG. 22 illustrates the method of the statistical device parameter extraction processing T2 from the viewpoint of the processing procedure. As shown in the figure, first, the parameters of the oxide film thickness and the channel dose are extracted from the long channel MOS saturation current and the threshold (S41), and then the channel length and the short channel are extracted from the short channel MOS saturation current and the threshold. A parameter representing the effect suppression implant dose is extracted (S42). Finally, a parameter representing the channel width is extracted from the saturation current of the short channel MOS and the threshold (S43). In short, device parameters are extracted for devices having different device sizes and the like. In step S41, parameters are extracted for a saturation current in a long-channel MOS, an oxide film thickness, and a channel dose, which are factors that cause variations in threshold, and in step S42, A parameter representing a channel length and a short channel effect suppression implant dose, which are the causes of the variation in the saturation current and the threshold in the short channel MOS, is extracted. Extract parameters. FIG. 34 shows the difference in parameters extracted between the short channel MOS transistor and the long channel MOS transistor. Represents the typical device characteristics actually obtained by the wafer probe test, and ○ represents the characteristics obtained by the circuit simulation, and illustrates the latter being fitted to the former. The processing in steps S41 to S43 is described in detail in the specification of Japanese Patent Application No. 2000-322456.

FIG. 23 shows the circuit characteristic variation analysis T3.
Is exemplified. According to this, process variations, device parameters, and a net list are read (S45 to S47). Then, a random number is generated from the central value of the process variation, the type of distribution, and the standard deviation (S48), and the device parameters and the netlist value are rewritten accordingly (S49), thereby executing a circuit simulation (S50). Then, the circuit characteristics are executed (S51). The processes in steps S48 to S51 are repeatedly performed for the specified number of times or more, and the process ends.

FIG. 24 exemplifies a processing flow of the characteristic yield calculation T4. First, the characteristic variation and the circuit performance specification are read (S55, S56), and the central value and the standard deviation of the characteristic variation are obtained (S57). Then, by calculating a normal cumulative distribution in a range satisfying the specifications from the distribution of the circuit performance specifications and the characteristic variations, a characteristic yield is obtained (S58), and this is output (S59).

FIG. 25 illustrates a processing flow of the product yield calculation T6. First, the characteristic yield and the foreign matter yield are read (S60, S61), and the product yield is calculated (S6).
2) The calculated product yield is output (S63).

FIG. 26 illustrates a processing flow of the wafer price calculation T7. The product yield, the cost per chip, and the number of chips per wafer are read (S64 to S6).
6) The wafer price is calculated (S67), and the calculated wafer price is output (S68).

FIG. 27 exemplifies a processing flow of the chip unit price calculation T8. Product yield, wafer unit price, wafer 1
The number of chips per chip is read (S70 to S72),
The chip unit price is calculated (S73), and the calculated chip unit price is output (S74).

FIG. 28 illustrates a processing flow of the worst and best parameter generation T9. The characteristic variation is read (S76), the central value of the characteristic variation and the standard deviation are calculated (S77), a condition where the characteristic variation is three times the standard deviation is detected (S78), and the condition is written in the parameter. (S79), and the process ends.

FIG. 29 shows the device robust design T1.
0 is exemplified. This process flow uses a linear programming method. First, parameters and levels are determined (S80), and the parameters and levels are assigned to an orthogonal table (S81).
In response, a process and device simulation are executed (S82). Based on the simulation result, SN regarding the threshold value (Vth) of the MOS transistor
The ratio and the sensitivity are calculated (S83), and the S / N ratio and the degree of duty with respect to Vth and Ids (drain-source current) of the MOS transistor are calculated (S84). It is created (S85), and the optimum condition is determined using it (S86). And SN
The ratio, the sensitivity, and the effect are estimated (S87), and a confirmation simulation is performed on the estimation result (S8).
8) After confirming the reproducibility (S89), the process ends.

FIG. 30 illustrates a processing flow of the pre-silicon device parameter generation T12. The device parameters and information on the target channel length and the oxide film thickness are read (S90, S91), whereby the conditions of the channel length and the oxide film thickness are rewritten (S92).
This time, the Lg-Vth dependency is read (S93),
Lg-Vth dependency matching is performed (S94),
Thereby, the device parameters are rewritten (S95).

FIG. 31 exemplifies a processing flow of the product delivery date calculation T3. First, data of the requested number of requested processes, the throughput, and the order status are read (S96).
~ 98). The line introduction timing of the required product is calculated from the read order status and the line throughput (S9).
9). Further, the throughput of the line is read from the requested process (S100), and the delivery date of the requested product is calculated from the line input timing of the requested product and the throughput of the requested process (S101).

FIG. 32 exemplifies a processing flow of calculation T14 of the lot input timing and period of the product. First, the number of chips per chip, the required number, and the required delivery date are read (S102), and the product yield in time series is read (S103). The lot input timing for performing the lot out before the delivery date from the period is calculated (S104). Then, prior to the lot input timing, the products are selected in descending order of yield (S105), and the number of non-defective products is calculated from the product yield and the number of chips per wafer (S106). Is determined to be greater than or equal to the required number (S107). If the number of non-defective products is small, the process returns to step S105 and the process is repeated. Is output (S108),
The process ends.

FIG. 42 shows the knowledge management server 6.
0, the data providing sources and providing timings (or access timings) for various data such as the typical device data used are shown in an organized manner.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, the content of the service provided by the knowledge management server is not limited to the content shown in FIG. 1, and can be changed as appropriate. It manages information obtained from the manufacturing department and the design department, integrates information from both sides to generate or process information that is valid for both parties, and transfers the generated information and processed information from the manufacturing department and the design department. Any service provided in response to the request may be used.

In the example of FIG. 1, the manufacturing department has one line data server, the design department has one design data server, and the manufacturing department is equivalent to the one line data server. As described above, the design department was described as being equivalent to one design data server, but it is natural that the manufacturing department and the design department may each include a plurality of data servers, in which case, Service requests and data provision are performed in line data server units and design data server units.

[0131]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, based on information on devices manufactured by the manufacturing department and information on chips designed by the designing department, L
It is possible to generate information such as parameter information, yield information, chip unit price, and the like necessary for SI design, to generate information for the design department, and to provide the manufacturing department with information for increasing the yield. The design department can determine from which manufacturing department it is costly and timely to order products,
Circuit design can be advanced in advance, and cost reduction, QTAT development of product development, and improvement in LSI performance can be achieved. The manufacturing department can obtain information for increasing the yield, and the design department can receive a line for ordering a product, so that an effect of improving the sales of the LSI can be expected. In short, an LSI can be manufactured by reflecting the contents of the information.
I manufacturing efficiency improvement, LSI manufacturing cost reduction, and LS
The performance of I can be expected to improve.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a first embodiment of an information processing system according to the present invention connected to a network.

FIG. 2 is a flowchart illustrating an example of a relationship between service providing processes by a knowledge management server.

FIG. 3 is an explanatory diagram of information input and output regarding provision processing of product yield data, wafer unit price, and chip unit price.

FIG. 4 is an explanatory diagram of information input / output relating to provision processing of circuit design device parameters.

FIG. 5 is an explanatory diagram of first information input / output relating to a process of providing a line yield improvement measure.

FIG. 6 is an explanatory diagram of second information input / output relating to a process of providing a line yield improvement measure.

FIG. 7 is an explanatory diagram of information input / output relating to a pre-silicon parameter providing process.

FIG. 8 is an explanatory diagram of information input / output relating to a process of providing a line placement.

FIG. 9 is an explanatory diagram of information input / output relating to a lot input timing data providing process.

10 is a data flow of product yield calculation according to [1] to [4] described in FIG.

FIG. 11 is a data flow for obtaining an appropriate unit price of a wafer described in FIG. 3;

FIG. 12 is a data flow for obtaining an appropriate unit price of a chip described in FIG. 3;

FIG. 13 is a data flow for generating the device parameters for design described in FIG. 4;

FIG. 14 is a data flow for seeking a yield improvement measure described with reference to FIG. 5;

FIG. 15 is a data flow for seeking a yield improvement measure exclusively for products of the design department as described with reference to FIG. 6;

FIG. 16 is a data flow for generating pre-silicon device parameters for circuit design described in FIG. 7;

FIG. 17 is a data flow when a production line is introduced to a service request source in the design departments 13 to 16 described with reference to FIG.

FIG. 18 is a data flow for obtaining the lot input timing of the product described in FIG. 9;

FIG. 19 is a flowchart illustrating a processing method of device parameter extraction (T1) from the viewpoint of a data flow.

FIG. 20 is a flowchart illustrating a device parameter extraction process (T1) from the viewpoint of a processing procedure.

FIG. 21 is a flowchart illustrating a method of statistical device parameter extraction processing (T2) from the viewpoint of data flow.

FIG. 22 is a flowchart illustrating a method of statistical device parameter extraction processing (T2) from the viewpoint of a processing procedure.

FIG. 23 is a flowchart illustrating a process of circuit characteristic variation analysis (T3).

FIG. 24 is a flowchart illustrating a processing flow of characteristic yield calculation (T4).

FIG. 25 is a flowchart illustrating a processing flow of a product yield calculation (T6).

FIG. 26 is a flowchart illustrating a processing flow of calculating a wafer price (T7).

FIG. 27 is a flowchart illustrating a processing flow of chip unit price calculation (T8).

FIG. 28 is a flowchart illustrating a processing flow of worst and best parameter generation (T9).

FIG. 29 is a flowchart illustrating a processing flow of device robust design (T10).

FIG. 30 shows pre-silicon device parameter generation (T1).
It is a flowchart which illustrates the processing flow of 2).

FIG. 31 is a flowchart illustrating a process flow of calculating a product delivery date (T3).

FIG. 32: Calculation of lot input timing and period of product (T1)
It is a flowchart which illustrates the processing flow of 4).

FIG. 33 is an explanatory diagram schematically illustrating a process of statistical device parameter extraction (T2).

FIG. 34 is an explanatory diagram illustrating a difference in parameters extracted between a short channel MOS transistor and a long channel MOS transistor.

FIG. 35 is an explanatory diagram illustrating an example of a circuit characteristic variation analysis;

FIG. 36 is an explanatory diagram illustrating an example of a characteristic yield calculation.

FIG. 37 is an explanatory diagram illustrating an example of worst and best parameter generation processing;

FIG. 38 is an explanatory diagram exemplifying a state in which device characteristics manufactured in a line vary periodically with a cleaning timing of the manufacturing line.

FIG. 39 is an explanatory diagram illustrating a state in which the yield of high-speed products fluctuates in synchronization with a cleaning cycle of a manufacturing line.

FIG. 40 is an explanatory diagram illustrating a process condition expression.

FIG. 41 is an explanatory diagram showing an example of information indicating the order receiving status of the manufacturing department.

FIG. 42 is an explanatory diagram showing the data providing sources and providing timings for various data such as typical device data used by the knowledge management server.

[Explanation of symbols]

 10A, 10-12 Manufacturing department 13A, 13-16 Design department 17 Service provider 18 Network 20-22 Manufacturing line 30-32 Measuring instrument 40-42,43 Line data server 50-53,54 Design data server 60,61,62 Knowledge Management Server

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Joe Yoji 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group of Hitachi, Ltd. No. 20-1, Hitachi Semiconductor Co., Ltd. (72) Megumi Kawakami Inventor 5--20-1, Kamisumihonmachi, Kodaira-shi, Tokyo F-term, Hitachi Semiconductor Group 5B046 AA08 CA06

Claims (34)

[Claims] 1. A process in which a first computer device inputs element characteristic information of a semiconductor device via a network from a second computer device in a manufacturing section having a semiconductor integrated circuit manufacturing facility, and a design section for designing a semiconductor integrated circuit. A first computer device inputting design information of a semiconductor integrated circuit from a third computer device via a network; a process of requesting a service from the second computer device to the first computer device; A process of generating response information required by the requestor in response to the service request based on the input device characteristic information and design information, and returning the generated response information to the requesting second computer device; A semiconductor integrated circuit using manufacturing equipment corresponding to the second computer device to which the response information has been returned And the process of production,
A method for manufacturing a semiconductor integrated circuit, comprising: 2. A process in which a first computer device inputs element characteristic information of a semiconductor element via a network from a second computer device in a manufacturing section having a semiconductor integrated circuit manufacturing facility, and a design section for designing a semiconductor integrated circuit. A first computer device inputting design information of a semiconductor integrated circuit from a third computer device via a network; a process of requesting a service from the second computer device to the first computer device; In response to the service request, response information required by the request source is generated on the assumption that a semiconductor device specified by the device characteristic information is used in a semiconductor integrated circuit, and the generated response information is generated by the request source. Second
A process of returning to the computer device, a process of manufacturing a semiconductor integrated circuit using a manufacturing facility corresponding to the second computer device to which the response information has been returned,
A method for manufacturing a semiconductor integrated circuit, comprising: 3. The semiconductor device according to claim 3, wherein the response information is information on a predicted yield when a semiconductor integrated circuit is configured using an element specified by the element characteristic information and a chip desired by a design information supplier of the semiconductor integrated circuit. 3. The method according to claim 1, further comprising wafer unit price information generated based on the unit price information. 4. The process for manufacturing the semiconductor integrated circuit includes:
4. The method according to claim 3, wherein the process satisfies a wafer unit price specified by the wafer unit price information. 5. The response information is based on time-series element characteristic information of a semiconductor element input from the second computer device, and a required amount and a production deadline of the semiconductor integrated circuit input from the third computer device. 3. The method for manufacturing a semiconductor integrated circuit according to claim 1, further comprising information on a formed lot delivery time that satisfies a delivery date and a small number of wafers of the semiconductor integrated circuit. 6. A process for manufacturing the semiconductor integrated circuit, comprising:
6. The process according to claim 5, wherein the process satisfies a lot input timing specified by the information on the lot input timing.
The manufacturing method of the semiconductor integrated circuit described in the above. 7. A process in which a first computer device inputs element characteristic information of a semiconductor device via a network from a second computer device in a manufacturing section having a semiconductor integrated circuit manufacturing facility, and a design section for designing a semiconductor integrated circuit. A first computer device inputting design information of a semiconductor integrated circuit from a third computer device via a network, a process of requesting a service from the third computer device to the first computer device, A process of generating response information required by the request source in response to the service request based on the input element characteristic information and design information, and returning the generated response information to the requesting third computer device; A semiconductor integrated circuit using a manufacturing facility designated by the third computer device to which the response information has been returned And the process of production,
A method for manufacturing a semiconductor integrated circuit, comprising: 8. A process in which a first computer device inputs element characteristic information of a semiconductor element via a network from a second computer device in a manufacturing section having a semiconductor integrated circuit manufacturing facility, and a design section for designing a semiconductor integrated circuit. A first computer device inputting design information of a semiconductor integrated circuit from a third computer device via a network, a process of requesting a service from the third computer device to the first computer device, In response to the service request, response information required by the requester is generated on the assumption that a semiconductor device specified by the device characteristic information is used in the semiconductor integrated circuit, and the generated response information is generated by the request. A process to return to the original third computer device, and the third computer device to which the response information is returned is designated A process of manufacturing a semiconductor integrated circuit by using the manufacturing equipment,
A method for manufacturing a semiconductor integrated circuit, comprising: 9. The method according to claim 9, wherein the response information includes predicted yield information assuming that the semiconductor integrated circuit is configured using an element specified by the element characteristic information input from the second computer device. 9. The method for manufacturing a semiconductor integrated circuit according to claim 7, wherein: 10. The method of manufacturing a semiconductor integrated circuit according to claim 9, wherein the third computer device specifies a manufacturing facility whose yield specified by the predicted yield information is relatively high. 11. The response information according to claim 9, wherein said response information includes chip unit price information generated based on said predicted yield information and desired wafer unit price information provided from said second computer device. A method for manufacturing a semiconductor integrated circuit. 12. The method of manufacturing a semiconductor integrated circuit according to claim 11, wherein said third computer specifies a manufacturing facility whose unit price specified by said chip unit price is relatively low. 13. The semiconductor device according to claim 7, wherein the response information includes information on a layout structure for a semiconductor integrated circuit for reducing variation in circuit characteristics of a benchmark circuit provided from the third computer device.
Or a method of manufacturing a semiconductor integrated circuit according to item 8. 14. The method according to claim 13, wherein the third computer device specifies a manufacturing facility for manufacturing a semiconductor integrated circuit having a layout modified based on the information on the layout structure. . 15. The semiconductor device according to claim 15, wherein said response information is chip unit price information obtained from predicted yield information of said semiconductor integrated circuit and desired wafer unit price information given from said third computer unit, 10. The method of manufacturing a semiconductor integrated circuit according to claim 9, further comprising information on a congestion state of a manufacturing facility and information on a completion time of a required wafer obtained based on a throughput of the manufacturing facility provided together with the element characteristic information. 16. The semiconductor integrated circuit according to claim 15, wherein said third computer device designates a manufacturing facility with a faster completion time at a relatively lower cost than the information on the chip unit price and the completion time. Production method. 17. A process in which a first computer device inputs element characteristic information of a semiconductor device via a network from a second computer device of a manufacturing section having a semiconductor integrated circuit manufacturing facility, and a design section for designing a semiconductor integrated circuit. Requesting a service from the third computer device to the first computer device, and the first computer device responding to the service request.
A process of generating device parameters for simulating the device characteristics specified by the input device characteristic information, and returning the generated device parameters to a third computer as the request source; A method for manufacturing a semiconductor integrated circuit, comprising: performing a circuit simulation using the semiconductor device; and manufacturing a semiconductor integrated circuit using manufacturing equipment designated by a third computer device. 18. A process in which a first computer device inputs device characteristic information of a semiconductor device and device conditions of an unknown semiconductor device via a network from a second computer device of a manufacturing section having a semiconductor integrated circuit manufacturing facility, and A process of requesting a service from the third computer device of the design department for designing an integrated circuit to the first computer device, wherein the first computer device responds to the service request;
A process of generating pre-silicon device parameters for simulating the device characteristics of the unknown semiconductor device based on the input device characteristics information and the device conditions, and returning the generated pre-device parameters to the request source; Manufacturing a semiconductor integrated circuit, comprising: a process in which a device performs a circuit simulation using the pre-silicon device parameters; and a process in which a third computer device manufactures a semiconductor integrated circuit using manufacturing equipment designated by the third computer device. Method. 19. A process in which a first computer device inputs device characteristic information of a semiconductor device and benchmark circuit information using the device from a second computer device of a manufacturing section having a semiconductor integrated circuit manufacturing facility via a network. Processing for requesting a service from the second computer device to the first computer device; and responding to the service request by the first computer device,
A process of generating response information obtained by assuming that a benchmark circuit is configured using the element specified by the element characteristic information, and returning the generated response information to the request source; and A process of manufacturing a semiconductor integrated circuit using a manufacturing facility corresponding to the computer device;
A method for manufacturing a semiconductor integrated circuit, comprising: 20. The semiconductor integrated circuit circuit according to claim 19, wherein the response information includes information on a process condition and a device structure for a semiconductor element for reducing variation in circuit characteristics of the benchmark circuit. Method. 21. The manufacturing of a semiconductor integrated circuit according to claim 20, wherein the processing for manufacturing the semiconductor integrated circuit is performed using a manufacturing facility reflecting the information on the process conditions and the device structure. Method. 22. A process in which a first computer device inputs element characteristic information of a semiconductor element via a network from a second computer device in a manufacturing section having a semiconductor integrated circuit manufacturing facility, and a design section for designing a semiconductor integrated circuit. A first computer device inputting design information of a semiconductor integrated circuit from a third computer device via a network, and the first computer device executes the design section based on the input element characteristic information and design information. Generating the predicted yield information of the product when it is assumed that the product requested by the manufacturing department is manufactured, and the third computer device has a relatively high yield specified by the predicted yield information. The process includes a process of designating a manufacturing facility and a process of manufacturing a semiconductor integrated circuit by a manufacturing department using the designated manufacturing facility. The method of manufacturing a semiconductor integrated circuit according to claim. 23. The method according to claim 13, further comprising a process in which the first computer generates wafer unit price information based on the predicted yield information and chip unit price information provided from a third computer in the design department. A method for manufacturing a semiconductor integrated circuit according to claim 22. 24. The method according to claim 23, wherein the processing for manufacturing the semiconductor integrated circuit satisfies a wafer unit price specified by the wafer unit price information. 25. The apparatus according to claim 25, further comprising a process in which the first computer generates chip unit price information based on the predicted yield information and wafer unit price information presented from the second computer in the manufacturing section. A method for manufacturing a semiconductor integrated circuit according to claim 22. 26. A process for designating the manufacturing equipment, wherein the yield designated by the predicted yield information is relatively high, and
26. The method of manufacturing a semiconductor integrated circuit according to claim 25, wherein the process is a process of designating a manufacturing facility whose chip unit price specified by the chip unit price information is relatively low. 27. The apparatus according to claim 26, further comprising a process of estimating a completion time of a required wafer based on a manufacturing equipment congestion state and a manufacturing equipment throughput input from a second computer device of the manufacturing section. A method for manufacturing a semiconductor integrated circuit. 28. A process for designating the manufacturing equipment, wherein the yield specified by the predicted yield information is relatively high, the chip unit price specified by the chip unit price information is relatively low, and 28. The method of manufacturing a semiconductor integrated circuit according to claim 27, wherein the processing is a process of designating a satisfying manufacturing facility. 29. Based on the time-series element characteristic information of the semiconductor device input from the second computer device of the manufacturing department, and the required amount of the semiconductor integrated circuit and the production delivery date input from the third computer device of the design department. 23. The method of manufacturing a semiconductor integrated circuit according to claim 22, further comprising a process of generating information on a lot input time that satisfies a delivery date and a small number of wafers of the semiconductor integrated circuit. 30. The method of manufacturing a semiconductor integrated circuit according to claim 29, wherein the process of manufacturing the semiconductor integrated circuit is performed in accordance with a lot input timing indicated by information on a lot input timing. 31. A process in which a first computer device inputs element characteristic information of a semiconductor element via a network from a second computer device in a manufacturing section having a semiconductor integrated circuit manufacturing facility, and based on the input element characteristic information. A process in which the first computer device generates device parameters necessary for circuit simulation for performing circuit design, and a third computer device in a design department designing a semiconductor integrated circuit performs circuit simulation using the device parameters. A method of manufacturing a semiconductor integrated circuit, comprising: processing; and manufacturing a semiconductor integrated circuit using manufacturing equipment designated by a third computer device. 32. A process in which a first computer device inputs device characteristic information of an existing semiconductor device and device conditions of an unknown semiconductor device via a network from a second computer device of a manufacturing section having a semiconductor integrated circuit manufacturing facility. A process in which a first computer device generates a pre-silicon device parameter for simulating a blocking characteristic of the unknown semiconductor device based on the input device characteristic information and the device condition; and a design department for designing a semiconductor integrated circuit. A semiconductor integrated circuit comprising: a process in which a third computer device performs a circuit simulation using the pre-silicon device parameters; and a process in which a semiconductor integrated circuit is manufactured using manufacturing equipment designated by the third computer device. Circuit manufacturing method. 33. A process for inputting element characteristic information of a semiconductor element via a network from a second computer device in a manufacturing section having semiconductor integrated circuit manufacturing equipment, and a third computer device in a design section for designing a semiconductor integrated circuit. A first computer device inputs design information of a semiconductor integrated circuit via a network from a computer, and based on the input device characteristic information and design information, the first computer device generates a benchmark circuit included in the design information. A process of generating improvement measure information relating to a layout structure for reducing circuit characteristic variations; and a third computer device of a design department designating a manufacturing facility for manufacturing a semiconductor integrated circuit whose layout is corrected based on the improvement measure information. And manufacturing a semiconductor integrated circuit using designated manufacturing equipment. The method of manufacturing a semiconductor integrated circuit, characterized in that it comprises a and. 34. A first computer device inputs, via a network, a second computer device of a manufacturing section having a semiconductor integrated circuit manufacturing facility, via a network, element characteristic information of a semiconductor element and benchmark circuit information using the semiconductor element. A process for a semiconductor device for reducing a variation in circuit characteristics of the benchmark circuit in response to a request from the second computer device based on the input device characteristic information and benchmark circuit information. Processing for generating improvement measure information relating to conditions and device structures; processing for providing the improvement measure information to the requesting second computer; and manufacturing equipment corresponding to the second computer provided with the improvement measure information. Reflecting process conditions and device structure based on the improvement information A method of manufacturing a semiconductor integrated circuit, comprising: a process of manufacturing a semiconductor integrated circuit.