JP2002352730A - Plasma display panel and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plasma display panel enabling reductions of voltages of write-in and discharging. SOLUTION: The plasma display panel comprises a first substrate where a plurality of electrode pairs, consisting of the first electrode and the second electrode respectively, are disposed in parallel in stripe formation and are covered with a dielectric layer further, and the second substrate where the third electrodes are disposed in stripe formation, where both the substrates are facing each other via partitioning ribs. The plasma display panel is provided with distinctive construction, that whiskers are formed at least on a portion of a surface layer of the dielectric layer or a dielectric layer protective film which covers the dielectric layer further.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel used for a display device and the like, and more particularly to a panel structure for eliminating a discharge delay.

[0002]

2. Description of the Related Art Conventional plasma display panels are:
The configuration shown in FIG. 3 is generally used.

[0003] The plasma display panel includes a front panel 100 and a rear panel 200. The front panel 100 includes a scan electrode 102 on a front glass substrate 101.
a, sustain electrodes 102b are alternately formed in a stripe shape, and are further formed by being covered with a dielectric glass layer 103 and a protective layer 104 made of magnesium oxide (MgO).

[0004] The rear panel 200 includes a rear glass substrate 20.
1, an address electrode 202 is formed in a stripe shape, an electrode protection layer 203 is formed so as to cover the address electrode 202, and a partition wall 204 is formed in a stripe shape on the electrode protection layer 203 so as to sandwich the address electrode 202. Furthermore, the partition wall 20
It is formed by providing a phosphor layer 205 between the four. Then, the front panel 100 and the rear panel 200 are bonded together, and a discharge space is formed by filling a discharge gas into a space 210 partitioned by the partition wall 204. The phosphor layer is usually red for color display.
Phosphor layers of three colors of green and blue are arranged in order.

[0005] In the discharge space 210, for example, a discharge gas obtained by mixing neon and xenon is usually 0.6.
It is sealed at a pressure of about 7 × 10 ⁵ Pa.

Next, a driving method of the plasma display panel will be described.

FIG. 4 is a block diagram showing a configuration of a driving circuit of the plasma display panel. The drive circuit includes an address electrode drive unit 220, a scan electrode drive unit 230, and a sustain electrode drive unit 240.

An address electrode drive section 220 is connected to the address electrodes 202 of the plasma display panel, a scan electrode drive section 230 is connected to the scan electrodes 102a, and a sustain electrode drive section 240 is connected to the sustain electrodes 102b.

In general, in an AC type plasma display panel, an image of one frame is displayed in a plurality of subfields (S.
F. ) Is used to perform gradation expression. In this method, 1S. Is applied to control the discharge of gas in the cell. F. Is further divided into four periods. The four periods will be described with reference to FIG. FIG. F. It is a middle drive waveform.

In FIG. 5, a setup period 250 is shown.
In this case, wall charges are uniformly accumulated in all cells in the PDP in order to easily generate a discharge. In the address period 260, write discharge of the cell to be lit is performed. In the sustain period 270, the cells written in the address period 260 are turned on and the lighting is maintained. Erase period 280
Then, the lighting of the cell is stopped by erasing the wall charges.

In the setup period 250, the scan electrodes 10
A voltage higher than that of the address electrode 202 and the sustain electrode 102b is applied to 2a to discharge the gas in the cell. The generated charges are accumulated on the cell wall so as to cancel the potential difference between the address electrode 202, the scan electrode 102a, and the sustain electrode 102b.
Negative charges are accumulated as wall charges on the surface of the protective film in the vicinity, and positive charges are accumulated as wall charges on the surface of the phosphor layer near the address electrodes and on the surface of the protective film near the sustain electrodes. The wall charges generate a predetermined value of wall potential between the scan electrode and the address electrode and between the scan electrode and the sustain electrode.

In the address period 260, when the cell is turned on, a voltage lower than that of the address electrode 202 and the sustain electrode 102b is applied to the scan electrode 102a, that is, between the scan electrode and the address electrode, in the same direction as the wall potential. And a voltage is applied between the scan electrode and the sustain electrode in the same direction as the wall potential to generate a write discharge. As a result, negative charges are accumulated on the phosphor layer surface and the protective layer surface, and positive charges are accumulated as wall charges on the protective layer surface near the scanning side electrode. As a result, a predetermined value of the wall potential is generated between the sustain electrode and the scan electrode.

In the sustain period 270, the scan electrode 102
A sustain discharge is generated by applying a higher voltage to a than in the sustain electrode 102b, that is, by applying a voltage between the sustain electrode and the scan electrode in the same direction as the wall potential. Thereby, cell lighting can be started. Then, by applying a pulse so that the polarity is alternately switched between the sustain electrode and the scan electrode, the pulse can be emitted intermittently.

In the erase period 280, an incomplete discharge occurs by applying a narrow erase pulse to the sustain electrode 102b, and the wall charges disappear, so that the erase operation is performed.

[0015]

By the way, when a television image is displayed because the number of scanning lines increases as the cell structure becomes higher definition, all the sequences within one field = 1/60 [s] are required. Must be terminated. In order to respond to this, it is necessary to perform high-speed driving by narrowing the pulse width of the address pulse applied during the writing period.However, there is a “discharge delay” that discharge occurs considerably later than the rise of the pulse. In addition, the probability that the discharge ends within the applied pulse width decreases, and writing cannot be performed on a cell to be lit originally, resulting in lighting failure.

The present invention has been made in view of the above problems, and has as its object to provide a plasma display panel having a structure effective for preventing "discharge delay" and a method of manufacturing the same. It is a thing.

[0017]

First, it is considered that the main cause of the discharge delay is that initial electrons serving as a trigger when the discharge is started are hardly released from the substrate surface into the discharge space.

Accordingly, it is considered that if a situation where the initial electrons are easily emitted can be created, a discharge delay can be effectively prevented.

As a method for this, a method of increasing the drive pulse voltage at the time of addressing and maintaining the discharge, or reducing the distance between the electrodes can be considered. However, the increase in the pulse voltage is such that the withstand voltage of the switching element of the drive circuit and the slew rate are in a contradictory relationship. Therefore, in the high withstand voltage element, the rise of the pulse is slowed down, and there is a limit in suppressing the discharge delay time. Reducing the distance between the electrodes also decreases the height of the partition walls at the same time. However, if the height of the partition walls is reduced in this way, the discharge space itself is reduced, and the volume per unit volume surrounding the plasma is reduced. Since the area of the wall surrounding the discharge space increases, the efficiency is reduced due to the so-called wall loss that the plasma disappears when the plasma collides with the wall.

Accordingly, the present inventors have sought a panel structure which can prevent a discharge delay even if the configuration of the drive circuit and the distance between the electrodes follow the conventional one without any change. As a result, the present invention has been made.

That is, in order to achieve the above object, according to the present invention, a plurality of electrode pairs of a first electrode and a second electrode arranged in stripes are arranged in parallel, and the plurality of electrode pairs are further arranged. A plasma display panel in which a first substrate covered with a dielectric layer and a second substrate on which third electrodes are arranged in stripes are arranged to face each other with a partition wall interposed therebetween. A whisker structure is present in at least a part of a surface layer of the dielectric layer or a surface layer of a dielectric protective film further covering the dielectric.

Here, the whisker structure generally indicates that the film grows differently from the previous film growth due to impurities, stress, and the like generated at that location. Not limited to this, it indicates that the film grows with a change in the crystal structure, lattice constant, shape, or the like from that location.

Here, it is desirable that the whisker portion is a single crystal of MgO.

The whisker part has a diameter of 0.1 to 0.1 mm.
Desirably, it is 2.0 nm.

Here, it is preferable that the whisker portion is formed by a thermal chemical vapor deposition method or a plasma chemical vapor deposition method using an organometallic compound of magnesium and oxygen.

An underlayer is formed between the dielectric layer and the protective film, and the underlayer contains at least one of a Group 2a element, a Group 3b element, and a transition metal in the periodic table. It is desirable.

Here, it is desirable that the underlayer has a (110) or (100) plane orientation.

Thus, in the surface layer of the dielectric layer,
The electric field intensity due to the applied voltage increases, and the amount of electrons emitted toward the discharge space increases. As a result, trigger electrons for the address discharge and the sustain discharge are easily released, so that the discharge delay at the time of the address discharge and the sustain discharge can be suppressed, and the response of the occurrence of the discharge to the voltage application can be improved. A good image can be displayed.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An AC type plasma display panel according to an embodiment of the present invention will be specifically described below with reference to the drawings.

FIG. 1 shows an AC surface discharge type plasma display panel 1 (hereinafter simply referred to as P) according to an embodiment of the present invention.
DP1).

The PDP 1 generates a discharge in the discharge space 30 by applying a pulsed voltage to each electrode, and emits visible light of each color generated on the rear panel PA2 side by the discharge to the main panel PA1. This is an AC surface discharge type PDP that transmits light from the surface.

The front panel PA1 is formed on a front glass substrate 11 in which a plurality of scanning electrodes 12a and sustaining electrodes 12b are arranged in a stripe pattern (one pair is shown for convenience in the drawing) so as to cover the front surface 11a. A dielectric glass layer 13 is formed, and a protective layer 14 made of MgO is formed so as to cover the dielectric glass layer 13.

The back panel PA2 protects the address electrodes on a back glass substrate 16 in which the address electrodes 17 are arranged in a stripe shape so as to be orthogonal to the scan electrodes 12a and the sustain electrodes 12b so as to cover the address electrodes 17. In addition, an electrode protection layer 18 is formed to serve to reflect visible light to the front panel side. The electrode protection layer 18 extends on the electrode protection layer 18 in the same direction as the address electrodes 17 and partitions the address electrodes 17 therebetween. 19, and a phosphor layer 20 is provided between the partition walls 19.

The PDP having the above configuration is driven based on the driving waveform shown in FIG. 6 using the driving circuit shown in FIG. The address electrodes 17 are connected to the address electrode driving section 220, the scanning electrodes 12 a are connected to the scanning electrode driving section 230, and the sustain electrodes 12 b are connected to the sustain electrode driving section 240.

(Detailed Structure) FIG. 2A is a vertical sectional view including the line AA ′ in FIG. 1, and FIG. 2B is an enlarged view of a whisker portion.

As shown in FIG. 2, the structure of the protective layer 14 is characteristic in the PDP.

The protective layer 14 includes an underlayer 14a and a whisker portion 14b.

The underlayer 14a is formed between the whisker portion 14b and the dielectric glass layer 13.

The whisker portion 14b is formed by densely arranging crystals of a plurality of protective film components in a whisker shape.

(Effects) As described above, since the outermost surface of the protective layer facing the discharge space has a whisker structure, an electric field distribution is generated in the protective layer surface, and there are places where the electric field intensity is extremely strong. Accordingly, the amount of electrons emitted from the place where the electric field strength is strong toward the discharge space increases. as a result,
Since trigger electrons for address discharge and sustain discharge are easily emitted, a discharge delay at the time of address discharge and sustain discharge can be suppressed, responsiveness of discharge to voltage application can be improved, and a good image can be obtained. Can be displayed.

From such a viewpoint, it is important to define the size of the whisker portion 14b and the density occupying a certain area. Specifically, the diameter of the whisker portion 14b is set to 0.1
It is desirable to set it to 2.0 nm. With such a definition, a discharge delay at the time of an address discharge or a sustain discharge can be more effectively suppressed.

As described above, in the whisker portion 14b,
In order to form a dense whisker structure with good crystallinity, an underlayer 14a is required between the dielectric glass layer 13 and the whisker portion 14b. The underlayer 14a is preferably an oxide, a nitride, or a fluoride containing at least one of Group 2a element, Group 3b element and transition metal in the periodic table. Specifically, when TiO ₂ and SiO ₂ were used, the whisker portion 14b showed good crystallinity.

(Method of Manufacturing PDP) Next, a method of manufacturing PDP will be described.

(Assembly of PDP) (Preparation of Front Panel PA1) First, the front glass substrate 11
The scan electrodes 12a and the sustain electrodes 12b are formed so as to be alternately arranged thereon.

The scanning electrode 12a and the sustaining electrode 12b are metal electrodes, and are formed by forming a platinum film by an electron beam evaporation method and then patterning the film by a lift-off method. Note that each scanning electrode 12a and sustain electrode 12b may be formed by a pair of a transparent electrode such as ITO and a metal electrode.

Next, the scanning electrode 12a and the sustain electrode 1
The dielectric glass layer is formed by printing and baking by a known printing method such as a screen printing method so as to cover 2b.

Next, the protective layer 1 is formed on the surface of the dielectric glass layer 13.
4 is formed. In the present invention, the underlayer 14a is formed first, and then the whisker portion 14b is formed. Specifically, the underlayer 14a is formed by a vapor deposition method, a magnetron RF sputtering method, or the like, but the present invention is not limited to this manufacturing method alone.

The whisker portion 14b is suitably formed by a CVD method (chemical vapor deposition method).
Is used, the organic metal containing MgO is vaporized and transported into a CVD apparatus by a carrier gas such as nitrogen to form a film. Although the present invention has been described with reference to the CVD method, the present invention is not limited to this. Includes construction methods that can obtain a shape.

(Preparation of Back Panel PA2) Back Panel P
In A2, an address electrode 17 is formed on a rear glass substrate 16, and the address electrode 17 is covered with an electrode protection layer 18. A partition 19 is formed on the surface of the electrode protection layer 18.
It is produced by forming

The address electrodes 17 are formed on the back glass substrate 16.
The upper electrode is manufactured by the same method as that of the scanning electrode 12a and the sustain electrode 12b.

The electrode protection layer 18 is formed by printing on the address electrode 17 by using a printing method such as a screen printing method and then firing the same, and is formed of the same glass as the dielectric glass layer 13. The composition is a thin film containing titanium oxide particles.

The partition wall 19 is formed by applying a partition wall forming material by a method such as a screen printing method, a lift-off method, or a sand blast method, baking it, and then processing the top of the partition wall. .

The phosphor layer 20 is formed by a method such as a screen printing method and a nozzle spraying method. Note that three colors of red, green, and blue are used for the phosphor.

(Panel bonding) Next, the front panel P
A1 and rear panel PA2 are positioned such that scanning electrodes 12a and sustain electrodes 12b and address electrodes 17 are orthogonal to each other, and both panels are attached to each other. Thereafter, a discharge gas (for example, He-X) is introduced into a discharge space 30 partitioned by the partition wall 19.
e-type, Ne-Xe-type inert gas) is sealed at a predetermined pressure.

As shown in FIG. 4, the PDP manufactured as described above has an address driver 220 and a scan electrode driver 23.
0, the sustain electrode driving unit 240 is connected to the address electrode 1
7 is grounded (GND), and the scanning electrode 12b and the sustain electrode 12
An aging process is performed by alternately applying a voltage to b in a predetermined cycle.

[0056]

As described above, according to the present invention, a plurality of pairs of first and second electrodes arranged in stripes are arranged in parallel, and furthermore, the plurality of pairs of electrodes are insulated. A plasma display panel in which a first substrate covered with a body layer and a second substrate on which third electrodes are arranged in a stripe shape are opposed to each other with a partition wall interposed therebetween. A whisker structure is present in at least a part of the surface layer of the dielectric layer or at least a part of the surface layer of the dielectric protective film further covering the dielectric.

Thus, in the surface layer of the dielectric layer,
The electric field intensity due to the applied voltage increases, and the amount of electrons emitted toward the discharge space increases. As a result, trigger electrons for the address discharge and the sustain discharge are easily released, so that the discharge delay at the time of the address discharge and the sustain discharge can be suppressed, and the response of the occurrence of the discharge to the voltage application can be improved. A good image can be displayed.

[Brief description of the drawings]

FIG. 1 is a partial perspective view showing a plasma display panel according to an embodiment.

2A is a vertical cross-sectional view including the line AA ′ in FIG. 1. FIG. 2B is an enlarged view of a whisker portion.

FIG. 3 is a partial perspective view showing a conventional plasma display panel.

FIG. 4 is a block diagram showing a common connection state between a plasma display panel and a driving circuit in the related art and the present invention.

FIG. 5 is a time chart showing a driving waveform of a plasma display panel common to the conventional and the present invention.

[Explanation of symbols]

PA1 Front panel PA2 Back panel 1 AC surface discharge type plasma display panel (PD
P) 11 Front glass substrate 11a Surface 12a Scan electrode 12b Sustain electrode 12c Discharge gap 13 Dielectric glass layer 14 Dielectric protection layer 14a Underlayer 14b Whisker portion 16 Back glass substrate 17 Address electrode 18 Electrode protection layer 19 Partition 20 Phosphor layer Reference Signs List 30 discharge space 220 address electrode driver 230 scan electrode driver 240 sustain electrode driver

Continuing on the front page (72) Inventor Koichi Kodera 1006 Kadoma, Kazuma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F-term (reference) 5C027 AA07 5C040 FA01 FA04 GB03 GB14 GE01 GE02 GE07 MA12 MA17 5C058 AA11 AB06 BA02 BA35

Claims (9)

[Claims] A first electrode in which a plurality of pairs of first and second electrodes arranged in a stripe are arranged in parallel, and the plurality of pairs of electrodes are covered with a dielectric layer. A plasma display panel in which a substrate and a second substrate on which third electrodes are arranged in a stripe shape are arranged to face each other with a partition wall interposed therebetween, wherein a surface layer of the dielectric layer;
Alternatively, a plasma display panel characterized in that at least a part of a surface layer of a dielectric protective film further covering the dielectric has a whisker structure. 2. The plasma display panel according to claim 1, wherein the whisker portion is formed of the same element as the protective film. 3. The plasma display panel according to claim 1, wherein the whisker portion is made of magnesium oxide. 4. The whisker portion has a diameter of 0.1 to 2.
The plasma display panel according to claim 1, wherein the thickness is 0 µm. 5. The plasma display according to claim 1, wherein the whisker portion is formed by a thermal chemical vapor deposition method or a plasma chemical vapor deposition method using an organometallic compound of magnesium and oxygen. panel. 6. The plasma display panel according to claim 1, wherein an underlayer is formed between the dielectric layer and the protective film. 7. The plasma display panel according to claim 1, wherein the surface layer of the underlayer or at least a part of the surface layer of the protective film has a whisker structure. 8. An element belonging to Group 2a of the periodic table,
2. The plasma display panel according to claim 1, wherein at least one of a group b element and a transition metal is included. 9. The method according to claim 1, wherein the underlayer is a (110) plane or a (1) plane.
(00) The plasma display panel according to claim 1, wherein the panel is oriented.