JP2002344548A - Data transmitter-receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transmitter-receiver which is improved in error correction performance, taking advantage of the reliability of determination at demodulation corresponding to bit mapping in higher order QAM. SOLUTION: An error correction encoder 2 enables input bit strings to undergo an error correction encoding process, and the bit strings subjected to the process are outputted as sorted out corresponding to their conduciveness to error correction characteristics. A higher order QAM modulator 4 outputs so as to map bit strings having high conduciveness to error correction characteristics onto signal points of high judgement reliability in demodulation and bit strings having low conduciveness to error correction characteristics onto signal points of low judgement reliability in demodulation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique of performing error correction coding on data and performing quadrature amplitude modulation (QA) of 16 or higher order.
M) Regarding the data transmission device / reception device transmitted and received in
In particular, the present invention relates to an apparatus that uses turbo coding as error correction coding.

[0002]

BACKGROUND OF THE INVENTION As is well known in the art, Q
AM refers to a digital modulation method obtained by adding two bipolar ASK (amplitude shift keying) signals having carrier phases different by (π / 2) radians. The signal space constellation of QAM is a lattice-like two-dimensional signal constellation composed of in-phase and quadrature components. The two-dimensional signal constellation is also called a data point constellation, and represents a state of amplitude and phase that a transmission symbol can take on a two-dimensional plane. When each component consists of k bits, each QAM code has an information amount of 2k bits. At this time, the signal point is 2
^The number becomes ^2k , forming 2 ^{2 k-} QAM.

[0003] In other words, QAM indicates a state by a combination of amplitude and phase and conforms to two conditions of high efficiency and high speed operation. Therefore, QAM is applied to a digital microwave communication system for relay transmission. Used. QAM is expressed as follows as a signal s (t) obtained by amplitude-modulating two carrier waves cosΩct and sinΩct having a phase difference of 90 ° from each other.

S (t) = i (t) cosΩct−q (t) sinΩct Here, i (t) and q (t) indicate independent signal waves, respectively. In digital communication, i (t) and q (t) are basically multi-level modulated signals having discrete levels for each divided time slot, and usually i (t) and q (t) The matching time slots are used. Note that i (t) is called an in-phase component and q (t) is called a quadrature component.

[0005] On the other hand, in order to correct a bit error occurring during data transmission, an error correction technique is generally employed. Here, error correction refers to a method of recovering a bit error when the bit error is detected in data received from a communication line. If the data to be transmitted (to be transmitted) is encoded using an error correction code, the error bit can be corrected to a correct bit on the receiving side. An error correction code refers to a code having a function of automatically correcting this bit error, and it is common to add a redundant code for correction to original data.

As described above, a data transmitting apparatus and a receiving apparatus which perform error correction coding on data and transmit / receive data by using quadrature amplitude modulation (QAM) of 16 or higher order generally have the following configuration. have. That is, the data transmitting apparatus performs error correction coding on input data (input bit sequence) and outputs an error correction coded bit sequence, and uses the error correction coded bit sequence to perform QAM on the two carriers. And a higher-order QAM modulator for performing modulation. On the other hand, the data receiving apparatus is composed of a higher-order QAM demodulator that outputs a QAM-demodulated signal by QAM demodulating the received multi-level modulated signal, and an error correction decoder that corrects a bit error of the QAM-demodulated signal. ing.

As described above, in this type of conventional data transmitting / receiving apparatus, when one-bit bit sequence is subjected to error correction coding and transmitted using QAM (Quadrature Amplitude Modulation), generally, error correction is performed. The subsequent bit string is directly mapped to a QAM signal point and transmitted.

Further, there is known a prior art document in which the error correction capability of an error correction code of a bit string to be mapped is changed according to mapping of a signal point of multi-level QAM.

For example, Japanese Unexamined Patent Publication No. 59-23946 (hereinafter referred to as “first prior art document”) discloses that a transmitting side performs error correction coding and QAM modulation according to an error occurrence probability. A “error correction method for digital signal transmission” is disclosed in which a receiving side decodes in accordance with error correction coding on a transmitting side. In addition, Japanese Unexamined Patent Application Publication No.
Japanese Patent No. 288752 (hereinafter referred to as "second prior art document") discloses a "multi-level QAM communication system" in which the redundancy of an error correction code is changed according to a bit error rate. I have. Further, Japanese Patent Laid-Open Publication No. Hei 8-116341 (hereinafter referred to as "third prior art document") discloses a "digital modulation device and demodulation device" in which the error correction capability for burst errors is improved. ing.

Japanese Patent Laid-Open Publication No. Hei 8-163085 (hereinafter referred to as “fourth prior art document”) discloses that a transmitting side divides and encodes a plurality of streams to perform multi-level modulation.
On the receiving side, an “information communication device” that demodulates and decodes a multi-level modulated code sequence is disclosed. Furthermore,
In Japanese Patent Publication No. 7-95762 (hereinafter referred to as "fifth prior art document"), an uncoded signal is arranged at a signal point having a good error rate characteristic, and a signal point having a bad error rate characteristic is arranged. "Multi-level QAM communication system" in which coded signals are arranged
Is disclosed.

[0011]

Problems to be Solved by the Invention Higher order Q of 16 or higher order
In the AM, a difference occurs in “decision reliability” at the time of demodulation between bits according to mapping. Hereinafter, the “determination reliability” at the time of demodulation in 16-level QAM and 64-level QAM will be specifically described.

FIG. 4 is a diagram showing a data point arrangement of 16-level QAM. In FIG. 4, the horizontal axis represents the in-phase component i (t), and the vertical axis represents the quadrature component q (t). In this example, since 16-level QAM, k is 2, the in-phase component i (t) is composed of 2 bits i ₁ and i ₂ , and the quadrature component q (t) is 2 bits of q ₁ and q ₂ Consists of At this time, the signal point is i ₁ q ₁ i ₂ as shown in FIG.
represented by 4 bits of q _2. That is, the most significant bit (MSB) is i _{1, 1} 2 th bits q, 3-th bit i _2, the least significant bit (LSB) is q _2.

More specifically, the most significant bit i ₁ is an in-phase component
A bit indicating whether i (t) is positive or negative. If it is positive, its value is logic "0"; if it is negative, its value is logic "1". Therefore, when the signal point is in the first quadrant and the fourth quadrant, the upper bits i ₁ top is a logic "0", when the signal point is in the second quadrant and the third quadrant, the upper bits i ₁ most logical It is "1". Second bit q ₁ is a quadrature component q (t) is a bit indicating whether positive or negative, positive if the value is a logical "0", the value for negative is a logic "1". Thus, when the signal point is in the first and second quadrants, the second bit q ₁ is logic “0”, and when the signal point is in the third and fourth quadrants, the second bit q ₁ Is logical "1". The third bit i ₂ is a bit indicating whether the absolute value of the in-phase component i (t) is larger or smaller than 0.5. When the absolute value is smaller than 0.5, the value is logic “0”. It is logic "1". Similarly, the least significant bit q ₂ is the orthogonal component q
This bit indicates whether the absolute value of (t) is larger or smaller than 0.5. When the absolute value is smaller than 0.5, the value is logic “0”,
If greater, the value is a logical "1". Note that in the example shown in FIG. 4, the signal point is represented by the in-phase component i (t) and the quadrature component q.
(t), the absolute values are 0.3162 and 0.9487.
Has the value of

As described above, in the case of 16-value QAM, the most significant bit i ₁ and the second bit q ₁ need only determine whether the signal point is positive or negative on each orthogonal axis. However, the third bit i ₂ and the least significant bit q ₂ must be determined by comparing the value of the signal point to 0.5. As a result, compared to the most significant bit i ₁ and the second bit q ₁ ,
The “decision reliability” of the second bit i ₂ and the least significant bit q ₂ is inferior.

FIG. 5 is a diagram showing the arrangement of data points of 64-value QAM. In 64-value QAM, the "determination reliability" has three levels as described later. In FIG. 5, the horizontal axis represents the in-phase component i (t), and the vertical axis represents the quadrature component q (t). In this example, since 64-value QAM, k is 3, the in-phase component i (t) is composed of three bits i ₁ , i ₂ , and i ₃ , and the quadrature component q (t) is q ₁ , q _2, and it consists of 3 bits of q _3. At this time, as shown in FIG. 5, the signal point is 6 of i ₁ q ₁ i ₂ q ₂ i ₃ q ₃ .
Expressed in bits. That is, the most significant bit (MS
B) is at i _1, 2 th bit is q _1, the third bit
In i _2, the fourth bit q _2, the fifth bit i _3,
The least significant bit (LSB) is q _3.

More specifically, the most significant bit i ₁ is an in-phase component
A bit indicating whether i (t) is positive or negative. If it is positive, its value is logic "0"; if it is negative, its value is logic "1". Therefore, when the signal point is in the first quadrant and the fourth quadrant, the upper bits i ₁ top is a logic "0", when the signal point is in the second quadrant and the third quadrant, the upper bits i ₁ most logical It is "1". Second bit q ₁ is a quadrature component q (t) is a bit indicating whether positive or negative, positive if the value is a logical "0", the value for negative is a logic "1". Thus, when the signal point is in the first and second quadrants, the second bit q ₁ is logic “0”, and when the signal point is in the third and fourth quadrants, the second bit q ₁ Is logical "1". The third bit i ₂ is a bit indicating whether the absolute value of the in-phase component i (t) is greater than or less than 0.6. When the absolute value is less than 0.6, the value is logic “0”. It is logic "1". Similarly, the fourth bit q ₂ is the orthogonal component
This bit indicates whether the absolute value of q (t) is greater than or less than 0.6.
If greater, the value is a logical "1". The fifth bit i _3, the absolute value of the in-phase component i (t) is between 0.3 and 0.9, a bit indicating a 0.3 or smaller or larger than 0.9, when it is between 0.3 and 0.9 that The value is logic "0",
If it is less than 0.3 or greater than 0.9, its value is a logical "1". Similarly, the least significant bit q ₃ is the orthogonal component q
This bit indicates whether the absolute value of (t) is between 0.3 and 0.9, smaller than 0.3, or larger than 0.9. When it is between 0.3 and 0.9, the value is logic "0" and smaller than 0.3. Otherwise, if greater than 0.9, the value is a logical "1".
In the example shown in FIG. 5, the absolute value of the signal points of the in-phase component i (t) and the quadrature component q (t) is 0.154 and 0.46, respectively.
It has values of 3, 0.771, and 1.08.

As described above, in the case of 64-level QAM, the most significant bit i ₁ and the second bit q ₁ need only determine whether the signal point is positive or negative on each orthogonal axis. However, the third bit i ₂ and the fourth bit q ₂ must be determined by comparing the value of the signal point with 0.6, and furthermore, the fifth bit i 3 and the least significant bit q 3 Judgment must be made by comparing the point value to 0.3 and 0.9. As a result, compared to the most significant bit i ₁ and the second bit q ₁ ,
"Decision reliability" of the i-th bit i ₂ and the fourth bit q ₂
Is inferior, and the third bit i ₂ and the fourth bit q ₂
, The “judgment reliability” of the fifth bit i ₃ and the least significant bit q ₃ is inferior.

As is generally practiced, the bit string after error correction is directly mapped to QAM signal points, so that the "determination reliability" at the time of demodulation is not used.

As described above, the first to fifth prior art documents disclose a method for changing the error correction capability of error correction coding of a bit string to be mapped according to mapping of signal points of multi-level QAM. Although it is disclosed,
There is no disclosure or suggestion of using “judgment reliability” during demodulation.

Accordingly, it is a main object of the present invention to provide a data transmitting apparatus and a receiving apparatus in which the error correction capability is improved by utilizing the determination reliability at the time of QAM demodulation.

[0021]

The present invention employs the following technical structure to achieve the above object.

That is, a data transmitting apparatus according to the present invention includes an error correction encoder for performing error correction coding on an input bit sequence, and dividing and outputting the bit sequence as a result of processing according to the degree of contribution to the error correction characteristic. , The bit string output by the error correction coding unit, a bit string having a high contribution to the error correction characteristic is a signal point having high determination reliability during demodulation, and a bit string having a low contribution is a signal point having a low determination reliability during demodulation. And a high-order QAM modulator for mapping and outputting points.

In QAM modulation, a bit sequence having a high contribution to the error correction characteristic is mapped to a signal point having a high determination reliability at the time of demodulation. Can be expected to be able to demodulate with high reliability, and therefore the error correction capability can be improved.

A data receiving apparatus according to the present invention determines a signal point for a received multi-level modulation signal, and divides each bit of a bit pattern corresponding to the signal point into a bit string according to the determination reliability of each bit. A high-order QAM demodulator to be output and an error correction decoder to calculate and output an error-corrected bit sequence from the bit sequence output by the high-order QAM demodulator are provided.

The Q transmitted by the data transmitting apparatus according to the present invention
A bit string having a higher contribution to the error correction characteristic than the AM signal can be demodulated with high reliability, and thus the error correction capability can be improved.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to clarify the above and other objects, features and advantages of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, there is shown a data transmitting apparatus according to an embodiment of the present invention. The data transmitting apparatus includes an error correction encoder 2 and a higher-order QAM modulator 4.
And

The error correction coder 2 performs error correction coding on the input bit string input from the coded input signal line 1, and then, according to the importance of each output bit, outputs the first bit in descending order of importance. From the encoded output signal line 3-1 to the n-th encoded output signal line 3-n. Here, "importance"
This refers to the degree of contribution of each bit to the error correction characteristics (ability). Here, n is an integer of 2 or more.

The high-order QAM modulator 4 converts the bit string input from the first coded output line 3-1 through the n-th coded output line 3-n into importance (degree of contribution to error correction characteristics). Bits with a high value are mapped to signal points with high decision reliability during demodulation, and bits with low importance are mapped to signal points with low decision reliability during demodulation, and output from the modulation output signal line 5.

The output signal of the high-order QAM modulator 4 is sent to a data receiving device (FIG. 2) through a transmission line (not shown).

FIG. 2 shows a data receiving apparatus according to an embodiment of the present invention. This data receiving apparatus includes a high-order QAM demodulator 7 and an error correction decoder 9.

The high-order QAM demodulator 7 determines the signal point of the multilevel modulated signal input from the demodulation input line 6,
Each bit of the bit pattern corresponding to the signal point is output from the first demodulation output line 8-1 to the n-th demodulation output line 8-n in descending order of reliability according to the determination reliability at the time of demodulation.

The error correction decoder 9 is connected to the first demodulation output line 8
-1 to a bit string after error correction is calculated from the bit string input from the n-th demodulation output line 8-n, and the decoded output line 10 is calculated.
Output to

The operation of this embodiment will be described below.

First, the operation of the error correction encoder 2 will be described.

FIG. 3 is a diagram showing a configuration example of a turbo encoder having a coding rate of 1/3, which is used as the error correction encoder 2. Since the turbo encoder 2 is well known to those skilled in the art, and the configuration itself is not directly related to the present invention, a detailed description thereof will be omitted.

The outline of the turbo code will be described below. The turbo code is a combination of a plurality of convolutional codes. 3 has a turbo code inner interleaver 20 and first and second systematic encoders 21 and 22. The turbo encoder 2 shown in FIG. First
Outputs the first parity bit Z _k ,
Second tissue encoder 22 outputs the second parity bits Z _'k.

That is, the turbo encoder having a coding rate of 1/3 outputs the input bit string (X _k ) as it is and also outputs the same number of first and second parity bits (Z _k ,
Z ' _k ). A bit string output as an input bit string as it is has a higher degree of importance (contribution) to the error correction capability (characteristic) than two parity bit strings.

Therefore, the error correction encoder 2 according to the present invention outputs the input bit string (X _k ) to the first coded output line 3-1 and outputs the first and second parity bits (Z _k , Z ′). _k ) are output to a second encoded output line 3-2 and a third encoded output line 3-3, respectively. In this case, the second encoded output line 3
-2 and the third encoded output line 3-3 have the same importance.

Next, the operation of the high-order QAM modulator 4 will be described.

The higher-order QAM is 16-level QAM, and the input lines are a first encoded output line 3-1 and a second encoded output line 3
Let it be -2. In this case, the bits X _k and Z _k input at time k from the first encoded output line 3-1 and the second encoded output line 3-2, and the bit input at time k + 1 X
_{k + 1} and Z _{k + 1} , for example, bit X _k is the most significant bit i ₁ ,
Bit X _{k + 1} the second bit q _1, the bit Z _k in the third bit i _2, bits Z _{k +1} is mapped to the least significant bit q _2.

The lines input as described above are the first to third lines.
Are coded output lines 3-1 to 3-3. In this case, input bit strings (X _k , X _{k + 1} , X _{k + 2} , X _{k + 3} , Z _k , Z _{k + 1} , Z _{k + 2} , Z _k) at four times from time k to k + 3 _{k + 3} , Z ' _k ,
Z ′ _{k + 1} , Z ′ _{k + 2} , Z ′ _{k + 3} ), for example, bits X _k , X
_{k + 1} and X _{k + 3} to the most significant bit i ₁ and bits Z _k , X _{k + 2} and Z ' _{k + 2}
To the second bit q _1, bit Z _'k, Z' to _{k + 1,} Z _{k + 3} the third bit i2, bits _{Z k + 1, Z k +} 2, the Z'k + 3 top respectively mapped to the lower bit q _2. The mapping may be in a format different from that shown here, but the bit string X _k input from the first encoded output line 3-1 is the most significant bit i ₁ having a high determination reliability at the time of decoding. Or the second bit
q Map to ₁ .

It is assumed that the higher-order QAM is a 64-level QAM, and three input lines are first to third encoded output lines 3-1 to 3-3. In this case, for an input bit string (X _k , X _{k + 1} , Z _k , Z _{k + 1} , Z ′ _k , Z ′ _{k + 1} ) at two times _k and _{k + 1} , for example, the bit X _k , X _{k + 1} , Z _k , Z _{k + 1} , Z ' _k , Z'
_{k + 1} is replaced by the most significant bit i ₁ and the second bit q ₁ , 3
Bit i ₂ , least significant bit q ₃ , fifth bit i ₃ , 4
Map to the second bit q2. The mapping may be in a format different from that shown here. However, the bit string X _k input from the first encoded output line 3-1 has the most significant bit i ₁ , which has high determination reliability at the time of decoding. Or the second bit
q Map to ₁ .

It should be noted that the present invention is not limited to the above-described embodiment, but can be appropriately modified without departing from the gist of the present invention. For example, in the above-described embodiment, a turbo encoder is shown as an example of the error correction encoder. However, it goes without saying that the error correction encoder is not limited to this.

[0045]

As described above, according to the present invention,
The error correction encoder performs error correction encoding on the input bit sequence, divides and outputs the bit sequence of the processing result according to the contribution to the error correction characteristic, and the high-order QAM modulator
The bit string output by the error correction encoder is converted to a signal point having a high degree of determination reliability at the time of demodulation for a bit string having a high contribution to the error correction characteristic, and a signal point having a low determination reliability at the time of demodulation for a bit string having a low contribution. Based on the basic configuration of mapping and outputting the data, a data transmission device / reception device is provided that has improved error correction capability by utilizing the determination reliability at the time of QAM demodulation.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data transmission device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a data receiving device according to one embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration example of a turbo encoder used as an error correction encoder used in the data transmission device of FIG. 1;

FIG. 4 is a diagram showing an arrangement of signal points of 16-level QAM.

FIG. 5 is a diagram showing an arrangement of signal points of 64-level QAM.

[Explanation of symbols]

 2 error correction encoder 4 high-order QAM modulator 7 high-order QAM demodulator 9 error correction decoder

Claims (8)

[Claims] An input bit sequence is subjected to error correction coding,
An error correction encoder that divides the bit string of the processing result according to the degree of contribution to the error correction characteristic and outputs the divided bit string; Is characterized by comprising a high-order QAM modulator which maps to a signal point having high determination reliability at the time of demodulation and a bit string having low contribution to a signal point having low determination reliability at the time of demodulation and outputs the signal. Data transmission device. 2. The high-order QAM modulator, wherein a modulation scheme is 1
2. A bit string which is 6-value QAM and has a high degree of contribution to error correction characteristics is mapped so as to be represented by signal points separated by orthogonal axes of 16-value QAM.
A data transmission device as described in the above. 3. The high-order QAM modulator, wherein the modulation scheme is 6
2. A bit string which is quaternary QAM and has a high degree of contribution to error correction characteristics is mapped so as to be represented by signal points separated by orthogonal axes of 64-value QAM.
A data transmission device as described in the above. 4. The error correction encoder according to claim 1, wherein an error correction encoding method is turbo encoding, and a bit sequence for outputting an input bit sequence as it is is more contributing to error correction characteristics than a parity bit sequence of turbo encoding. 2. The data transmission device according to claim 1, wherein the data transmission device has a high bit sequence. 5. The high-order QAM modulator, wherein a modulation scheme is 1
5. The method according to claim 4, wherein a bit string that is a six-value QAM and has a high degree of contribution to error correction characteristics is mapped so as to be represented by signal points separated by orthogonal axes of the sixteen-value QAM.
A data transmission device as described in the above. 6. The high-order QAM modulator, wherein a modulation scheme is 6
5. A bit sequence which is quaternary QAM and has a high degree of contribution to error correction characteristics is mapped so as to be represented by signal points divided by orthogonal axes of 64-level QAM.
A data transmission device as described in the above. 7. A high-order QAM demodulator that determines a signal point of a received multi-level modulation signal, and outputs each bit of a bit pattern corresponding to the signal point in a bit sequence according to the determination reliability of each bit. A data receiving device comprising: a decoder; and an error correction decoder that calculates and outputs an error-corrected bit sequence from the bit sequence output by the higher-order QAM demodulator. 8. When an error correction is applied to an input bit string and a bit string after the error correction has a different contribution to the error correction capability depending on the bit, a multi-valued Q is determined according to the contribution.
A data transmission method characterized by changing a mapping of an AM to a signal point.