JP2002342114A - Processor capable of collecting trace data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processor capable of accurately and easily collecting an instruction trace (data). SOLUTION: This processor is provided with a trace buffer 18 for storing and holding trace data of an instruction block of a performed program, a PC 14 for storing and holding a current PC value being a value of a program counter used in an instruction fetch cycle of this time, a preceding PC 15 for storing and holding the preceding PC value being the value of the PC 14 used in the preceding instruction fetch cycle, a branch decision processing part 16 for deciding to be a branch occurrence if the difference between the current PC value and the preceding PC value does not coincide with a fixed instruction length with the instruction fetch of this time as a branch decision trigger and generating a collection trigger signal, and a data collection processing part 17 for receiving the collection trigger signal, collecting the preceding PC value and the current PC value as a branch source address and a branch destination address respectively and storing the preceding PC value and the current PC value in the trace buffer 18, detects a branch occurrence on the basis of change of a value of the PC 14 and collects trace data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor capable of collecting trace data, and more particularly, to an execution profile of a predetermined program (extracted from data obtained by tracing the execution of a program according to the purpose of use). Creation of program execution history data), performance optimization (improvement of programs), failure investigation, debugging, and collection of trace data of program execution history as basic information used for various simulations in hardware and software development A possible processor.

[0002]

2. Description of the Related Art First, some terms used in the present specification will be defined. In this specification, the entire control transfer of instruction execution due to all factors such as a branch instruction and an interrupt is referred to as “branch” (branch in a broad sense). On the other hand, only control transfer by a branch instruction is called "branch".
(Branch in a narrow sense).

On the processor, a block unit of an instruction sequence linearly executed on a program code from a branch destination instruction in a certain branch to a branch source instruction executed from the next branch to the next branch is referred to as an “instruction block”. Call. Note that a branch destination may come in the middle of this instruction block. Although the term “basic block” is used in the same definition, it is common that this basic block does not include a branch destination in the middle.

The prior art of a processor from which trace data can be collected will be described below. Traditionally, most processors have tweaked program code,
As a processor that can collect trace data of program execution history without additional dedicated hardware, trace data collection (hereinafter simply referred to as data collection) by giving an interrupt to the trace data collection software for each execution instruction If data is collected for each processor or execution instruction, the overhead will be large. To reduce this overhead, interrupt the data collection software not for each execution instruction but for each branch by a branch instruction, that is, for each instruction block. To collect data.

Further, in order to further reduce overhead, a conventional processor has a plurality of branch instructions (branches) provided with a function of buffering a plurality of collected data without interrupting each time at a collection timing. There was a processor that gave an interrupt every time. For example, In
tel's Itanium processor is Taken
A Branch Trap (taken branch trap) function is provided, and IIPA (Interr) is used as a dedicated register for recording instruction addresses of a branch source and a branch destination.
uption Interaction Previo
us Address: address before interrupt instruction) and II
P (interrupt instruction pointer, ie address after interrupt instruction)
Are provided.

[0006] This processor also has Take in the register of the PSR (processor status register).
A flag for controlling n Branch Trap from predetermined software is provided. By setting this flag to ON, the instruction address of the branch source / branch destination is recorded in each of the above-described dedicated registers every time a branch is executed. The software is interrupted.

At this time, a branch trigger for recording data in a register and raising an interrupt is only a branch as a branch by a branch instruction, and a branch due to other factors such as an interrupt is not recorded. Also, other conventional processors, such as Intel's Pentium Pr
o In addition to the functions equivalent to the above, the processor has a function of recording the address of the branch source / destination even at the time of control transfer of instruction execution due to an interrupt or an exception, and a function of raising an interrupt to data collection software. . However, between a branch by a branch instruction and a branch by an exception such as an interrupt, IIPA (InterruptionIntera) is used.
two sets of registers each corresponding to a Ction Previous Address (address before an interrupt instruction) and an IIP (interrupt instruction pointer) are provided independently.
The recording method and recording location of the target data are different. That is, when an interrupt occurs, the trace collection software determines whether the branch is a branch by a branch instruction or a branch by an exception such as an interrupt.
The instruction address of the branch destination / branch source from one of the two register pairs corresponding to IPA must be recorded.

[0008]

FIG. 9 is a diagram showing an example of an execution program for explaining the problem of trace data collection according to the prior art. In the example shown in FIG. 9, the correct history of the executed program is A1-B1-B2-
A2 (where A1, A2, B1, and B2 indicate instruction blocks). That is, From1-To1-A1-F
rom2-To2-B1-From3-To3-B2-
From4-To4-A2-From5-To5 (where From1 to From5 and To1 to To5 indicate addresses) is a correct program execution history. In order to generate this execution history, From1-To1, Fr
om2-To2, From3-To3, From4-T
The trace data of the branch source-destination of five pairs of o4 and From5-To5 must be correctly collected. However, the prior art has the following problems.

In a conventional processor typified by the above-described Itanium, an erroneous execution profile is created by simply analyzing trace data collected due to an interrupt or the like other than a branch instruction (branch). I had to do something with the software. For example, in a system where trace data is being collected, an interrupt is generated during the execution of a program running on that system, and execution control is interrupted from the middle of the program by examining the cause of the interrupt to the hardware. (A program prepared in an OS that operates in response to the interrupt handler), since the branch at the moment when the process proceeds to the interrupt handler is not recorded, the trace data is stored as From1-To1, From3.
Trace data of three pairs of branch source and branch destination of -To3 and From5-To5 are collected. That is, To1-Fr
An abnormal instruction block such as om3 or To3-From5 is created.

That is, if an execution profile is simply created from the trace data, if the OS service section is located at a lower address of the storage section than the main thread section, an abnormally long linear continuous execution block is generated. If the section is at a higher address of the storage section than the main thread section, there is a possibility that an erroneous instruction block appears such that a continuous execution block in the direction of decreasing PC is generated (it cannot actually occur). To avoid
The software, that is, the trace data collection program (list of raw data and the collection order of instruction addresses) and the analysis program (execution profile data) had to deal with some kind of coordination.

[0011] Further, even in a conventional processor which also supports a branch caused by an interrupt or an exception as represented by the above-mentioned Pentium Pro, the recording method at the time of branching is different between a branch by a branch instruction and a branch by an interrupt or an exception. Because of the difference, it was not possible to simply create an accurate execution profile from the trace data, and it was necessary for software to deal with this, as in the case of the Itanium processor.

Therefore, according to the present invention, no special measures need to be taken by software such as a trace data collection program and an analysis program, and more accurate trace data can be collected as compared with the related art. It is another object of the present invention to provide a processor capable of executing data analysis and profile creation more easily.

[0013]

A processor capable of collecting trace data according to the present invention, which achieves the above object, has a trace buffer for storing and holding trace data of an instruction block of an executed program, and a trace buffer used in the present instruction fetch cycle. Current PC which is the value of the program counter PC
In a processor capable of collecting trace data, comprising a program counter PC for storing and holding a value, a change in the value of the program counter PC, not the branch instruction itself, is used to determine whether or not a branch has occurred and to determine whether or not a branch has occurred. It is characterized by being used as a trigger.

With the above configuration, the software for collecting or analyzing the trace data does not need to take any special measures. The processor may also include the program counter PC used in a previous instruction fetch cycle.
And a previous PC value holding unit that stores and holds a previous PC value that is a value of the current PC value and the previous PC value in synchronization with the cycle of the instruction fetch using the current instruction fetch as a branch determination trigger. When the difference does not match the fixed instruction length, it is determined that a branch has occurred, a branch determination processing unit that generates a collection trigger signal for collecting trace data, and receives the collection trigger signal, and receives the previous PC value and the A data collection processing unit that collects a current PC value as a branch source address and a branch destination address in pairs, stores the pair in the trace buffer, and generates a collection completion notification signal after the collection is completed;
Is provided.

In the above-mentioned branch determination processing unit, it is observed whether or not the PC value changes irregularly (decrease or discontinuity) at each instruction fetch cycle, and it is determined that a branch has occurred. In this case, a trigger signal to execute the collection is sent to the data collection processing unit. The data collection processing unit to which the collection signal has been sent collects each address data of the branch source and the branch destination and stores them in the trace buffer. Accordingly, since a point where the execution of the instruction sequence is not linearly executed is used as a trigger for collecting data, it is possible to collect trace data that is more accurate and can be easily used from software.

The processor also enables the branch determination trigger signal sent from the instruction fetch unit that retrieves and temporarily stores an instruction written to a memory address indicated by the value of the program counter to the branch determination processing unit. And a control flag for controlling whether to invalidate. The control flag is a trace control flag of an instruction block that can be set from software, and thereby control of start / stop of collection of trace data can be made from software in hardware as well as from software.

The processor may further include a previous instruction length holding unit that stores and holds a previous instruction length decoded in a previous instruction decode cycle (an instruction fetched in a fetch cycle). The instruction length is used as the instruction length for branch determination for determining whether a branch is taken. By providing the previous instruction length holding unit and using it as the instruction length for branch determination, trace data processing can be applied to a processor of a variable length instruction.

In the above processor, the branch determination processing unit may include an instruction address that is out of the instruction cache when the difference between the current PC value and the previous PC value exceeds the instruction cache size. And a cache use monitoring unit that generates a trigger signal for collecting trace data. By providing the cache use monitoring unit and determining whether or not the difference between the current PC value and the previous PC value is equal to or larger than the instruction cache size, it is possible to catch a branch that is wasting the cache and causing a waste. The prospect of the place where the performance of the executed program is improved can be set. Further, by performing the statistical processing, the effective utilization rate of the instruction cache can be measured.

The data processor may be configured to determine whether or not the trace buffer has become full with the trace data every time buffering is completed, and to detect that the trace buffer has become full. A buffer full detection unit for notifying the software of an interrupt and turning off the control flag. By providing the buffer full detection unit and the control flag for trace data collection, once the trace buffer becomes full, the trace data is temporarily stored and stored in the data collection area in the formal storage device, and the trace data is stored again. By turning on a control flag for collecting trace data, it is possible to start collecting trace data. This allows
Actually, trace data is collected in an arbitrary trace section and in an arbitrary data size. However, it is possible to continuously and unlimitedly collect trace data.

[0020]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. First, a first embodiment of the present invention will be described below. FIG. 1 is a block diagram of a processor capable of collecting trace data according to the first embodiment of the present invention. FIG. 1 shows that in a processor having a fixed instruction length, it is determined whether or not a change in the value of PC is irregular, and if it is determined to be irregular, a trigger is generated and trace data (branch source and branch (Each of the above addresses).

The main components are as follows. Fixed length setting unit 10: A register for storing the instruction length in a processor whose instruction length to be executed has a fixed length L. Storage device 11: a main storage (memory) or cache that stores and holds instructions and data. A cache is often used as the storage device 11 in recent processors.

Instruction fetch & decode unit 12 fetches an instruction from the storage device 11 (instruction fetch) and decodes the fetched instruction. This decoding will be described later. Executing unit 13 executes an operation specified by the operation code. PC14: Program counter. A register for designating a storage destination address of a next instruction to be executed in the storage device, and holds the address.

The above components are the basic components of the instruction execution processing which are usually provided in a normal processor.
Hereinafter, the instruction flow between these elements, that is, the repetition of a series of instruction execution processes will be referred to as an “instruction cycle”. Next, the components mainly shown on the right side of FIG. 1 according to the first embodiment of the present invention will be described.

Previous PC 15... A previous PC holding unit which stores and holds the value of the program counter PC 14 used in the previous instruction fetch cycle. Branch determination processing unit 16: Upon receiving a trigger signal for branch determination synchronized with instruction fetch (indicated by a broken line), the PC 14
Is compared with the previous PC value stored in the previous PC 15, and the difference is the instruction length (fixed length L).
If it does not match, it is determined that a branch has occurred, and a collection trigger signal (indicated by a broken line arrow) is sent to the data collection processing unit 17. Also, every time the determination process is completed, the PC 14
(Overwrite copy) of the current PC value to In addition,
When a trace collection trigger signal is transmitted to the data collection processing unit 17, the shift processing is executed after waiting for a completion notification signal (indicated by a broken line) from the data collection processing unit 17.

Data collection processing unit 17: Abbreviation of trace data collection processing unit. Upon receiving the sampling trigger signal from the branch determination processing unit 16 described below, the previous PC value stored in the previous PC 15 and the current P
The C value is collected in pairs as a branch source address and a branch destination address, respectively, and stored in the trace buffer 18 including a memory or a register. Further, a completion notification signal is sent to the branch determination processing unit 16 when the collection is completed.

Selector 19: A fixed instruction length stored in the fixed length setting unit 10, a branch destination address in the first case (arrow A in FIG. 1) by execution of a branch instruction (branch) described later, and an interrupt factor. In the second case (arrow B in FIG. 1), a signal for selecting any one of the branch destination addresses is written to the PC 14. Next, an instruction cycle mainly shown on the left side of FIG. 1 will be described using these components.

FIG. 2 is a flowchart of an instruction cycle executed by the processor. The processor shown in FIG. 1 executes instructions one by one by repeatedly executing the processing described in the following steps S01 to S04 (the instruction cycle of a normal processor is basically the same). Step S01: Instruction fetch (instruction fetch) ... PC
An instruction to be executed next is read from a location (address) on the storage device 11 indicated by the content (value) of the instruction 14.

Step S02: Updating the PC ... The instruction length (fixed length L in this case) of the read instruction is added to the value of the PC 14 to obtain an instruction address to be read next. Step S03: Decode the instruction ...
The operation (instruction) code part for specifying the type of instruction and the operand (data to be operated) specification part are divided into operation code analysis and operand storage destination determination. The operation content of the instruction is determined by the operation code analyzed here. The operand storage destination includes a register (not shown) and the storage device 11, and in the latter case, the operand address is also calculated.

Step S04: Execution of an instruction designating operation, writing of a result, calculation of a branch destination address, etc. An operation according to the decoding result is performed. If necessary, operands are read and operation results are written into a register (not shown) or the storage device 11. In the case of a branch instruction (branch), if necessary, a test of a flag or the like is performed, and based on the result, a branch destination address is calculated.
Set to C14. After the execution of the processing from step S01 to step S04, the process returns to step S01.

In the above-described instruction fetch cycle, P is maintained until a series of trace data collection processing described later is completed.
The C value is not updated. By the way, the causes of the branch in the instruction cycle include a first case (arrow A in the figure) due to execution of a branch instruction (branch) and a second case (arrow B in the figure) due to an interrupt cause. is there. In the case of the second (arrow B), the process waits until the execution of the process of step S04 is completed, including a case where an interrupt from the outside of the processor is raised during the execution of the processes of steps S01 to S04. The value of the PC 14 is rewritten to the branch destination address of the interrupt (the top address of the interrupt handler). In the second case, immediately after the interruption, the value of the PC 14 is rewritten to the branch destination address of the interruption.

As described above, the timing of the occurrence of the interrupt includes the exception interrupt I1 when the error occurs during the execution of the instruction in the decode unit 12, the execution unit 1
3 is an exceptional interrupt I2 when an error occurs during the execution of the instruction, and two patterns of an external interrupt and an interrupt between instructions which are timings for processing a trap. In any case, when an interrupt occurs, the start address of each interrupt handler is set in the PC 14. The processor having the instruction block tracing function according to the present invention can cope with the occurrence of an interrupt at any given timing in the same manner.

FIG. 3 is a flowchart of the trace data collecting process by the processor capable of collecting trace data according to the first embodiment of the present invention shown in FIG. Step numbers S1 to S8 shown in FIG. 3 are indicated by encircling 1 to 8 in FIG. Step S1: A branch determination trigger signal for performing a branch determination is transmitted in synchronization with an instruction fetch for reading an instruction to be executed next from the storage device 11.

Step S2: Upon receiving the trigger signal for branch determination, the branch determination processing section 16 fetches the current PC value and the previous PC value from the PC 14 and the previous PC 15, respectively, and makes a comparison determination. Here, the subsequent processing is separated according to the comparison result. First, if the difference between the current PC value and the previous PC value does not match the instruction length (fixed length L), that is, if it is determined to be a branch, the process proceeds to step S3. If it is determined, the process proceeds to step S13 described below.

Step S3: If the branch determination processing section 16 determines that a branch has occurred, a trace data collection trigger signal is sent from the branch determination processing section 16 to the data collection processing section 17. Step S4: Upon receiving the trace data collection trigger signal, the data collection processing unit 17 collects the current PC value and the previous PC value from the PC 14 and the previous PC 15 in pairs.

Step S5: The data collection processing unit 17
After the collection of the current PC value and the previous PC value is completed, a completion notification signal is sent to the branch determination processing unit 16. Step S6: After the completion notification, the data collection processing unit 17
The current PC value and the previous PC value collected in step S4 are stored in the trace buffer 18 as a branch destination address and a branch source address, respectively. On the other hand, the branch determination processing unit 16
A trigger signal for shifting the value of PC14 is sent from C14 to the previous PC15.

Step S7: The current PC value is shifted (overwritten copy) from the PC 14 to the previous PC 15. Step S8: The value of the PC 14 is updated. Step S13: The PC 14 sends a trigger signal for shifting the value of the PC 14 to the previous PC 15 by the operation of the branch determination processing section 16 in the above step S6.

Next, a second embodiment of the present invention will be described below. FIG. 4 is a block diagram of a processor capable of collecting trace data according to the second embodiment of the present invention. As shown in FIG. 4, the processor capable of collecting trace data according to the second embodiment is obtained by adding a mechanism for enabling trace control to the processor according to the first embodiment of the present invention shown in FIG. is there. In FIG. 4, FIG.
The components added to the processor of the first embodiment shown in FIG.

Control flag section 20: A storage section for an instruction block / trace control flag. This control flag is sent out in synchronization with the instruction fetch, and enables or disables a trigger signal generated for performing branch determination. This is a flag for performing the control of With this control flag, it is possible to set whether to enable or disable the trace control of the instruction block, and the trace collection program (software) 21 can also start and stop the trace collection. Accordingly, in actual sampling, it is possible to use the trace by enabling the trace only for the instruction block portion to be sampled.

Next, a third embodiment of the present invention will be described below. FIG. 5 is a block diagram of a processor capable of collecting trace data according to the third embodiment of the present invention. As shown in FIG. 5, the processor capable of collecting trace data according to the third embodiment is different from the processor having the control flag unit 20 according to the second embodiment of the present invention shown in FIG. It adds a corresponding mechanism.

Pre-instruction length 31: A pre-instruction length holding unit provided in the branch judgment processing unit 30, and holds the instruction length decoded in the previous instruction cycle at the time of branch judgment processing, that is, at the time of fetching a certain instruction. This is a register for storing.
In the third embodiment, unlike the first and second embodiments shown in FIGS. 1 and 4, the increment used for updating the value of the PC 14 is not fixed length.

In the third embodiment as well, the flow chart of the trace data collection process is basically the same as that of the first embodiment.
The only difference from the processing of the first embodiment is that if the difference between the value and the previous PC value is not a fixed value and does not match the previous instruction length, it is determined to be a branch, and if matched, it is determined not to be a branch. According to the third embodiment, it is possible to collect trace data corresponding to a variable instruction length.

As another embodiment of the processor capable of collecting trace data according to the third embodiment, a mechanism corresponding to a variable instruction length is added to the processor according to the first embodiment of the present invention shown in FIG. Alternatively, the control flag unit 20 may be removed from the processor of the third embodiment shown in FIG. Next, the fourth aspect of the present invention.
An embodiment will be described below.

FIG. 6 is a block diagram of a processor capable of collecting trace data according to a fourth embodiment of the present invention. As shown in FIG. 6, the processor capable of collecting trace data according to the fourth embodiment replaces the storage device 11 in the processor according to the third embodiment of the present invention shown in FIG. The processing unit 30 includes a cache use monitoring unit 40 that monitors the effective use of the instruction cache, and has a mechanism for capturing a branch that wastes the cache.

The cache usage monitoring unit 40 is a monitoring unit for monitoring the effective use of the instruction cache 110.
It is determined whether the difference from the C value is equal to or larger than the size of the instruction cache 110. That is, upon receiving a trigger signal for branch determination synchronized with the instruction fetch, the current P
The C value is compared with the previous PC value held in the previous PC 15. If the difference is equal to or larger than the size of the instruction cache 110, it is determined that the instruction cache 110 is being wasted, and the trace is sent to the data collection processing unit 17. Send a data collection trigger signal. Further, every time the determination process is completed, the current PC value is shifted (overwritten copy) from the PC 14 to the previous PC 15. Note that, when a trace data collection trigger signal is transmitted to the data collection processing unit 17, the shift process is executed after waiting for a completion notification signal from the data collection processing unit 17.

Cache size 41: a cache size holding unit provided in the cache use monitoring unit 40, and is a register for holding the size of the instruction cache 110 at the time of branch determination processing, that is, at the time of fetching a certain instruction. . In the fourth embodiment as well, the flowchart of the trace data collection process is basically the same as in the first and third embodiments. However, step S in the flowchart
In 2, when the difference between the current PC value and the previous PC value is not the previous instruction length and is equal to or larger than the instruction cache size, it is determined that the instruction cache 110 is wasted, and if it is smaller than the instruction cache size, it is determined that the instruction cache 110 is not wasted. Only the point is different from the processing of the first embodiment or the third embodiment. According to the fourth embodiment, the effective utilization rate of the instruction cache 110 can be measured.

Finally, a fifth embodiment of the present invention will be described below. FIG. 7 is a block diagram of a processor capable of collecting trace data according to the fifth embodiment of the present invention. As shown in FIG. 7, the processor capable of collecting the trace data of the fifth embodiment is different from the processor of the third embodiment of the present invention shown in FIG. A data acquisition processing unit 50 provided with a buffer full detection unit 51 for detecting a full state is provided, and a mechanism for automatically stopping the acquisition of trace data is added.

Buffer full detection unit 51: Checks whether the trace buffer 18 is full at each buffering, and when a buffer full is detected, gives an interrupt notification to software (trace data collection program) and issues an instruction. The control flag in the control flag section 20 for enabling or disabling the block trace control is turned off.

FIG. 8 is a flowchart showing a specific example of the operation of the buffer full detector. Step numbers S101 to S104 shown in FIG. 8 are indicated by encircling 1 to 4 in FIG. Step S101: The trace data collection program starts collection of trace data by turning on the control flag in the control flag section 20.

Step S102: The buffer full detecting section 51 checks the full state of the trace buffer 18 for each buffering. Step S103: When the buffer full detecting section 51 detects the buffer full, it notifies the software (here, the trace collection program) of an interrupt and turns off the control flag to automatically stop the collection of the trace data. In addition, since the interrupt processing is being performed, the instruction execution on the corresponding processor remains interrupted unless returning from the trace collection program.

Step S104: The trace collection program (interrupt handler unit) that has received the interrupt notification in step S103 stores the trace data from the trace buffer 18 in a formal (own) data collection area. Thereafter, if the trace data collection process is to be continued, the control flag is turned on again, and the process returns from the interrupt process. When the control flag is turned on and the process returns from the interrupt process, the instruction execution process and the trace data collection process are started.

Thereafter, steps S101 to S104 are repeated as long as the control flag is kept ON. According to the fifth embodiment, it is possible to collect trace data in an arbitrary section and an arbitrary trace data size. (Supplementary Note 1) A trace buffer for storing and holding the trace data of the instruction block of the executed program and a program counter PC for storing and holding the current PC value which is the value of the program counter PC used in the current instruction fetch cycle. A processor capable of collecting trace data, comprising detecting a branch occurrence based on a change in the value of the program counter PC and collecting the trace data.

(Supplementary Note 2) The previous PC value holding unit for storing and holding the previous PC value which is the value of the program counter PC used in the last instruction fetch cycle, and the current instruction fetch as a branch determination trigger, A branch determination processing unit that determines that a branch has occurred when a difference between a current PC value and the previous PC value does not match a fixed instruction length, and generates a collection trigger signal for collecting trace data; A data collection processing unit that receives the signal, collects the previous PC value and the current PC value as a branch source address and a branch destination address, respectively, stores them in the trace buffer, and generates a collection completion notification signal after the completion of the collection. The processor according to supplementary note 1 provided.

(Supplementary Note 3) Whether to enable the branch determination trigger signal sent from the instruction fetch unit that fetches and temporarily stores the instruction written at the memory address indicated by the value of the program counter to the branch determination processing unit 3. The processor according to claim 2, further comprising a control flag for controlling whether to invalidate the processor. (Supplementary Note 4) The branch determination processing unit includes a previous instruction length holding unit that stores and holds a previous instruction length decoded in a previous instruction decode cycle, and determines whether the previous instruction length is a branch. Supplementary note 2 or 3 used for instruction length for determination
A processor according to claim 1.

(Supplementary Note 5) When the difference between the current PC value and the previous PC value exceeds the instruction cache size, the branch determination processing unit determines whether a branch to an instruction address not on the instruction cache at that time is made. 5. The processor according to appendix 2 or 4, further comprising a cache use monitoring unit that determines that generation has occurred and generates a collection trigger signal for collecting trace data.

(Supplementary Note 6) The data collection processing unit determines whether or not the trace buffer is full of trace data each time buffering is completed, and notifies the software of an interrupt when it detects that the buffer is full. 6. The processor according to any one of claims 2 to 5, further comprising a buffer full detection unit that turns off the control flag.

(Supplementary Note 7) A buffer transfer unit that transfers the trace data to a predetermined location in a storage device each time the buffer full detection unit detects that the trace buffer is full of trace data. 7. The processor according to claim 6, wherein:

[0057]

As described above, according to the present invention,
It is possible to collect accurate program execution history data not only in the narrow sense that triggered by a branch instruction as in the past, but also in the broad sense including asynchronous factors such as software interrupts and external interrupts. Become.

According to the present invention, it is also possible to collectively collect, store, and manage target data according to the purpose without being conscious of the types of branch factors such as branch instructions and interrupts. Therefore, in the program section for analyzing the collected data, it is only necessary to read the collected information from one type of storage source, and it is not necessary to read the collected information from another storage location and to perform extra merge processing thereby. The analysis process is simplified. As a result, creation of an execution profile and the like becomes more accurate and easier.

[Brief description of the drawings]

FIG. 1 is a block diagram of a processor capable of collecting trace data according to a first embodiment of the present invention.

FIG. 2 is a flowchart of an instruction cycle executed by a processor.

FIG. 3 is a flowchart of trace data collection processing by a processor capable of collecting trace data according to the first embodiment of the present invention.

FIG. 4 is a block diagram of a processor capable of collecting trace data according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a processor capable of collecting trace data according to a third embodiment of the present invention.

FIG. 6 is a block diagram of a processor capable of collecting trace data according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram of a processor capable of collecting trace data according to a fifth embodiment of the present invention.

FIG. 8 is a flowchart illustrating a specific example of the operation of the buffer full detection unit.

FIG. 9 is a diagram showing an example of an execution program for explaining a problem of trace data collection according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Fixed length setting part 11 ... Storage device 12 ... Instruction fetch & decode unit 13 ... Execution unit 14 ... PC (program counter) 15 ... Previous PC 16, 30 ... Branch judgment processing part 17, 50 ... Data collection processing part 18 ... Trace buffer 19 selector 20 control flag unit 31 previous instruction length 40 cache use monitoring unit 41 cache size 51 buffer full detection unit

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Claims (5)

[Claims] 1. A trace buffer for storing and holding trace data of an instruction block of an executed program, and a program counter PC for storing and holding a current PC value which is a value of a program counter PC used in a current instruction fetch cycle. A processor capable of collecting trace data, comprising detecting a branch occurrence based on a change in the value of the program counter PC and collecting the trace data. 2. A previous PC value holding unit for storing and holding a previous PC value which is a value of the program counter PC used in a previous instruction fetch cycle; and a current PC using a current instruction fetch as a branch determination trigger. A branch determination processing unit that determines that a branch has occurred when the difference between the value and the previous PC value does not match the fixed instruction length, and generates a collection trigger signal for collecting trace data; Receiving the previous PC value and the current PC value as a branch source address and a branch destination address, respectively, storing the same in the trace buffer, and generating a collection completion notification signal after the completion of the collection. The processor according to claim 1. 3. The method according to claim 1, wherein the instruction written to the memory address indicated by the value of the program counter is fetched and temporarily stored in an instruction fetch unit. The processor according to claim 2, further comprising a control flag for controlling whether to perform the operation. 4. The branch determination processing unit includes a previous instruction length holding unit that stores and holds a previous instruction length decoded in a previous instruction decode cycle, and determines whether the previous instruction length is a branch. 4. The processor according to claim 2, which is used for an instruction length for branch determination. 5. The branch determination processing unit determines, when a difference between the current PC value and the previous PC value exceeds an instruction cache size, that a branch to an instruction address off the instruction cache at that time has occurred. 5. The processor according to claim 2, further comprising a cache use monitoring unit that generates a collection trigger signal for collecting trace data.