JP2002328655A - Active matrix type display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display for displaying switching between a moving picture display mode in which data are inputted at any time and a still picture display mode which displays the still picture in accordance with the data of a holding circuit, by arranging the holding circuit to each pixel. SOLUTION: Almost all circuits are shared and used by the still picture display mode and the moving picture display mode, by supplying data to a holding circuit 6 corresponding to each sub-pixel electrode 5 from respectively different video signal lines 3 in the still picture display mode, and by supplying the same voltage to a plurality of sub-pixel electrodes 5 corresponding to one pixel in the moving picture display mode. Thereby, the number of elements to be arranged to one pixel can be reduced, size of the pixel can be made small, and high definition can be realized. Moreover, as one embodiment, multi- level display can be carried out in the still picture display mode by integrating the holding circuit of multiple bits into one pixel and by using a dot area modulation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an active matrix display device, and more particularly to an active matrix display device provided with a plurality of holding circuits corresponding to pixels.

[0002]

2. Description of the Related Art In recent years, portable display devices such as portable televisions and portable telephones have been demanded as market needs. In response to such demands, research and development have been actively conducted to reduce the size, weight, and power consumption of the display device.

FIG. 5 shows a circuit configuration diagram of one display pixel of a liquid crystal display device according to a conventional example. A plurality of gate signal lines 102 and analog signal lines 103 are formed on an insulating substrate 101 so as to intersect with each other.
Pixel selection thin film transistor 10 connected to 2 and 103
4 are provided. Hereinafter, a thin film transistor is referred to as a TFT.
Abbreviated. The analog signal line 103 is a pixel selection TFT 104
Is connected to the pixel electrode 105 via the. Further, an auxiliary capacitance 106 for holding the voltage of the pixel electrode 105 for one field period is provided.
Is connected to the pixel selection TFT 104, and a common potential is applied to the other electrode 107 for each display pixel. The pixel selection TFT 104, the pixel electrode 105, and the storage capacitor 106 are arranged in each pixel.

A gate driver 108 and a drain driver 109 are arranged in a peripheral area of the substrate 101. The gate driver 108 includes a plurality of gate signal lines 1
02 is connected to sequentially apply a scanning signal. A plurality of analog signal lines 103 are connected to the drain driver 109, and a video signal voltage corresponding to each analog signal line 103 is applied. A scanning signal (H level) is applied to the gate signal line 102
Is applied, the pixel selection TFT 104 connected to the gate signal line 102 is turned on, an analog video signal is transmitted from the analog signal line 103 to the pixel electrode 105, and is held in the auxiliary capacitance 106. A video signal voltage applied to the pixel electrode 105 is applied to the liquid crystal, and the liquid crystal is oriented according to the voltage, whereby a liquid crystal display can be obtained. Therefore, liquid crystal display can be performed regardless of a moving image or a still image.

By the way, a memory element is arranged for each pixel,
Proposals for stopping the operation of peripheral circuits when displaying a still image and reducing the power consumption of the display device include, for example, Japanese Patent Application Laid-Open No. 8-194205 and Japanese Patent Application No. 2000-2821.
68 and the like.

FIG. 6 is a circuit diagram showing one pixel of a conventionally proposed active matrix display device with a memory element.

A gate signal line 10 is provided on an insulating substrate 101.
2. An address signal line 121 is formed so as to intersect, and a pixel selection TFT 122 connected to both signal lines 102 and 121 is provided near the intersection. Further, the digital signal lines 123 are arranged in a direction parallel to the address signal lines 121. The digital signal line 123 is connected to the pixel 1
The number is arranged in accordance with the number of bits of the digital signal to be supplied to the column, and four bits and four are arranged in the figure. The digital signal lines 123 are respectively connected to the memory elements 124. The memory element 124 includes a pixel selection TFT 1
22 turns on, the digital signal line 123 at that time
Is held in two values, ON and OFF. The output of the memory element 124 is input to the gate of the sub-pixel TFT 125 to control on / off thereof. Each of the sub-pixel TFTs 125 is connected to a sub-pixel electrode 126, and the reference voltage Ref is supplied to the sub-pixel electrode 126 when the sub-pixel TFT 125 is turned on.

In the peripheral area of the substrate 101, a gate driver 108 and a drain driver 127 are arranged. The gate driver 108 includes a plurality of gate signal lines 1
02 is connected to sequentially apply a scanning signal. A plurality of address signal lines 121 and digital signal lines 123 are connected to the drain driver 127.
3 is applied. Gate signal line 10
2 and the address signal line 121, when a scanning signal (H level) is applied, the pixel selection TFT 12
2 is turned on, and the memory element 124 is activated.
At the same time, a digital video signal is transmitted from the digital signal line 123 to the memory element 124. The digital data is 4-bit data. The least significant bit D0 is on the digital signal line 123a, and the most significant bit D3 is on the digital signal line 12a.
3d. The memory element 124 holds data so that when each bit data is high, it outputs high. The sub-pixel TFT 125 connected to the memory element 124 holding high is turned on, and the reference voltage is supplied to the sub-pixel electrode 126 connected to the sub-pixel TFT 125. The sub-pixel electrodes 126 have different areas, and the area ratio of the sub-pixel electrodes 126a to 126d is (126a:
126b: 126c: 126d) = (1: 2: 4: 8)
It has become. Therefore, each sub-pixel electrode 126
By independently controlling the ON and OFF of the display, it is possible to display 4 bits and 16 gradations.

The display device having such a configuration can reduce power consumption when displaying a still image as compared with a normal display. That is, when the memory element 124 is an SRAM, the data is held until the next data is overwritten, so that the gate driver 108 and the drain driver 1
Even if 27 is stopped, the still image can be continuously displayed. When the memory element 124 is a DRAM, the operation cycle of the gate driver 108 and the drain driver 127 can be delayed until the refresh cycle.

[0010] Also, in Japanese Patent Application No. 2000-282168,
It is disclosed that the circuits of FIG. 5 and FIG. 6 are arranged in parallel to each pixel to switch between a moving image display mode and a still image display mode.

[0011]

SUMMARY OF THE INVENTION Japanese Patent Application No. 2000-282.
The display device disclosed in 168 arranges a circuit for displaying a moving image and a circuit for displaying a still image in parallel, and switches between a moving image display mode and a still image display mode. Therefore, it is necessary to integrate and arrange the respective circuits in each pixel, so that the number of elements arranged in one pixel increases, and it is difficult to reduce the pixel size and to achieve high definition. Also, it has been difficult to increase the number of bits of data to be held.

Accordingly, an object of the present invention is to provide an active matrix type display device capable of reducing the number of elements integrated in one pixel, achieving higher definition, and holding more bits of data. I do.

[0013]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a plurality of gate signal lines arranged in one direction on a substrate and a plurality of gate signal lines arranged in a direction intersecting the gate signal lines. A plurality of video signal lines, a plurality of pixel electrodes arranged for each pixel and a plurality of sub-pixel electrodes that are insulated from each other, and are arranged corresponding to the sub-pixel electrodes, and store data corresponding to the video signals. Holding circuits arranged in one pixel, different video signal lines are arranged corresponding to each other, and the holding circuit holds data corresponding to the video signal via each of the video signal lines. Then, a still image display mode for displaying according to the data held in the holding circuit, and a voltage for each pixel corresponding to a video signal input as needed, are applied to each sub-pixel electrode via each video signal line. Apply And a Shimesuru video display mode,
The active matrix type display device supplies the same voltage to a plurality of sub-pixel electrodes corresponding to one pixel in the moving image display mode.

Further, the video signal line and the holding circuit are respectively connected via pixel selection transistors, and the pixel selection transistors arranged in one pixel are simultaneously turned on,
Turn off.

Further, the holding circuit has a holding capacity for holding a voltage, and in the moving image display mode, the holding capacity is:
Functions as an auxiliary capacitor.

Further, a plurality of sub-pixel electrodes constituting one pixel electrode have different areas from each other.

[0017]

FIG. 1 is a circuit diagram of an active matrix display device according to a first embodiment of the present invention.

A gate signal line 2 and a video signal line 3 are formed to intersect on an insulating substrate 1 made of non-alkali glass or the like, and are connected to both signal lines 2 and 3 corresponding to the intersection. A plurality of pixel selection TFTs 4 are provided. The number of the video signal lines 3 is arranged according to the number of bits of the digital signal supplied for each column. Hereinafter, when the video signal lines 3 corresponding to the respective bits are distinguished from each other, they are denoted as 3a, 3b, 3c, and 3d, respectively, and these are collectively referred to as the video signal lines 3. Regarding the other configurations described below, the configurations arranged for each bit are distinguished from each other by adding a, b, c, and d to the numbers. The video signal line 3 is connected to the sub-pixel electrode 5 via the pixel selection TFT 4. As a memory element for holding the voltage of the sub-pixel electrode 5 for a predetermined period, a storage capacitor 6 is provided corresponding to each sub-pixel electrode 5, and one terminal of the storage capacitor 6 is a pixel selection TFT 4 , And a common potential is applied to the other electrode 7 for each display pixel. Pixel selection TFT
The pixel electrode 5, the storage capacitor 6, and the storage capacitor 6 are arranged in each pixel.

In the peripheral area of the substrate 1, a gate driver 8 is provided.
And a drain driver 9. A plurality of gate signal lines 2 are connected to the gate driver 8, and sequentially apply a scanning signal. A column selection line 10 is connected to the drain driver 9, and sequentially applies a column selection signal. The column selection line 10 is connected to the gate of the column selection TFT 11. The video signal common lines 12 are arranged in a direction crossing the video signal lines 3 of each column, and are connected to the video signal lines 3 of each column via the column selection TFT 11.

A second substrate disposed opposite to the substrate 1 is provided with a counter electrode, a color filter, and the like, which are formed facing a plurality of pixels. Forming device. The configuration of the second substrate is the same as that of a generally known configuration, and will not be described in detail.

The column selection TFTs 11 are arranged by the number of bits in each column of the pixel electrode.
One column selection line 10 is commonly connected to the gates of 11b, 11c, and 11d, and is turned on and off at the same time. When the column selection TFT 11 is turned on, the video signal line 3 is connected to the video signal common line 12, and a video signal voltage corresponding to a digital signal of each bit is applied.

The display device according to the present embodiment includes a moving image display mode in which an input video signal is displayed at any time to display a moving image, and a still image in which a still image is displayed while retaining the video signal to reduce power consumption. It has a display mode. Hereinafter, each operation mode will be sequentially described.

(1) Moving Image Display Mode In the moving image display mode, a common analog signal is supplied to a plurality of video signal common lines 12 to perform almost the same operation as the conventional active matrix display device shown in FIG. I do. First, when the gate driver 8 selects a predetermined gate signal line 2 and applies a scanning signal (H level) to the gate signal line 2, all the pixel selection TFTs 4 connected to the gate signal line 2 are turned on. The drain driver 9 selects a predetermined column selection line 10 and outputs a selection signal. by this,
The four video signal lines 3a, b, c, and d in this column are connected to the video signal common line 12. The same analog video signal is supplied to the four video signal common lines 12. The analog video signal is supplied to each of the sub-pixel electrodes 5 a to 5 d of the pixel electrode 5 via the video signal common line 12, the column selection TFT 11, the video signal line 3, and the pixel selection TFT 4, and is stored in the storage capacitor 6. . Video signal common line 12 and sub-pixel electrode 5
a to 5d are column selection TFTs 1
1 and a pixel selection TFT 4, both of which have their gates connected to each other and are turned on and off at the same time.
Since the same analog signal voltage is supplied to each sub-pixel electrode 5, each of the sub-pixel electrodes 5a to 5d operates as if it were one pixel electrode in the moving image display mode. The storage capacitors 6a to 6d are the same as the conventional auxiliary capacitors 1
Works the same as 06.

FIG. 2 is a characteristic diagram showing a correlation between the pixel voltage Vp applied between the counter electrode and the pixel electrode 5 and the transmittance T of the liquid crystal in the present embodiment. FIG. 2A shows a normally black (NB) mode in which the transmittance becomes minimum when the pixel voltage Vp = 0, and FIG. 2B shows a normally white (NB) mode in which the transmittance becomes maximum when the pixel voltage Vp = 0. NW) mode. In FIG. 2A, the pixel voltage Vp
When the pixel voltage Vp is gradually increased from = 0, the transmittance T of the liquid crystal starts to increase when a certain voltage Vp = V1. Thereafter, the transmittance T continues to increase with an increase in the pixel voltage Vp, and when a certain voltage Vp = V2, the transmittance T becomes a maximum value, and the transmittance T does not increase any more, resulting in a luminance saturated region. . The same applies when the NW mode is used.
When Vp = V3, the transmittance T starts to decrease, and Vp = V3
4, the transmittance T becomes the lowest, and becomes a luminance saturated region where the transmittance T does not further decrease. V _{min for} both NB mode and NW mode
In the above V _MAX following voltage region, the correlation between the transmittance T and the pixel voltage Vp is substantially linear (linear). Analog video signal in the video display mode is any of a voltage selected from the linear region the V _min or V _{M AX.}

(2) Still Image Display Mode The still image display mode is a mode in which an analog video signal is converted into a digital signal, video data for one screen is stored in a frame memory (not shown), and a still image is displayed. is there.
Each bit data of the digitized video signal is supplied as high or low to the video signal common lines 12a, b, c, and d. The data of the least significant bit of the digital video signal is supplied to the video signal common line 12a, and the data of the most significant bit is supplied to 12d. The gate driver 8 sequentially inputs an operation signal to the gate signal line 2. Gate signal line 2
Is input, all the pixel selection TFTs 4 connected to the gate signal line 2 are turned on. Each bit data of the digital video signal is transmitted via the pixel selection TFT 4 to the sub-pixel electrode 5 and the storage capacitor 6a.
To 6d, and stored in the storage capacitors 6a to 6d, respectively. When the gate driver 8 selects another gate signal line 2 and the gate signal line 2 goes low, the pixel selection TF
T4 is turned off, and each of the sub-pixel electrodes 5 becomes floating. The area ratio of the sub-pixel electrodes 5a to 5d is (5
a: 5b: 5c: 5d) = (1: 2: 4: 8). Therefore, the least significant bit, 5d
Supplies the pixel voltage based on the data of the most significant bit to
By controlling the on / off of each sub-pixel electrode 5 independently, a 4-bit 16-gradation display can be performed. In this way, the pixel electrode is divided into a plurality of regions,
A method of adjusting the luminance by controlling the area of light emission (in the case of liquid crystal, transmitting light) is called an area gradation method.

In the present embodiment, the video signal line in the still image display mode and the video signal line in the moving image display mode are
Since it is common, the circuit scale is greatly increased as compared with the case where the operating circuits are switched and displayed between the still image display mode and the moving image display mode as disclosed in Japanese Patent Application No. 2000-282168, for example. Can be reduced to

Next, the voltage stored in the storage capacitor 6 will be described with reference to FIG. As described above, in the moving image display mode it has been performed a display using the following linear voltage region V _min or V _MAX. Of course, this voltage may be held. However, since the memory element of the present embodiment is a DRAM using the storage capacitor 6, the storage voltage gradually decreases due to, for example, leakage from the pixel selection TFT 4. Therefore, it is necessary to refresh the holding voltage every predetermined cycle. Here, when the voltage in the linear region used in the moving image display mode is held by the holding capacitor 6, a decrease in the holding voltage due to a slight leak is directly linked to a change in the transmittance of the liquid crystal. For example, in the NB mode, Vp = V
_It is assumed that _MAX is stored in the storage capacitor 6. Assuming that the holding voltage, that is, the pixel voltage Vp decreases by ΔV1 during the period between the refresh and the next refresh, the transmittance T decreases by ΔT1. Therefore, when the refresh is performed and the holding voltage recovers, the transmittance T recovers at the same time. This is visually recognized as a flicker of the luminance difference ΔT1, that is, a display flicker when observing the screen, which is a factor of deteriorating the display quality.
Therefore, in the present embodiment, this problem is solved by setting the holding voltage in the luminance saturation region of the pixel voltage. More specifically, the boundary voltages V2 and V4 that are in the luminance saturation region
The voltage VH is set to be higher than the voltage VH by at least ΔV. The row voltage held in the holding circuit 6 is set to a luminance saturation region, that is, a voltage VL lower than the boundary voltages V1 and V3. As described above, Vp ≦ V1, Vp ≧
In the luminance saturation region of V2 or Vp ≦ V3, Vp ≧ V4, even if the pixel voltage changes, the transmittance T of the liquid crystal hardly changes. Now, it is assumed that the holding voltage decreases by ΔV between the refresh and the next refresh. In the present embodiment, the high voltage held in the holding circuit 6 in the still image display mode is set to be higher than the boundary of the luminance saturation region by ΔV or more. Therefore, even if the holding voltage drops by ΔV, the holding voltage is still within the luminance saturation region and the transmittance does not change. The voltage to be held is defined as a luminance saturated region like these VH and VL.
Further, by setting the voltage higher than the boundary area by △ V or more, even if the holding voltage decreases by の 間 に V before refreshing and the holding voltage recovers during refreshing, the transmittance T does not fluctuate and the display does not flicker. Is done. Decreasing voltage △
V is the characteristic of the pixel selection TFT 4, the leakage from the liquid crystal,
It depends on the refresh cycle. Pixel selection TF
If T4 is an N-channel type TFT, it is possible to reduce the leakage and minimize ΔV.

Next, the shape and arrangement of the sub-pixel electrode 5 will be described. Both the conventional sub-pixel electrode 126 and the sub-pixel electrode 5 of the present embodiment have an area ratio of 5a to 5d of (1: 2:
4: 8). However, the conventional sub-pixel electrode 1
In the arrangement of 26, for example, the distance between the bright spots is determined when the pixel in which only the sub-pixel electrode 126a is lit and the pixel in which only 126d is lit are adjacent to each other, and when all 126a to 126d are lit. However, the display quality deteriorates, for example, the edge of the image becomes dull, the resolution is visually recognized as low, and the RGB color mixing is not performed properly. Therefore,
In this embodiment, the pixels are concentric rectangles.
First, the sub-pixel electrode 5a is a rectangle located at the center of the pixel. Next, the sub-pixel electrodes 5b to 5d have a rectangular shape whose center is hollowed out, and are arranged so as to surround the periphery of the smaller sub-pixel electrode. For more details, see 5
The rectangles on the outer periphery of a to 5d and the inner periphery of 5b to 5d are all rectangles, and are so-called concentric rectangles arranged so that all intersections of diagonal lines coincide. With such an arrangement, the viewing angle characteristics become uniform in the vertical and horizontal directions, and the edges of the image can be sharpened. Also, for example, when only 5d is lit, the ring-shaped portion is actually lit, but if the ring is sufficiently fine, the center of the human eye, that is, It is an illusion that the bright spot is located at the intersection of the diagonal lines. Therefore, when part or all of the sub-pixel electrodes 5a to 5d are lit, it is not visually recognized that the pixel intervals are different, and it is possible to prevent a decrease in image quality such that the resolution is perceived to be low. Can be.

The shape of the sub-pixel electrode 5 is not limited to the one described above, and the shape shown in FIG. 3 is also suitable. In FIG. 3A, the sub-pixel electrode 5a is vertically arranged at the center of the pixel. Sub-pixel electrodes 5b1 and 5b2 are arranged on both sides of the sub-pixel electrode 5a, and they are connected via 5b3 arranged above. Sub-pixel electrodes 5c and 5d are sequentially and similarly arranged on both sides thereof. FIG. 3B is different from FIG. 3A in that the sub-pixel electrode 5 is arranged horizontally long with respect to the vertically long pixel electrode. 3 (a) and 3 (b), 5b
The connections 1 and 5b2 may be arranged in the same layer with the arrangement of 5b3 as shown, or may be connected to the lower conductive layer via a contact. What is common to both the shapes of FIG. 1 and FIG. 3 is that the arrangement of the sub-pixel electrodes 5 is line-symmetric with respect to a line crossing the center of the pixel horizontally and vertically. In the arrangement shown in FIG. 3, for example, since 5b3 connecting the parts 5b1 and 5b2 arranged on the left and right of 5b is arranged, it is not strictly line-symmetrical in the vertical direction. It does not contribute to display and can be said to be substantially line-symmetric. In this way, by arranging the sub-pixel electrodes 5 in line symmetry, the viewing angle characteristics can be improved.

By the way, if an electric field in only one direction is continuously applied to the liquid crystal, it causes deterioration of the liquid crystal. Therefore, it is general to perform a so-called inversion drive in which the direction of the electric field is inverted at predetermined intervals. This inversion drive is inverted once per frame in the moving image display mode in the present embodiment. That is, the inversion cycle is about 60 Hz. This is generally performed even in a conventional liquid crystal display device having no holding circuit. However, from the viewpoint of preventing deterioration of the liquid crystal, several H
An inversion cycle of about z is sufficient. Further, as described above, the stored contents need to be refreshed every predetermined period due to the leakage of the storage capacitor 6. Hereinafter, the refresh and inversion cycle of the holding circuit 6 will be described in detail with reference to FIG.

As shown in FIG. 4A, the voltage held in the holding circuit, that is, the potential of the pixel electrode is reduced by ΔV during the period t1 due to leakage. The holding voltage is maintained by refreshing at the cycle t1. For example, if the refresh cycle is 0.1
Second, it is assumed that the frequency is 10 Hz. The inversion driving is performed at a cycle t2, and the pixel electrode potential and the counter electrode potential are inverted. It is preferable to set the inversion cycle t2 as late as possible within a range in which deterioration of the liquid crystal can be prevented, because power consumption can be reduced. In the present embodiment, for example, 0.4 seconds,
2.5 Hz. The inversion cycle is synchronized with the refresh cycle, and the holding circuit 6 overwrites the same data in the cycle t1 and overwrites the inverted data in the cycle t2.

Further, as shown in FIG. 4B, the refresh cycle t1 and the inversion cycle t2 can be set equal. By reducing the leakage of the holding circuit 6 or setting the voltage held in the holding circuit 6 sufficiently higher than the boundary voltage of the luminance saturation region, the period from when the voltage is held until the luminance starts to decrease is lengthened. can do. If the refresh cycle t1 can be set long, the refresh cycle t1 and the inversion cycle t2 are made to match,
A circuit for refreshing and a circuit for inversion driving can be used in common, thereby simplifying the circuit configuration. Simultaneous operation can reduce power consumption.

Next, the storage capacitor 6 will be described. The sum of the capacitance values of the storage capacitors 6a to 6d arranged in one pixel is set to be larger than that of the auxiliary capacitance 106 of the normal active matrix display device shown in FIG. This is because if the capacitance value of the storage capacitor 6 is large, the voltage drop due to the leak current is small, so that the refresh cycle t1 can be set longer. For example, the total capacity of the holding capacity 6 is about four times the capacity of the conventional auxiliary capacity 106. In a conventional active matrix display device, an auxiliary capacitor 1
When the capacity of 06 is set to be large, the time required to apply a necessary voltage to the pixel electrode becomes long, and it becomes difficult to operate at 60 Hz. On the other hand, in the active matrix display device of the present embodiment, a common video signal is supplied to the four video signal lines 3 in the moving image display mode, and a voltage is applied to each sub-pixel electrode 5 in parallel. , Individual storage capacitors 6 corresponding to individual sub-pixel electrodes 5a to 5d.
Even if the capacitance values of a to 6d are not set so large, there is no problem in displaying moving images. In the still image display mode, it is necessary to write a voltage higher than the voltage in the moving image display mode to the storage capacitor 6, but in the still image display mode, the period of one frame is set longer than in the moving image display mode. By doing so, writing can be performed favorably.

Next, the capacitance value of the storage capacitor arranged in each pixel will be described. In the moving image display mode, the pixel selection T
When the FT 4 changes from on to off, the pixel electrode 5 becomes floating, so that the potential of the pixel electrode fluctuates due to coupling with the counter electrode. The amount of variation at this time depends on the capacitance value of the storage capacitor 6 and each of the sub-pixel electrodes 5a to 5d.
Corresponds to the sum of the counter electrode and the liquid crystal capacitance to be formed via the liquid crystal. The capacitance values of the storage capacitor 6 are Ca, Cb, and C, respectively.
c, is denoted as Cd, denoted each subpixel electrode 5 liquid crystal capacitance corresponding to the respective _{C LC a, C LC b,} C LC c, and C _LC d. If this variation value differs among the sub-pixel electrodes 5a to 5d, it is visually recognized as flicker.

Hereinafter, a first method for preventing flicker will be described. The potential difference △ VF causing generally flicker on the gate, the gate voltage switching OFF Von-off, the gate of the transistor, the source capacitance Cgs, the holding capacitor C, and a liquid crystal capacitance C _LC △ VF = Von-off represented by Cgs / (Cgs + C + C LC). In the first method, the sum of the storage capacitance value and the liquid crystal capacitance value is set to be equal for each sub-pixel electrode. That is, Ca + C _LC a = Cb + C _LC b = Cc + C _LC c = Cd + C
Meet _LC d. As a result, ΔVF becomes equal for each sub-pixel electrode, so that flicker can be prevented. Of course, it is difficult to determine the liquid crystal capacitance value _CLC strictly at the time of designing, so that the liquid crystal capacitance value _CLC may be designed with some errors. However, the range of the error needs to be smaller than C _LC-Black -C _LC-White . Here, _CLC-Black is the liquid crystal capacity when displaying black, and _CLC-White is the liquid crystal capacity when displaying white.

Also, as the area of the sub-pixel electrode 5 increases, the corresponding liquid crystal capacitance also increases. Therefore, Ca>Cb>Cc> Cd. From the viewpoint of preventing flicker, comparing the storage capacitor 6 and a liquid crystal capacitor connected to the respective sub-pixel electrodes and keep the _{Ca> C LC a Cb> C} LC b Cc> C LC c Cd> C LC d It is effective for preventing flicker.

A second method effective for preventing flicker will be described. As described above, since the area of each sub-pixel electrode 5 is (1: 2: 4: 8), the liquid crystal capacitance C _LC is also substantially (C _LC a: C _LC b: C _LC c: C _LC d) = (1: 2: 4:
8) is satisfied. At this time, (Ca: Cb: Cc: Cd) = (1: 2: 4: 8) and the channel widths W4a to W4d of the pixel selection transistors 4a to 4d are set as (W4a: W4b: W4c: W4d) = (1: 2: 4:
8) Set as Thereby, the pixel selection transistor 4a
The capacitance Cgs between the gate and the source of ~ 4d becomes the same ratio. Accordingly, flicker can be prevented by setting △ VF substantially to zero.

[0038]

As described in detail above, in the still image display mode, data is supplied from different video signal lines to the holding circuits corresponding to the respective sub-pixel electrodes, and data is supplied to one pixel in the moving image display mode. By supplying the same voltage to a plurality of sub-pixel electrodes, most circuits are shared between the still image display mode and the moving image display mode.
The number of elements arranged in one pixel can be reduced, the size of the pixel can be reduced, and high definition can be achieved. Further, as in the embodiment, by integrating a multi-bit holding circuit in one pixel and using area gradation, multi-gradation display can be performed in the still image display mode.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an active matrix display device according to a first embodiment of the present invention.

FIG. 2 is a correlation diagram between a pixel voltage applied between a pixel electrode and a counter electrode and a liquid crystal transmittance.

FIG. 3 is a diagram showing a layout of a sub-pixel electrode of the present invention.

FIG. 4 is a diagram illustrating refresh and inversion drive timings of a holding circuit according to the present invention.

FIG. 5 is a circuit diagram showing a conventional active matrix display device.

FIG. 6 is a circuit diagram showing a conventional active matrix display device with a holding circuit.

[Explanation of symbols]

 1: substrate 2: gate signal line 3: video signal line 4: pixel selection TFT 5: pixel electrode, sub-pixel electrode 6: storage capacitor 11: column selection TFT 12: video signal common line

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 621 G09G 3/20 621K 641 641G 660 660U 660V (72) Inventor Michiru Senda Keihan, Moriguchi-shi, Osaka 2-5-5 Hondori Sanyo Electric Co., Ltd. F-term (reference) 2H093 NA12 NA33 NA43 NA54 NC12 NC28 NC34 NC35 ND06 ND10 ND52 5C006 AA02 AF45 AF69 BB16 BC03 BC06 BC13 BF37 FA04 FA43 FA47 FA56 5C080 AA10 BB05 DD22 DD26 EE29 JJ02 JJ03 JJ04 JJ05 5C094 AA15 AA22 AA51 BA03 BA43 CA19 CA20 EA04 EA07 HA08

Claims (4)

[Claims] 1. A plurality of gate signal lines arranged in one direction on a substrate, a plurality of video signal lines arranged in a direction crossing the gate signal lines, and a plurality of video signal lines arranged for each pixel and insulated from each other. A plurality of pixel electrodes each including a plurality of sub-pixel electrodes, and a holding circuit arranged corresponding to the sub-pixel electrodes and storing data corresponding to a video signal, the holding circuit being arranged in one pixel Respectively, the different video signal lines are arranged corresponding to each other, hold data corresponding to the video signal in the holding circuit via each of the video signal lines, and display according to the data held in the holding circuit. A still image display mode, and a moving image display mode in which a voltage for each pixel corresponding to a video signal input as needed is applied to each sub-pixel electrode as needed via each of the video signal lines and displayed. , Said An active matrix display device, wherein the same voltage is supplied to the plurality of sub-pixel electrodes corresponding to one pixel in a moving image display mode. 2. The image signal line and the holding circuit are connected via respective pixel selection transistors, and the pixel selection transistors arranged in one pixel are turned on and off at the same time. Item 7. An active matrix display device according to item 1. 3. The active device according to claim 1, wherein the holding circuit has a holding capacitor for holding a voltage, and the holding capacitor functions as an auxiliary capacitor in the moving image display mode. Matrix display device. 4. The active matrix type display device according to claim 1, wherein the plurality of sub-pixel electrodes constituting one pixel electrode have different areas from each other.