JP2002325460A - Method/device for modulation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily restrain leakage of a carrier power signal to a load side. SOLUTION: This PWM modulation device subjects an input digital signal S1 to pulse width modulation (PWM), to generate a pair of PWM power signals S7, S15 mutually in a complementary relation of 2, suppresses in the respective PWM power signals a carrier frequency component via power LPF8, 24 to obtain a pair of power signals, balance drives a load (speaker 12) by a pair of the power signals, so as to make a fixed edge side K of these PWM power signals capable of shifting at random in a time axial direction, and disperses a spectrum of respective carrier of a pair of these PWM power signals S7, S15, so that a peak level of the carrier leaking to this load side can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PWM modulation method and a PWM modulation apparatus which are suitably applied for the purpose of reducing a peak value of a frequency component of a carrier signal of a PWM signal supplied to a load. About.

[0002]

2. Description of the Related Art Conventionally, as a power amplifier to which a PWM modulation method or a PWM modulation device is applied, a part of this power amplifier is class D amplification (class D operation).
Pulse width modulated power amplifier (pulse wi
dth modulation (in the following description, pulse width modulation is referred to as PWM)
is known as one form of the PWM modulator. Since this type of pulse width modulation power amplifier has good power amplification efficiency and is power saving, there are many power amplifiers such as a power amplifier for an audio signal, a power amplifier for driving a deflection coil of a cathode ray tube, and a power amplifier for driving an induction motor. Applications in this area have been reported in the literature.

[0003] First, this PWM using a PWM modulator is applied.
A typical example of the power amplifier will be described with reference to FIG.

FIG. 7A is a block diagram showing an example of a configuration of a main part of the PWM power amplifier.
Denotes an input terminal 2 for a digital signal S1, a PWM amplifier 3, a pre-driver circuit 4, a first N-channel power MOS
FET (hereinafter referred to as first power FET) 6 and second N-channel power MOSFET
(In the following description, it is referred to as a second power FET.)
Class D power amplifying section 5 having 7 and power choke coil 9
And a high frequency cutoff type power filter unit (hereinafter referred to as a power LPF unit) 8 having a carrier frequency and the like having a power capacitor 10, a speaker unit 12, and a clock signal S2 having a constant repetition period t. Output master clock signal generator 13 and power supply 14
It is composed of

[0005] The class D power amplifying section 5 has a first power F
The source of the ET6 and the drain of the second power FET 7 are connected in series, the drain side of the first power FET 6 is connected to the + DC power supply terminal + Vcc of the power supply unit 14, and the source side of the second power FET 7 is grounded. It is configured.

Therefore, the first power FET 6 and the second power FET 6
Are connected in this way to form a half-bridge circuit. And as a driver to drive the half-bridge circuit configured in this way,
A pre-driver circuit section 4 is provided, and the half-bridge circuit section and the pre-driver circuit section constitute a half-bridge output stage.

Next, the operation of the pulse width modulation power amplifier 1 will be described.

In the following description, for example, PWM
An edge locked in synchronization with the clock signal S2 at the timing of the repetition period t of the clock signal S2, such as the waveform of the power signal S7, is referred to as a fixed edge K. For example, the fixed edge K is a waveform edge of the PWM power signal S7 indicated by an upward arrow in each of 1B, 2B, 3B and 4B in FIG. 7B.

The waveform of the PWM power signal S7, etc.
An edge whose position changes according to a change in the signal level of the digital signal S1 is referred to as a movable edge M.
For example, the waveform of the PWM power signal S7 shown by horizontal arrows in each of 2B and 3B in FIG. 7 indicates a state in which the edge M is moved. In the following description, among the fixed edges K locked to the clock signal S2, the edge that precedes in time is referred to as a starting edge for convenience. For example, in the waveform shown in FIG. 7B, of the fixed edge K of the PWM modulation waveform, the movable edge M
On the other hand, the fixed edge K on the left side in FIG. 7 is the starting edge. Note that the pulse width modulation amplifier 3, pre-driver circuit 4, and class D power amplifier 5 also
Although not shown, power necessary for operation is supplied to these amplifying units and circuit units as is well known.

Then, DC power stabilized to a predetermined constant voltage value is generated by the power supply unit 14, and is supplied to the D-class power amplification unit 5 from the + DC power supply terminal + Vcc of the power supply unit 14 to + DC power supply.
Polarity DC power is supplied, and the negative polarity side of the DC power output is grounded via the ground terminal 15.

However, when the class D amplifier is constituted by an amplifier of a dual power supply system, + Vcc and -Vcc are output from the power supply unit 11, and + Vcc and -Vc
The power supply unit in which the midpoint between the points c is grounded is also included as a modification of the switching power supply unit 14 unless otherwise specified in the following description.

The digital signal S1 input to the input terminal 2
Is a pulse width modulation circuit 3A provided in the pulse width modulation amplification unit 3.
7B generated by the master clock signal generator 13 as shown in FIG.
Having a fixed edge K which is locked in synchronization with the repetition period of the clock signal S2 having the following. The movable edge represented by the change in the pulse width direction between the fixed edges K according to the change in the signal level of the digital signal S1. PW with edge M
An M signal is generated via the pulse width modulation circuit 3A.

The PWM signal S3, which is obtained by amplifying the PWM signal to a predetermined level via the amplifier 3B, is output from the pulse width modulation amplifier 3. On the other hand, the PWM signal S4 whose phase is inverted through the phase inverting amplifier 3C and amplified to a predetermined level is output from the pulse width modulation amplifier 3.

That is, a change in the signal level of the digital signal S1 input to the signal input terminal 2 is converted into a PWM signal S3 represented by a change in the pulse width direction and a PWM signal S4 having a waveform negatively related to the signal S3. It is converted and output from the pulse width modulation amplifier 2. Therefore, in the following description, the negative relationship between the waveform of the PWM signal S3 and the waveform of the PWM signal S4 means that when one of the signals S3 and S4 has a positive waveform, Is in a state of a waveform having a negative polarity, that is, a state of exhibiting a so-called complementary characteristic.

The PWM signal S3 is used as a drive signal S that enables the first power FET 6 to be turned on / off in a sufficiently stable state transiently via the pre-driver circuit section 4.
The PWM signal S4 is converted into a drive signal S6 through which the second power FET 7 can be turned on / off in a sufficiently stable state transiently via the pre-driver circuit section 4, and the first power The FET 6 is driven by the signal S5, the second power FET 7 is driven by the signal S6, and the FETs 6 and 7 are alternately turned on and off by the PWM signals S5 and S6.
7B generated by switching from the connection point between the source of the FET 7 and the drain of the FET 7 and the ground side in accordance with the change in the pulse width direction of the PWM signals S5 and S6. As a result, a PWM power signal S7 subjected to pulse width modulation in accordance with the change in the signal level of the digital signal S1 is output.

Accordingly, when the signal level of the digital signal S1 is 0 level, the PWM power signal S7
As shown in FIG. 7B, the movable edge M is located at the center position between the fixed edges K, and the duty ratio (duty ratio) is set.
io) is converted to a 50% PWM signal. When the signal S1 is a signal in a state of increasing from the 0 level in the + level direction, as shown in an example in 2B of FIG. 7, this movable edge M is shown in 1B of FIG. The signal is converted to a pulse width modulated PWM signal while moving rightward from this state toward FIG. And this signal S
When 1 is a signal in a state of increasing from the 0 level in the -level direction, as shown in an example of 3B in FIG. 7, the movable edge M changes from the state shown in 1B of FIG. The signal is converted to a pulse width modulated PWM signal while moving leftward toward.

That is, the change in the signal level of the digital signal S1 is changed by the pulse width modulation amplifier 3, the pre-driver circuit 4, and the D-class power amplifier 5 into a signal formed by the fixed edge K and the movable edge M. It is converted into a PWM signal S7 expressed as a change in the area of the waveform.

Further, as described above, when the waveform edges at both ends of the PWM modulation waveform are locked and fixed to the repetition period t of the clock signal S2, the movable edge M of the PWM modulation waveform becomes the signal of the digital signal S1. The PWM modulation waveform in which the position is modulated between the fixed edges K in accordance with the level change will be referred to as a one-sided PWM modulation waveform in the following description.

Furthermore, in the following description, the signal of the PWM modulation waveform obtained by inverting the phase of the signal of the one-side PWM modulation waveform will be used unless otherwise specified.
It shall be included in the modulation waveform.

That is, according to the pulse width modulation power amplifier 1, the digital signal S1 is converted into the one-side PWM modulation signal S3 corresponding to the signal level of the signal S1 and the PWM signal S3 through the pulse width modulation amplifier 3 by a negative value. The signal is converted into a related one-side PWM modulation signal S4. The signal S3 is supplied to the first power F through the pre-driver circuit unit 4.
The ET 6 is converted into a one-sided PWM modulation waveform drive signal S5 that can be turned on / off in a sufficiently stable state transiently, and this signal S4 is used to transiently drive the second power FET 7 via the pre-driver circuit unit 4. In a sufficiently stable state
Drive signal S of one-sided PWM modulation waveform that can be N / OFF driven
6 is converted.

Further, the first power FET 6 is driven by the drive signal S5, and the second power F6
ET7 is driven by this drive signal S6, and these F
From the connection point between the source of the first power FET 6 and the drain of the second power FET 7 in a state where the ETs 6 and 7 are alternately turned on and off, and the ground side, a PWM power signal S7 having a one-sided PWM modulation waveform is obtained. Is output.

Further, the PWM power signal S7 is
Through the power LPF section 8, frequency components outside the audible frequency band, such as the carrier signal component of the frequency of the clock signal S2, are eliminated. As an example, when the digital signal S1 is an audio signal, the digital signal S1 responds to a change in the signal level. The analog power signal S8 whose signal level changes by the demodulation is demodulated, and this power signal S8 is transmitted to the signal input terminals 9a. 9b, and the analog power signal S8 is reproduced as an audio signal.

Therefore, according to the pulse width modulated power amplifier 1 shown in FIG.
The pulse width modulation power amplifier 1 is configured as a class-class power amplifier, and the preceding stage of the pulse width modulation power amplifier 5 is also configured with a pulse signal processing system. There are advantages that can be configured.

[0024]

The P shown in FIG.
In the pulse width modulation power amplifier 1 to which the WM modulation device is applied, a signal having a constant frequency value which is the reciprocal of the repetition period t of the clock signal S2 becomes the carrier frequency of the PWM power signal S7, and the frequency of the clock signal S2 As an example, a high-frequency signal of about 500 KHz is selected. Therefore, in the class D power amplifier 5, a high-frequency current having a large peak value in the carrier frequency value flows, so that the power LPF section 8 is a single-stage L-type filter including a power choke coil 9 and a power capacitor 10. The configuration alone is not enough to eliminate the signal component of the carrier frequency from the analog power signal S8 to a degree that does not cause any problem.

Therefore, the power LPF section 8 is composed of a two-stage π-type or a multi-stage power LPF to make it strict, and furthermore, to devise a wiring pattern design so that all of the wiring through which the high-frequency current flows become thicker and shorter. At the same time, the wiring on the ground side through which this high-frequency current flows, such as the ground side of the class D power amplifier 5 and the ground side of the power LPF section 8, is collectively connected
By using a point ground, the leakage of the high-frequency current to peripheral circuits is prevented.

However, there is a problem that the implementation of such a carrier leakage prevention measure is considerably restricted in the circuit design of the pulse width modulation power amplifier 1.
Further, there is a problem that the cost is increased due to the strictness of the power LPF section 8.

The present invention has been made in view of such a conventional problem, and a high frequency current of the carrier frequency flowing through the class D power amplifier is supplied with a carrier frequency signal of a constant frequency synchronized with a constant repetition period t. By shifting the repetition period at random, the frequency distribution of the carrier is expanded, and the state in which the high-frequency current is generated at a constant frequency synchronized with a constant repetition period t is eliminated. It is an object of the present invention to solve the problem by reducing the peak value of the high-frequency current at the carrier frequency and easily implementing measures for preventing leakage of the high-frequency current at the carrier frequency.

[0028]

In order to solve the above-mentioned problems and to achieve the above object, a PWM modulation method according to the present invention employs a method of synchronizing with a repetition period of a clock signal generated by a clock signal generation means. And a signal waveform having a movable edge formed between the fixed edge generated by the first PWM conversion means and a movable edge whose position is changed in accordance with an input signal input to the first PWM conversion means. An output side of a first switching means that is controlled to be switched based on a first one-sided PWM signal having:
In synchronization with the repetition period of this clock signal, the second P
The position is changed between the fixed edge generated by the WM conversion means and the fixed edge in accordance with the input signal input to the second PWM conversion means, and
From the output side of the second switching means, which is switching-controlled based on a second one-sided PWM signal having a signal waveform in which a movable edge having a two's complement relationship with the PWM signal is formed. A two-sided PWM signal modulated according to the input signal can be supplied to the load, and the PWM signal obtained from the output of the first switching means and the PWM signal obtained from the output of the second switching means. By shifting each fixed edge of the PWM signal through the fixed edge shift means, the PWM signals on both sides are shifted.
It is characterized in that the peak value of the carrier signal of the signal is reduced.

Further, in the PWM modulator of the present invention, the position changes according to the input signal between the fixed edge locked in synchronization with the repetition period of the clock signal generated by the PWM clock signal generating means and the fixed edge. A first PWM conversion means for converting this input signal into a first one-sided PWM signal having a signal waveform having a movable edge formed thereon, a fixed edge locked in synchronization with a repetition period of the clock signal, and During the fixed edge, the position is changed according to the input signal and the first PW
A second PWM conversion means for converting the input signal into a second one-sided PWM signal having a signal waveform in which a movable edge having a two's complement relation with the M signal is formed, and the first PWM conversion; First switching means that is controlled by the first PWM signal obtained by the means, second switching means that is controlled by the second PWM signal obtained by the second PWM conversion means, Fixed position shift means for shifting the position of the fixed edge, wherein the output side of these first switching means and the second
Connected to the output side of the switching means to supply a double-sided PWM signal modulated in accordance with a change in the signal level of the input signal to the load, and the fixed position shift means. By these first
That the fixed edge of the PWM signal obtained from each of the switching means and the second switching means is shifted so that the peak value of the carrier signal of the two-sided PWM signal supplied to the load can be reduced. Features.

With the above-described configuration, in each of the PWM modulation method and the PWM modulation device according to the present invention, the carrier wave frequency output from the output side of the first switching means and the output side of the second switching means is used. Conventionally, the peak value of the component becomes sharp and high due to the fact that the frequency of this carrier is constant, and it becomes difficult to reduce the carrier leak to the load side. With the aim of solving this problem, it is possible to disperse the carrier frequency by enabling a random shift, reduce the peak value of the carrier frequency component, and reduce the leakage of the carrier frequency component to the load side. I have.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 1 to 6, the same parts as those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted. An embodiment will be described.

FIGS. 1 and 2 show an example of an embodiment of the present invention in which a PWM modulation method and a PWM modulation apparatus according to the present invention are applied to a pulse width modulation power amplifier. In FIG. FIG. 2 is a block diagram showing an example of an embodiment of a configuration of a main part of the amplifier, and FIG. 2 is a block diagram showing a part of the configuration of the pulse width modulation power amplifier 20 in more detail.

In the pulse width modulation power amplifier 20, the switching power amplifier part is BTL (bala).
This is shown as an example of an embodiment configured with a class D amplifier of the ncd (transformerless) type. That is, the pulse width modulation power amplifier 20 includes a first pre-driver circuit section 4, a first inverter 4A, a first class D power amplifier section 5, a first power LPF section 8, a speaker section 12, a master clock signal. Generator 13, power supply unit 1
4. It comprises a pulse width modulation amplifier 21, a second pre-driver circuit 22, a second inverter 22A, a second class D power amplifier 23, a second power LPF 24, and a timing signal generator 26. I have. 2 is a digital signal S1
Input terminals, 9a. 9b is a signal input terminal of the speaker unit 12, and 15 is a ground terminal of the power supply unit 14.

As shown in FIG. 2, the first and second D
Class power amplifiers 5 and 23 each include a first power FET 6
And the drain of the second power FET 7 is connected in series, the drain of the first power FET 6 is connected to the + DC power supply terminal + Vcc, and the second power FET 7
Are grounded.

Each of the power LPFs 8 and 24 has a power choke coil 9 and a power capacitor 10, and one end of the power choke coil 9 is connected to the first power FET 6.
And the drain of the second power FET 7 are connected to a connection midpoint in which they are connected in series, the other end of the choke coil 9 is connected to one end of a power capacitor 10, and the other end of the capacitor 10 is grounded. It is configured.

The connection point between the other end of the choke coil 9 of the first power LPF unit 8 and the power capacitor 10 on the power LPF unit 8 side is the signal input terminal 9a of the speaker unit 12.
The other end of the choke coil 9 of the second power LPF unit 24 and the midpoint of connection between the power capacitor 10 are connected to the signal input terminal 9b of the speaker unit 12.

Next, the operation of the pulse width modulation power amplifier 20 will be described with reference to FIGS.

The signal input terminal 2 is connected to the signal input terminal 21a of the pulse width modulation amplifier 21, the digital signal S1 is input to the pulse width modulation circuit 21A, and the signal of the digital signal S1 is passed through the pulse width modulation circuit 21A. P of one-sided PWM signal waveform pulse-width modulated according to level change
The WM signal S3 is converted to a pulse width modulation amplifier 22.
From the first output terminal 21b.

The pulse width modulation circuit 21A includes a digital PWM modulator capable of processing digital signals and a D / A
It consists of a converter. This pulse width modulation circuit 2
1A is a digital signal S1
The digital PWM signal is converted into a digital PWM signal via a WM modulator, and the digital PWM signal is supplied to a D / A converter and converted into an analog PWM signal. Then, the analog PWM signal is output from the pulse width modulation circuit 21A as the PWM signal S3. In addition, these digital PW
Since the configurations of the M modulator and the D / A converter are well known,
It is omitted in FIG.

The PWM signal S3, via the pre-driver circuit 4, turns the first power FET 6 of the first D-class power amplifier 5 on / off in a transiently sufficiently stable state.
The PWM signal S3 is converted into a drive signal S5 having a one-sided PWM signal waveform that can be F-driven.
The PWM signal S4, the phase of which is inverted via A, turns on / off the second power FET 7 of the power amplifying section 5 via the pre-driver circuit section 4 in a transiently sufficiently stable state.
This is converted into a drive signal S6 having a one-sided PWM signal waveform that can be F-driven.

The first power F of the power amplifier 5
ET6 is driven by the signal S5, the second power FET 7 of the power amplifier 5 is driven by the signal S6, and the PWM signals S5 and S6 control the FE.
T6 and T7 are alternately turned on and off, and are switched from between the connection point between the source of the FET 6 and the drain of the FET 7 and the ground side in accordance with the change in the pulse width direction of the PWM signals S5 and S6. The generated digital signal 1 as shown in 1B-3B of FIG.
A PWM power signal S7 having a one-sided PWM signal waveform that is pulse width modulated in accordance with the change in the signal level of S is output.

That is, when the signal level of the digital signal S1 is zero, as shown in FIG. 3A, 1B, the repetition period t
Are fixed in synchronization with a fixed clock signal S2, and a duty ratio 5 in which the movable edge M is fixed to the same point from each of the fixed edge K and the next fixed edge K.
The signal is output from the power amplification unit 5 as a signal having a waveform of 0%.

When the signal level of the digital signal S1 changes in a state of increasing from the zero level in the positive level direction, as shown by a right-pointing arrow → in FIG. 3A, 2B in FIG. 3A. , This movable edge M
Is moved to the right from the position shown in 1B of FIG. 3A, and in the state where the area of the PWM power signal S7, in the example of FIG. The PWM power signal S7 is output from the first class D power amplifier 5.

When the signal level of the digital signal S1 changes in a state of increasing from the zero level to the negative level, it is indicated by an arrow ← to the left in FIG. 3A in 3B of FIG. 3A. As shown in FIG. 3A, the movable edge M is moved leftward from the position shown in 1B of FIG. 3A, and is changed in a direction in which the area of the PWM power signal S7, in the example of FIG. In this state, the PWM power signal S7 is output from the first class D power amplifier 5.

The signal level of the digital signal S1 is set with a margin so that the movable edge M when the signal level of the digital signal S1 is maximum does not coincide with the fixed edge K.

The digital signal S1 is input to the pulse width modulation circuit 21B at the same time as the digital signal S1 is input to the pulse width modulation circuit 21A.
In the width modulation circuit 21B, pulse width modulation is performed in accordance with a change in the signal level of the digital signal S1 so that the PWM signal S3 having the one-sided PWM signal waveform has a 2's complement relationship. One-sided PWM
A PWM signal S11 having a signal waveform is generated.

Therefore, the change in the signal level of the digital signal S1 is transmitted to one side P via the pulse width modulation circuit 21B.
A PWM signal S1 having a one-sided PWM signal waveform pulse-width-modulated in a state synchronized with the PWM signal S3 having a WM signal waveform and in a two's complement relationship with the PWM signal S3.
The signal is converted to 1 and output from the second signal output terminal 21c.

The pulse width modulation circuit 21B comprises a digital PWM modulator capable of processing a digital signal, a digital complement converter capable of processing a digital signal, and a D / A converter. The digital signal S1 input to the pulse width modulation circuit 21B is converted to a digital PWM signal via the digital PWM modulator, and the digital PWM signal is input to the digital complement converter, and is converted via the digital complement converter. The PWM signal S3 is converted into a digital PWM signal having a two's complement relationship with the PWM signal S3, input to the D / A converter, converted into an analog PWM signal via the D / A converter, and converted into the PWM signal.
The signal is output from the pulse width modulation circuit 21B as a signal S11. These digital PWM modulators, digital complement converters, and D / A converters are well known, and are not shown in FIG.

The PWM signal S11, which is a PWM signal that has been subjected to pulse width modulation so as to have a two's complement relationship with respect to the PWM signal S3, is used as the first power of the second class D power amplifier 23. A drive signal S12 having a one-sided PWM signal waveform that can drive the FET 6 ON / OFF in a sufficiently stable state even transiently is converted via the pre-driver circuit unit 22. The PWM signal S11 is converted into a second inverter 22A.
The PWM signal S13 whose phase has been inverted through
One-sided P that can drive ON / OFF the second power FET 7 of the class D power amplifier 23 in a sufficiently stable state transiently
The drive signal S14 having the WM signal waveform is converted via the pre-driver circuit unit 22.

The first class D power amplifying section 23 side first
Is driven by the PWM signal S12, the second power FET 7 is driven by the PWM signal S14, and the FETs 6 and 7 are alternately turned on and off by the signals S12 and S14.
3C generated by switching from the connection point between the source of the FET 4 and the drain of the FET 5 and the ground side in accordance with the change in the pulse width direction of the PWM signals S12 and S14. , A PWM power signal S15 having a one-sided PWM signal waveform subjected to pulse width modulation in accordance with a change in the signal level of the analog signal S1 is output.

That is, when the signal level of the digital signal S1 is zero, the clock signal S2 having a constant repetition period t as shown in FIG.
Fixed edge K locked in synchronization with movable edge M
Are fixed to the same point from each of the fixed edge K and the next fixed edge K as a signal of a waveform having a duty ratio of 50%,
This PWM power signal S15 is supplied to the second class D power amplifier 23.
Output from

When the signal level of the digital signal S1 is changed in a state of increasing from the zero level in the positive level direction, the PWM pulse width modulated in accordance with the change in the signal level of the analog signal S1. The signal S15 moves the movable edge M to the left from the position shown in FIG. 3B at 1C, as indicated by the leftward arrow ← in 2C in FIG. 3B, and the PWM power signal S
The PWM power signal S15 in a state where the area of the 15 positive-direction signal waveforms is changed in a decreasing direction is output from the second class D power amplifying unit 23.

When the signal level of the digital signal S1 changes in a state of increasing from the zero level to the negative level, as shown by the right arrow → in FIG. This PWM power signal is moved rightward from the position shown by 1C in FIG. 3B, and is changed in a direction in which the area of the PWM power signal S15, in the example of FIG. 3B, the area of the positive signal waveform increases. S15 is output from the second class D power amplifier 23.

Next, the BTL shown in FIG. 1 and FIG.
In the connection circuit, a portion formed by connecting each of the first power LPF unit 6, the speaker unit 12, and the second power LPF unit 23 in series is the second power output from the first power switching circuit unit 5. 1 PWM power signal S7 and the second PWM output from the second power switching circuit 26.
When the load is applied to the M power signal S15,
FIGS. 4A to 4C show timing charts of the waveforms of the PWM power signals given from the first PWM power signal S7 and the second PWM power signal S15 for this load.
And will be described.

In FIGS. 4A to 4C, the signal levels indicated by -0 are the signals S7, S15 and (S7-S1).
5) represents the 0 level of each signal level, and the region above the 0 level represents the signal level of positive polarity.
The area below the level represents the signal level of the negative polarity.

The directions indicated by the horizontal arrows in FIGS. 4B and 4C indicate the direction of change of each of these signal waveforms in accordance with the change in the signal level of the digital signal S1. Is the master clock signal generator 13
Represents the repetition period t of the constant clock signal S2, and K represents the rising edge of the PWM power signal S7 of the one-sided PWM waveform and the rising edge of the PWM power signal S15 of the one-sided PWM waveform, respectively. The edge is a fixed edge K whose phase is locked in synchronization with the clock signal S2. M is the PWM power signal S7, the PWM power signal S15, and the signal (S7-S15).
Of the movable edge of FIG.

FIG. 4A shows these PWM signals when the signal level of the digital signal S1 input to the signal input terminal 1 is zero.
The respective signal waveforms of the power signal S7 and the PWM power signal S15 are shown. In this case, these PWM power signals S7 and P
The difference (S7-S15) of the WM power signal S15 becomes 0,
Therefore, the power supplied to the load side also becomes zero.

FIG. 4B shows the PWM power signal S7, when the signal amplitude level of the digital signal S1 changes in the range from zero to the + direction and reaches the maximum modulation degree, for example.
PWM power signal S15 and PWM power signals S7 and S15
Respectively (S7-S15).
As is apparent from FIG. 4B, these power signals S7 and S15, which are one-sided PWM waveforms having a two's complement relationship with each other, are provided.
The signal waveform of the difference power signal (S7-S15) is represented by the time center (t / t) of the waveform of the difference power signal (S7-S15).
With respect to the position 2), the left and right signal waveform widths change in opposite directions while maintaining a symmetric state in accordance with the change in the signal level of the digital signal S1, and the power signal (S7-S15) having this difference ) Is a PWM power signal having a PWM waveform on both sides with the peak value kept on the positive side. And this both sides P
The waveform of the PWM power signal of the WM waveform is characterized in that there is no fixed edge K locked in synchronization with the repetition period t of the clock signal S2 existing in the power signals S7 and S15.

FIG. 4C shows the PWM power signal S7, the PWM power signal S15, and the power signals S7 and PWM when the amplitude level of the signal S1 changes from zero to the negative direction and reaches the maximum modulation degree, for example. Power signal S15
5 shows respective signal waveforms of the power signal (S7-S15) having the difference between. As can be seen from FIG. 4C, each has a one-sided PWM.
These power signals S7 and PWM power signals S, which are waveform signals,
The signal waveform of the 15 difference power signal (S7-S15) has a signal level of the signal S1 with respect to the position of the time center (t / 2) of the waveform of the difference power signal (S7-S15). In response to the change, the left and right signal waveform widths change in opposite directions while maintaining a symmetrical state, and the peak value of the difference power signal (S7-S15) is maintained on the negative side. It becomes a modulation waveform. And P of the PWM waveform on both sides
The waveforms of the WM power signal include these power signals S7 and S15.
Is characterized in that there is no fixed edge K locked in synchronization with the repetition period t of the clock signal S2 that has existed.

Therefore, according to the pulse width modulated power amplifier 20 shown in FIGS. 1 and 2, the range excluding the range of the signal waveform width at the maximum modulation degree of the difference power signal (S7-S15), that is, FIG. 4, the PWM power signals S7 and S15 are within a range B excluding the dashed line shown by the dashed line.
Of the PWM signal on both sides based on the power signal (S7-S15) of the difference even if the respective fixed edges K are shifted.
There is an advantage that the waveform of the WM power signal is not affected.

Accordingly, in the present embodiment, a timing signal generator 26 is provided as shown in FIG. 1 as an example, and the signal of this difference at the maximum modulation degree of this difference signal (S7-S15) is provided from this signal generator 26. In a range B excluding the range of the amplitude of the signal generator 26, a timing shift signal S16 having a shift amount in the time axis direction (horizontal axis direction in FIG. 4), and the shift amount changes in a random state, And is generated in synchronization with the repetition period of the clock signal S2. The timing shift signal S16 is supplied to each of the first class D power amplifier 5 and the second class D power amplifier 23, and the position of the fixed edge K of each of the PWM power signal S7 and the PWM power signal S15 is determined. Within the range B can be controlled by the timing signal generator 26 so as to be randomly changed in synchronization with each other.

That is, according to this example, the fixed edge K of the PWM power signal S7 and the fixed edge K of the PWM power signal S15
Can be controlled so as to be shifted in a random state in synchronization with the repetition period t of the clock signal S2.

Therefore, when the fixed edge K is fixed, the carrier signal generated in synchronization with the repetition period t of the clock signal S2 is a single-spectrum carrier signal, but the PWM power signal S7 is fixed. Edge K
By making the positions of the fixed edges K of the PWM power signal S15 randomly shifted in this way, the frequency spectrum is dispersed and the peak value of the carrier frequency signal is reduced. This has the advantage that measures to reduce high-frequency current leakage at the carrier frequency, which has been considered as an issue, are facilitated.

Further, the LPF section 8 and the LPF
Since the power signal supplied to the load side of the section 24, in this example, the speaker section 12, is generated based on the PWM power signal having the PWM waveform on both sides, the amplitude level of the digital signal S1 is either positive or negative. Changes in the direction of
There is an advantage that secondary distortion due to M modulation does not occur.

In the embodiment of the present invention shown in FIG. 1, the timing shift signal S16 is supplied to each of the first D-class power amplifier 5 and the second D-class power amplifier 23. , PWM power signal S7 and PWM power signal S15
Are controlled by the timing signal generator 26 such that the positions of the fixed edges K are randomly changed in synchronization with each other. However, in the example of the embodiment of the present invention, the timing shift signal S16 shown in FIG. 1 is supplied to each of the pre-driver circuit unit 4 and the second pre-driver circuit unit 22, and the PWM power signal S7 and the The timing signal generator 26 controls the pre-driver circuit unit 4 and the second pre-driver circuit unit 22 so that the positions of the fixed edges K of the PWM power signal S15 are randomly changed in synchronization with each other. You may make it control. Also, the timing shift signal S16 is supplied to the pulse width modulation amplifier 21 so that the timing signal is changed so that the positions of the fixed edges K of the PWM power signal S7 and the PWM power signal S15 are randomly changed in synchronization with each other. Of course, the generator 26 may control each of the pulse width modulation circuits 21A and 21B constituting the pulse width modulation amplifier 21.

In the example shown in FIG. 1, it is a matter of course that the pulse width modulation power amplifier can employ various other configurations without departing from the spirit of the present example.

Next, an example of an embodiment of the timing signal generator 26 shown in FIG. 1 according to the present invention will be described with reference to FIG.

FIG. 5A shows an example in which the timing signal generator 26 is composed of a function calculator 27, a counter 28 and a CPU 30. Reference numeral 28A denotes a clock signal having a repetition cycle faster than that of the clock signal S2, for example, an input terminal of a clock signal S17 having a clock frequency 100 times higher than that of the clock signal S2, and 28B denotes an output terminal of the timing shift signal S16. Note that this clock signal S
17 is generated by multiplying the clock signal S2 as an example.

Next, the operation of the timing signal generator 26 will be described. A clock signal S2 having a constant repetition period t input from the master clock signal generator 13 to the input terminal 29A is supplied to the function calculator 27. Then, the clock signal S is calculated through the function calculator 27.
The random signal S18 is a random signal S18 having a function value that randomly changes with reference to the reference time 2, or the random signal S18 is a dither value that randomly changes in the time axis direction with the clock signal S2 as the reference time based on the function value. It is generated for each repetition period of the clock signal S2.

The random signal S18 having the function value or the dither value is supplied to the counter 28, and the counter 28 is set at the start point of the random signal S18 and reset at the end point of the random signal S18. Via a counter 28 which is set and reset in this way according to the random duration of the value,
Clock signal S17 input from signal input terminal 28A
The shift amount n is generated based on a random count value obtained by counting, and the shift amount n is input to the CPU 30.

The shift amount n is determined via the CPU 30 in accordance with the routine shown in FIG. 6, and a timing shift signal S16 whose timing is randomly shifted based on the clock signal S2 is generated in accordance with the result of this determination. You. The timing shift signal S16 is output from the signal output terminal 28B of the timing signal generator 26, and is input to each of the first D-class power amplifier 5 and the second D-class power amplifier 23. The timing of the fixed edge K of the PWM power signal S7 generated by the first class D power amplifier 5 and the timing of the fixed edge K of the PWM power signal S15 generated by the second class D power amplifier 23 are shifted by this timing shift. It is shifted randomly by the signal S16.

As means for shifting the fixed edge K of each of the PWM power signals S7 and S15, FIG.
In the course of the circuit in which the drive signal S5 is supplied to the gate of the first power FET 6 on the side of the first class D power amplifier 5,
The drive signal S6 indicated by S6 in FIG.
In the middle of the circuit supplied to the gate of the power FET 7, the drive signal S12 shown at S12 in the figure is supplied to the gate of the first power FET 6 on the side of the second class D power amplifier 23, and The drive signal S14 shown in FIG.
Inserts a phase shift circuit into each of the circuits supplied to the gate of the second power FET 6 on the amplification unit 23 side,
A timing shift signal S is applied to each of these phase shift circuits.
16 on the basis of the timing shift signal S16 and the respective fixed edges K of the PWM power signals S7 and S15.
Shift. Since the phase shift circuit itself may be any known phase shift circuit, it is omitted in FIG.

Next, another example of the timing signal generator shown in FIG. 1 according to another embodiment of the present invention will be described with reference to FIG. A description will be omitted.

The timing signal generator shown in FIG. 5B is configured by replacing the counter 28 in the timing signal generator 26 shown in FIG. 5A with an analog timing generator 31 and a selector 32, and the others are shown in FIG. 6A. The configuration is the same as that of the timing signal generator 26.

The clock signal S2 is input to the analog timing generator 31, and the analog timing generator 3
, N = 1 to n = n (where n is 1/100, 2/100, 3/100... Of the repetition period of the clock signal S2).
... N / 100) are generated, and each of these timing shift values is input to the selector 32 in parallel.

At the same time as the timing signal is input to the selector 32, the random signal S18 generated in the function calculator 27 is input to the selector 32, and the random shift signal S18 out of these timing shift values n = 1 to n = n One is selected based on the random value of the random signal S18, and the shift amount n is randomly generated. And CPU
At 30, the shift amount n is determined according to the routine shown in FIG. 6, and the result of this determination is generated based on the clock signal S2 to generate a timing shift signal S16 in which the timing from this reference is randomly shifted. , The signal output terminal 28 of the timing signal generator 26
B, the first D-class power amplifier 5 and the second D
5A, the timings of the fixed values K of these signals S7 and S15 are randomly shifted, as described with reference to FIG. 5A.

Therefore, it can be easily understood that the same operation and effect as in the example of FIG. 5A can be obtained in the example of FIG. 5B.

In the examples shown in FIGS. 5A and 5B, it is a matter of course that the timing signal generator 26 can have various other configurations without departing from the spirit of the present example.

Next, the timing shift signal S1 by the CPU 30 provided in the timing signal generator 26 is provided.
An example of the generation routine of No. 6 will be described in detail with reference to FIG.

When the generation program of the timing shift signal S16 of the CPU 30 built in the timing signal generator 26 starts, in step ST01, these PWM power signals S7 and PW shown in FIG.
The position of the movable edge M at the maximum modulation degree of each difference signal (S7-S15) of the M power signal S15 is determined. Then, the process proceeds to step ST02, and the maximum shift amount max and the minimum shift amount min are obtained based on the information on the position of the movable edge M obtained by the calculation. And step ST03
, The shift amount n is obtained as described with reference to FIGS. 5A and 5B, and the process shifts to step ST04, where the shift amount n is compared with the minimum shift amount min. If it is greater than or equal to min,
The process proceeds to step ST05, where the shift amount n is compared with the maximum shift amount max. If the shift amount n is equal to or smaller than the maximum shift amount max, the shift amount n is set as the timing shift signal S16. The signal is output from a signal output terminal 28B of the generator 26.

On the other hand, if it is determined in step ST04 that the shift amount n is not equal to or larger than the minimum shift amount min, the shift amount is set to the minimum shift amount min, and the timing shift signal S16 is set. Output from the signal generator 26. Step S
If it is determined at T05 that the shift amount n is neither equal to nor smaller than the maximum shift amount max, the shift amount n is set to the maximum shift amount max, and the signal of the timing signal generator 26 is set as the timing shift signal S16. Output from the output terminal 28B.

The routine from step ST01 to the output of the shift amount n is repeatedly executed at each generation time of the clock signal S2 indicated by A in FIG. 4C.
From the signal output terminal 28B of the timing signal generator 26, the timing shift signal S16 in which the shift amount n is randomly set is sent from the first class D power amplifier 5 and the second D
And the first power FET 6 and the second power FET 7 of each of these power amplifiers.
Is shifted in the time axis direction on the side of the fixed edge K of the power signal flowing through in accordance with the timing shift signal S16.

In the method of generating timing shift signal S16 in timing signal generator 26 shown in FIG.
It may be assigned to the routine following T02 and ST03. Further, it is a matter of course that the position of the movable edge may be obtained in this step ST01 for each repetition cycle of the clock signal S2. The generation routine of the timing shift signal S16 in the timing signal generator 26 shown in FIG. 6 is shown as an example. Therefore, as a routine for achieving the same object as the method of generating the timing shift signal S16 in the timing signal generator 26, various other routines can be used without departing from the spirit of the present invention.

The positions of the fixed edges K of these signals S7 and S15 are within the range indicated by B in FIG. 4A (excluding the positions of the movable edges M on both sides of the signal (S7-S15) of the PWM waveform on both sides). Of course, it may be made to shift randomly over (range).

In this embodiment, an example has been described in which each repetition cycle t of the clock signal S2 is set as a repetition cycle for generating the timing shift signal S16. However, in the present invention, the timing shift signal generated intermittently according to the appearance probability expressed by a predetermined mathematical formula is used as the timing shift signal.
As an example, the repetition cycle of the timing shift may be intermittently repeated not every repetition cycle t but every certain cycle t. It is needless to say that the number of the repetition periods t that are skipped may be set at random.

Further, as an example of the embodiment of the present invention, an example in which a speaker section is used as a driven load has been described. However, the present invention is not limited to the example in which the speaker unit is used as a load, but may be a load of various forms such as a motor such as an induction motor, a deflection coil of a cathode ray tube, and carrier wave carrier leakage may be a problem. Needless to say, the present invention can be widely applied to a PWM modulator used for supplying a drive signal to a simple load.

[0087]

According to the present invention, when a carrier power signal obtained by PWM-modulating a carrier with an input signal is supplied to a load, the carrier is repetitively changed in a state where the repetition period of the frequency of the carrier is randomly changed. Since the power signal is supplied to the load, the carrier frequency spectrum of the carrier power signal can be dispersed, so that the peak value of the carrier frequency signal can be reduced, which has been a problem. There is an advantage that the leakage of the carrier frequency component to the load side can be easily prevented.

[Brief description of the drawings]

FIG. 1 is a circuit block for explaining an example in which the present invention is applied to a pulse width modulation power amplifier.

FIG. 2 is a circuit block diagram for explaining details of the pulse width modulation power amplifier.

FIG. 3 is a signal waveform diagram for explaining an operation of the pulse width modulation power amplifier.

FIG. 4 is another signal waveform diagram for explaining the operation of the pulse width modulation power amplifier.

FIG. 5 is a circuit block diagram illustrating an example of a timing signal generator according to the present invention.

FIG. 6 is a flowchart for explaining the operation of the timing signal generator.

FIG. 7 is a circuit block diagram and a signal waveform diagram for explaining a conventional pulse width modulation power amplifier.

[Explanation of symbols]

1 ... Pulse width modulation power amplifier, 2 ... Input terminal of analog signal S1, 3 pulse width modulation amplifier ... 4
... Pre-driver circuit section, 5 (23)... First (second) D-class power amplifier section, 8 (23).
Unit, 12 speaker unit, 26 timing signal generator, 27 function calculator, 28 counter,
30 CPU, S1, digital signal, S1, S
2 ... clock signals S2, S3 ... PWM signals, S7
... PWM power signal, S11 PWM signal, S1
5: PWM power signal, K: fixed edge

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (10)

[Claims] An input to said first PWM conversion means between a fixed edge generated by said first PWM conversion means and said fixed edge in synchronization with a repetition period of a clock signal generated by said clock signal generation means. An output side of a first switching means that is controlled to be switched based on a first one-sided PWM signal having a signal waveform in which a movable edge whose position is changed according to an input signal to be changed, and a clock signal of the clock signal. In synchronization with the repetition period, the second
The position is changed according to the input signal input to the second PWM conversion means between the fixed edge generated by the PWM conversion means and the first PWM signal. From the output side of the second switching means, which is switching-controlled based on a second one-sided PWM signal having a signal waveform with a movable edge having a complement relation of A fixed edge of the PWM signal obtained from the output of the first switching means and of the PWM signal obtained from the output of the second switching means, so that a modulated double-sided PWM signal can be supplied to the load; The peak value of the carrier signal of the two-sided PWM signal is reduced by shifting the position of the carrier signal through fixed edge shift means. PWM modulation how to. 2. The PWM modulation method according to claim 1, wherein said first PWM conversion means and said second PWM
Each of the M conversion means converts the input signal into a digital PWM signal by digital signal processing, and converts each of these digital PWM modulated signals into an analog P
A PWM modulation method comprising a D / A converter that converts a signal into a WM modulation signal and outputs the converted signal. 3. The PWM modulation method according to claim 1, wherein a PWM signal obtained from an output side of said first switching means and a PWM signal obtained from an output side of said second switching means are fixed. A repetition period of a clock signal, which is a reference of an operation of the fixed edge shift unit for shifting an edge position, is set to a repetition period earlier than a repetition period of a clock signal generated by the clock signal generation unit. PWM modulation method. 4. The PWM modulation method according to claim 1, wherein said control means controls said fixed edge shift means.
Shift timing information for shifting the fixed edge via the fixed edge shift means is selected and controlled from each of a plurality of pieces of shift timing information generated by an analog timing generator and having different timings. A PWM modulation method comprising: 5. The PWM modulation method according to claim 1, wherein shift timing information for shifting the fixed edge via the fixed edge shift means is dither information in a time axis direction. Modulation method. 6. The PWM modulation method according to claim 1, wherein the shift timing information for shifting the fixed edge via the fixed edge shift means includes a clock signal serving as a reference of an operation of the fixed edge shift means. A PWM modulation method, wherein the shift timing information is continuously generated according to a repetition period. 7. The PWM modulation method according to claim 1, wherein the shift timing information for shifting the fixed edge via the fixed edge shift means is intermittent in accordance with an appearance probability represented by a predetermined mathematical expression. A PWM modulation method, characterized in that the information is timing shift information generated in (1). 8. A fixed edge locked in synchronization with a repetition period of a clock signal generated by a PWM clock signal generating means, and a movable edge whose position is changed according to an input signal is formed between the fixed edge. First PWM conversion means for converting the input signal to a first one-sided PWM signal having a signal waveform, and a fixed edge locked in synchronization with a repetition period of the clock signal and the input between the fixed edge. A second PWM conversion for converting to a second one-sided PWM signal having a signal waveform whose position is changed in accordance with the signal and in which a movable edge having a two's complement relation to the first PWM signal is formed; Means, first switching means that is switching-controlled by a first PWM signal obtained by the first PWM conversion means, and the second PWM. The second switching means is controlled by the second PWM signal obtained by the M conversion means, and comprises a fixed position shifting means for shifting the position of the fixed edge, and an output side of the first switching means. By connecting a load between the output sides of the second switching means, a double-sided PWM signal modulated in accordance with the input signal can be supplied to the load, and the first PWM signal can be supplied to the load.
The PWM signal obtained from the output side of the switching means and the P signal obtained from the output side of the second switching means
PWM modulation wherein the fixed edge shift means shifts each of the fixed edges of the WM signal to reduce the peak value of the carrier signal of the two-sided PWM signal supplied to the load. apparatus. 9. The PWM modulation apparatus according to claim 8, wherein said first PWM conversion means and said second PWM
PWM conversion means for performing PWM conversion of the input signal by digital signal processing and outputting the converted signal as a digital PWM modulation signal;
PWM having a D / A converter for converting each of the M modulated signals into an analog PWM modulated signal
Modulation device. 10. The PWM modulator according to claim 8, wherein said load is a motor.
WM modulator.