JP2002319965A - Data selection output device and data communication system provided with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To respectively cope with cases where the switching of data transmission paths is needed such as a failure of a transmission path and the switching of the data transmission paths is not needed such as congestion of the transmission path. SOLUTION: This data selection output device is provided with a transmission path detecting means 5 for detecting a transmission path by referring to a cell header, a switching mean 7 for switching states of a mode storage register 8 in accordance with detection results by the transmission path detecting means 5, a detection results storage register 6 for storing the detection results of the transmission path detecting means 5, a CPU 4 for referring to the detection results when the timer including the detection results stored in the detection results storage register 6 performs timeout and switching states of the mode storage register 8 in accordance with the detection results, and a VP selection filter 9 for selectively outputting either cell transmitted on transmission lines 40 and 50 according to the state of the mode storage register 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data selection / output device and a data communication system having the same.
The present invention relates to a data selection / output device for asynchronous transmission mode transmission of data having burst characteristics and a data communication system including the same.

[0002]

2. Description of the Related Art Hitherto, in order to realize high reliability of data communication, a network is provided with two routes of transmission paths. Then, upon detecting that a failure has occurred in the transmission path that is transmitting data at normal times, the transmission path that transmits data is changed from the failed transmission path to
Switching to another transmission path.

Here, the asynchronous transfer mode (Asynchronous
In Transfer Mode (ATM) transmission, OAM (operatio)
n and maintenance) cells were used to detect the occurrence of a failure in the transmission path.

On the other hand, in a private network including a network having a digital image transmission device employing an encoding system such as MPEG2, data transmission using OAM cells is difficult in terms of system realization and transmission efficiency. Some are not done.

[0005] In such a network, in a constant bit rate (CBR) transmission, C
Utilizing the property that the transmission speed of BR transmission data is constant, if a cell transmitted from a data transmitter within a predetermined time is not received by the data receiver, the transmission transmitting the data is performed. The transmission path can be switched assuming that a failure has occurred in the path.

[0006]

However, the conventional technique has a variable bit rate (VBR).
In data communication having a burst property, such as transmission and transmission of control data into cells, the data transmission speed is not constant. Therefore, the transmission path must be switched in the same manner as data communication in CBR transmission. Is difficult.

That is, since the data transmission speed is not constant, it is difficult to set the length of the predetermined time, and even if the predetermined time can be set, for example, When congestion occurs on the transmission line,
In many cases, the cell does not arrive at the data receiver side within the predetermined time, so that the transmission path is switched even if no failure has actually occurred in the transmission path. May occur and data may not be properly transmitted to the data receiver.

Accordingly, the present invention provides a method for switching data transmission paths, such as a failure in a transmission path, and a method for transmitting data, such as congestion of a transmission path, so that data is properly transmitted to a data receiver. It is an object of the present invention to be able to cope with a case where switching of a transmission path is unnecessary.

[0009]

In order to solve the above-mentioned problems, the present invention is directed to a data transmitter connected to a data transmitter via a plurality of transmission paths in which transmission times of cells are uniquely varied. A data selection and output device for selecting one of cells transmitted through each transmission path and outputting the selected cell to a data receiver, wherein the cell is a cell that is transmitted from the data transmitter through a plurality of transmission paths. A first output unit that outputs a cell transmitted through the transmission path having the shortest transmission time to the data receiver; and a cell that is input through a transmission path having a transmission time shorter than the transmission path having the shortest transmission time. A second output means for selecting the cell and outputting the selected cell to the data receiver; and transmitting the cell when the cell is continuously input through the transmission path having the slow transmission time. The cells transmitted is the transmission time, characterized in that instead of the output of the cell from the transmission path which is the shortest and a third output means for outputting to the data receiver.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

[Explanation of Configuration] FIG. 1 is a block diagram showing a schematic configuration of a data communication system according to an embodiment of the present invention. FIG. 1 shows a data transmitter 10 and a data receiver 3.
The figure shows a state in which the data selection output device 20 is provided between 0 and 0.

Data transmitter 10 and data selection output device 2
0 is connected via transmission lines (paths) 40 and 50, and the data selection / output device 20 and the data receiver 30 are connected via a transmission line 60.

From the data transmitter 10, transmission lines 40, 5
0, each cell of the same data is transmitted in two systems, one of the data input through the transmission lines 40 and 50 is selected by the data selection output device 20 by a method described later, and output to the data receiver 30 through the transmission line 60. I am trying to do it.

Therefore, even when a failure occurs in one of the transmission lines 40 and 50, the transmission of data is maintained by changing the transmission path, and the transmission lines 40 and 50 are maintained.
In the case where congestion occurs only in one of 0, no instantaneous interruption occurs without changing the data transmission path.

Here, the time required for the cells transmitted from the data transmitter 10 to be input to the data selection and output device 20 inherently varies due to the slightly different lengths of the transmission lines 40 and 50. ing. Hereinafter, in the present embodiment, for example, the transmission time on the transmission line 40 side is
Description will be made assuming that the transmission time is shorter than the transmission time on the 0 side.

FIG. 2 is a block diagram showing the internal configuration of the data selection and output device 20 of FIG. FIG. 2 shows transmission line 4
Input means 1 for inputting cells transmitted through 0,50
And a virtual channel extension (V) for passing only valid cells among the various cells input by the input means 1.
C) Selection filter 2, transmission path detection means 5 for detecting a transmission path by referring to the header of the valid cell which has passed VC selection filter 2, and mode storage register 8 according to the detection result by transmission path detection means 5. The switching means 7 for switching the state, the detection result storage register 6 for storing the detection result by the transmission path detection means 5, and the time when the timer containing the detection result stored in the detection result storage register 6 times out are referred to. A CP that switches the state of the mode storage register 8 according to the detection result, allocates the VCI, and stores the result in the VCI status storage register 3
U4 and the transmission line 4 according to the state of the mode storage register 8.
A virtual path (VPI) selection filter 9 for selectively outputting a cell that has transmitted any one of 0 and 50 is shown.

FIG. 3A is a conceptual diagram of the configuration of the detection result storage register 6 of FIG. As shown in FIG. 3A, in the present embodiment, the detection result storage register 6 is configured to have two banks of the A surface and the B surface. Bank is CP
Switching is performed by a toggle bit output at the time of access from U4.

For this reason, if the CPU 4 accesses the detection result storage register 6 while the bank that can be read / written from the CPU 4 is currently the A-side bank, the CPU 4 refers to the A-side bank and sets the toggle bit. Accordingly, the next time the CPU 4 accesses the detection result storage register 6, the CPU 4 is switched so as to refer to the B-side bank.

By the way, if the bank accessible from the CPU 4 is currently the A-side bank, the detection result of the transmission path detecting means 5 can be stored in the B-side bank.
If the bank accessible from the PU 4 is currently the B-side bank, the detection result of the transmission path detecting means 5 can be stored in the A-side bank.

Here, for example, when a transmission path of a cell is detected by the transmission path detecting means 5, the register value of the bank which can be stored by the transmission path detecting means 5 is "0".
From "1" to "1" so that it can be determined whether or not the cell is properly input during the access of the CPU 4. The register value of each bank may be reset to “0” when the bank is switched, although it depends on the setting of the time required for the timer built in the CPU 4 to time out.

FIG. 3B is a conceptual diagram of the configuration of the mode storage register 8 of FIG. FIG. 4 is a state transition diagram of the register values stored in the mode storage register 8 shown in FIG. As shown in FIG. 3B, in the present embodiment, the register value stored in the mode storage register 8 is 2
It's a bit.

As shown in FIG. 4, in the present embodiment, a first mode (S1): a mode in which cells transmitted through the transmission line 40 are set to be output to the data receiver 30, Mode (S2): A mode in which the cell transmitted through the transmission lines 40 and 50 and the cell previously input to the detection result storage register 6 are set to be output to the data receiver 30, the third mode (S3) ): A mode in which a cell transmitted through the transmission line 50 is set to be output to the data receiver 30 is prepared.

Here, for example, mode storage register 8
When the upper bit of the register value stored in the cell is "1", the cell input to the detection result storage register 6 among the cells transmitted through the transmission lines 40 and 50 is output to the data receiver 30 ( (Second mode), and when the upper bit is “0”, if the lower bit is “0”, the cell transmitted through the transmission line 40 is output to the data receiver 30 (first mode). Mode), and if the lower bit is "1", it indicates that the cell transmitted through the transmission line 50 is set to be output to the data receiver 30 (third mode). ing.

When resetting the VCI status storage register 3 and the detection result storage register 6 to "0", a power-on reset is performed. In addition, the mode storage register 8 is set to “1” by the power-on reset, and as a result, the state becomes the second mode.

[Explanation of Operation] First, the CPU 4
And VCI allocation. Specifically, any V
Assignment is made as to whether P and VC should be used as data transmission paths required for various controls of the data communication system main unit or as transmission paths of valid cells. The result of the assignment is stored in the VCI status storage register 3.

The CPU 4 turns on a built-in timer so that the detection result storage register 6 can be periodically referred to. Further, the mode storage register 8 is set to the first mode here (FIG. 4 (S2)) so that the cells transmitted from the data transmitter 10 via the transmission line 40 can be output to the data receiver 30. deep. Specifically, both the upper bit and the lower bit of the mode storage register 8 are set to “0”.

[Description of Normal Operation] In this state, when cells are transmitted from the data transmitter 10 through the transmission lines 40 and 50, these are input by the input means 1. Various cells input by the input means 1 are output to the VC selection filter 2.

The VC selection filter 2 allows only valid cells among the cells from the input means 1 to pass based on the register value stored in the VCI status storage register 3.
The valid cell is output to the transmission path detecting means 5 and the VP selection filter 9 in parallel.

Since the VP selection filter 9 is set to the first mode, only the cells transmitted through the transmission line 40 are passed, and the data receiver 3 is transmitted through the transmission line 60.
To output to 0. Cells transmitted through the transmission line 50 are discarded.

The transmission path detecting means 5 refers to the header of the cell that has passed through the VC selection filter 2 and detects through which of the transmission lines 40 and 50 the cell has been transmitted. Normally, each cell transmitted through the transmission lines 40 and 50 is sequentially input to the transmission path detecting means 5 with a shift of about several μs. Therefore, the detection result indicating that the cell from the transmission line 40 has been input first is output to the detection result storage register 6 and the switching unit 7 in parallel, and the detection result indicating that the cell from the transmission line 50 has been input is subsequently output. Output in parallel.

The detection result storage register 6 stores the detection result from the transmission path detecting means 5. Normally, for example, the register value of the A-side bank in FIG.
In both cases, “0” is switched to “1”.

The switching means 7 refers to the mode storage register 8 with the input of the detection result by the transmission path detecting means 5 as a trigger. When the upper bit of the register value of the mode storage register 8 is “1”, it indicates the second mode. Therefore, the upper bit of the register value of the mode storage register 8 is switched to “0” according to the detection result. , To the register value indicating the first or third mode. Here, since the mode storage register 8 stores a register value indicating the first mode, no switching is performed.

When the turned-on timer times out, the CPU 4 refers to the detection result storage register 6 and also refers to the mode storage register 8. When the upper bit of the register value of the mode storage register 8 is “0”, it indicates the first or third mode. Therefore, the first mode is set according to the detection result stored in the detection result storage register 6.
Alternatively, the setting of the third mode is held, or the mode is switched to the second mode.

When the CPU 4 refers to the detection result storage register 6 immediately after the detection result by the transmission path detection means 5 is stored in the A-side bank of the detection result storage register 6,
The CPU 4 refers to the B-side bank. Since the register values of the B-side bank are in the initial state, they are both held at "0", and it is determined that data is not transmitted from the data transmitter 10. On the other hand, the register value of the mode storage register 8 is such that the upper bit is “0” and the lower bit is “0”, indicating the first mode. Is switched to “1”.

Subsequently, the transmission line 4
When the next cell is transmitted through 0, 50, the transmission line 4
Each cell is output to the transmission path detecting means 5 and the VP selection filter 9 in the same manner as described above unless congestion or failure occurs in 0 and 50.

Here, since the mode is set to the second mode, the VP selection filter 9 selects the previously input cell and outputs it to the data receiver 30 through the transmission line 60.
Specifically, the cell transmitted through the transmission line 40 is output to the data receiver 30.

On the other hand, the transmission path detecting means 5
It is detected that the cell has been transmitted through both 0 and 50, and the detection result is output in parallel to the detection result storage register 6 and the switching means 7.

The detection result storage register 6 stores the detection result from the transmission path detecting means 5. This time, FIG.
Is switched from “0” to “1” on both the transmission lines 40 and 50.

The switching means 7 refers to the mode storage register 8 with the input of the detection result indicating that a cell has been input from the transmission line 40 by the transmission path detecting means 5 as a trigger. Here, since the upper bit of the register value of the mode storage register 8 is “1” and indicates the second mode, the upper bit of the register value is set to indicate the first or third mode according to the detection result. Is switched to “0”.

The detection result mode storage register 8 stores a first detection result indicating that a cell from the transmission line 40 has been input.
The mode is switched to indicate the mode. On the other hand, the transmission path 50
The mode is switched to indicate the third mode according to the detection result indicating that the cell from has been input. In this case, the mode is switched to the first mode at normal times, that is, since no congestion or failure occurs in the transmission line 40, based on a detection result indicating that a cell from the transmission line 40 has been input.

Even when the CPU 4 refers to the detection result storage register 6 and the mode storage register 8, the detection result storage register 6 stores the cell transmitted through the transmission line 40 and the cell transmitted through the transmission line 50. Since the fact that the input has been made earlier is stored (FIG. 4A), the register value on the transmission line 40 side becomes "1", and the mode setting is not changed and the first mode is held.

Actually, it takes some time from when the CPU 4 refers to the detection result storage register 6 to when the mode stored in the mode storage register 8 is changed, and the mode is changed during cell input. It is considered that the cell having the same content may be output redundantly to the data receiver 30 due to the switching, but this is solved by a method described below.

FIGS. 5 (a) and 5 (b) are explanatory diagrams for preventing a cell having the same content from being redundantly output to the data receiver 30 by mode switching during cell input. It is. FIG. 5A shows a case where cells having the same contents are redundantly output to the data receiver 30. FIG. 5B shows a case where cells having the same contents are prevented from being redundantly output to the data receiver 30.

As shown in FIG. 5A, at time [A], C
When the PU 4 refers to the detection result storage register 6, the fact that a cell has been input to the detection result storage register 6 through the transmission line 40 is not notified to the CPU 4 at this time. Start switching the register value.

During this switching, when the input of cells through the transmission line 40 starts at time [C], the cells input through the transmission line 40 at time [D] are output to the data receiver 30. Then, at time [E], the switching of the register value of the mode storage register 8 performed by the CPU 4 ends, and
The mode is switched from the first mode to the second mode.

Subsequently, when cell input starts at the time [F] through the transmission line 50 side, this cell is the first cell to reach after switching to the second mode. The cell input through the side is output to the data receiver 30.

As shown in FIG. 5B, at time [A], C
When the PU 4 refers to the detection result storage register 6, at this time, it is not notified to the CPU 4 that a cell has been input to the detection result storage register 6 through the transmission line 40 side.
The CPU 4 does not start switching the register value of the mode storage register 8 until time [B ′] when the time α has elapsed. That is, the first mode is maintained for a while.

In this state, when the cell input starts at the time [C] through the transmission line 40, the transmission line 4 at the time [D].
The cell input through the 0 side is output to the data receiver 30. Subsequently, when input of a cell through the transmission line 50 starts at time [F], the cell input through the transmission line 50 is not output to the data receiver 30 because this cell remains in the first mode.

Then, at time [B ′], the CPU 4 discloses switching of the register value of the mode storage register 8. Then, at time [E '], the switching of the register value of the mode storage register 8 performed by the CPU 4 ends, and the mode is switched from the first mode to the second mode.

According to such a method, it is possible to avoid a situation where cells input at time [C] and time [E] are duplicated and output to the data receiver 30.

The length of the time α may be, for example, equal to or greater than the difference in cell transmission time between the normal transmission lines 40 and 50. The length may be about 10 times the difference between the transmission times.

[Explanation of operation when congestion or the like of transmission line 40 occurs] Next, when congestion or the like occurs on the transmission line 40, only the input of cells transmitted through the transmission line 50 is temporarily detected, and It is possible that no cell input transmitted over line 40 is detected.

At this time, when the CPU 4 refers to the detection result storage register 6 in which the detection result is stored (FIG. 4B), it indicates that only the cells transmitted through the transmission line 50 have been input. Since it is stored, the register value of the mode storage register 8 is switched to the register value indicating the second mode (FIG. 4 (S2)).

Next, the cells transmitted from the data transmitter 10 through the transmission line 40 are transmitted through the transmission line 50 by the transmission path detecting means 5 if the congestion that has occurred in the transmission line 40 is resolved. Since a cell input from the transmission line 40 is detected earlier than a cell (FIG. 4)
(C)) The mode is switched to the first mode by the switching means 7.

By the way, if the data has a burst property, it is unlikely that two consecutive congestions have occurred on the transmission line 40. It is unlikely that you will be able to switch to mode. When the data does not have a burst property, for example, when only the cells from the transmission line 50 are input to the switching unit 7 in a multi-continuous manner, the third
It is sufficient to switch to the mode.

[Explanation of operation when a failure or the like of the transmission line 40 occurs] When a failure or the like occurs on the transmission line 40, the mode is switched to the second mode in the same manner as when congestion or the like of the transmission line 40 occurs.
However, cells from the transmission line 40 are not input to the data selection output device 20 unless the transmission line is restored by a network administrator or the like, so only cells transmitted through the transmission line 50 are input to the data selection output device 20. Will be done.

In this case, only cells transmitted through the transmission line 50 are continuously input (see FIG. 4).
(E)) The mode storage register 8 is switched by the switching means 7.
Is stored in the third mode (FIG. 4 (S
Switching is performed as shown in 3)).

If, for example, a fault occurs in the transmission line 50 immediately after the register value of the mode storage register 8 is switched to indicate the second mode, the state indicating the second mode is maintained (FIG. 11). 4 (d)).

Then, unless the transmission line 40 is restored,
Since only cells transmitted through the transmission line 50 are input to the data selection output device 20 (FIG. 4F), the third mode is maintained.

Thereafter, when the transmission line 40 is restored,
Again, the cells transmitted through the transmission line 40
The transmission path detection means 5 detects that the cell has been input before the cell transmitted through “0” (FIG. 4 (g)), and is switched to indicate the second mode. One mode is switched (FIG. 4
(C)).

As described above, in this embodiment, the transmission line 40
If no failure has occurred in the data receiver 30
The transmission path of the cell output to the transmission line 50 is not switched to the transmission line 50.

[0062]

As described above, according to the present invention, even if a failure or congestion occurs in a transmission path, instantaneous interruption or the like can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a data communication system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of the data selection output device of FIG.

FIG. 3 is a conceptual diagram of a configuration of a detection result storage register and a mode storage register of FIG. 2;

4 is a state transition diagram of register values stored in a mode storage register shown in FIG. 3;

FIG. 5 is an explanatory diagram for preventing a cell having the same content from being redundantly output to a data receiver due to mode switching performed during cell input.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input means 2 Virtual channel (VC) selection filter 3 VCI status storage register 4 CPU 5 Transmission path detection means 6 Detection result storage register 7 Switching means 8 Mode storage register 9 Virtual path (VP) selection filter 10 Data transmitter 20 Data selection Output device 30 Data receiver 40, 50, 60 Transmission line (path)

Claims (6)

[Claims] 1. A cell connected to a data transmitter via a plurality of transmission paths whose transmission times vary uniquely, and selects one of cells transmitted from the data transmitter through each transmission path. A data selection output device that outputs to a data receiver, and among the cells transmitted from the data transmitter via a plurality of transmission paths, the cells transmitted through the transmission path with the shortest transmission time are First output means for outputting to a data receiver, and when a cell is input via a transmission path having a transmission time longer than the transmission path having the shortest transmission time, the cell is selected and output to the data receiver. A second output unit, when cells are continuously input through the transmission path with the slowest transmission time, a cell transmitted through the transmission path is transmitted to the transmission path with the shortest transmission time. And a third output means for outputting the data to the data receiver in place of the cell output from the data receiver. 2. When a cell is input through a transmission path with the shortest transmission time while outputting a cell by the third output means, a cell from the transmission path with the shortest transmission time is selected. Fourth output means for outputting to the data receiver, and when cells are continuously input through a transmission path with the shortest transmission time when cells are output by the fourth output means, the transmission path 5. The data selection output device according to claim 1, further comprising: a fifth output unit configured to output a cell transmitted through the data receiver to the data receiver instead of outputting a cell from the transmission path having the slower transmission time. 3. A detecting means for detecting a transmission path of the cell by referring to a header of the cell, and a detection result storage register for storing a detection result of the detecting means, wherein the second to fifth registers are provided. 3. The data selection output device according to claim 1, wherein the output unit outputs the cell based on the detection result stored in the detection result storage register. 4. The detection result storage register has at least two or more banks, and the referenceable detection result on the second to fifth output means side is used as a trigger to switch a bank which can be referred to. The data selection output device according to claim 3, wherein 5. The data selection output device according to claim 1, wherein the cell is an asynchronous transfer mode cell. 6. A data communication system comprising the data selection output device according to claim 1. Description: