JP2002304232A - Operation processing system, operation processing control method, and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the processing with a request for the response time imposed thereon with less power consumption. SOLUTION: A system has a hardware mechanism for changing the operating frequency and the power supply voltage given to a processor while the system is in operation. A power manager sets the operating frequency and the power supply voltage necessary and sufficient for processing other loads in a waiting state (a state for waiting for the key input and the input-output of a mouse click). The power consumption of the processor is reduced by changing the operating frequency and the power supply voltage according to the elapsed time after leaving the waiting state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power reduction technique for a processor of the type that executes one or more tasks at the same time, and more particularly to executing one or more tasks including a task that is required to have a response time. The present invention relates to a power reduction technology for a processor.

More specifically, the present invention relates to a power reduction technology for a processor having a mechanism for changing an operating frequency and a power supply voltage, and relates to a GUI (Graphical User Interface).
e) The present invention relates to a power reduction technique for a processor that reduces power consumption by optimally setting an operation frequency and a power supply voltage at the time of execution of a task whose execution start time and processing time cannot be predicted in advance, such as processing.

[0003]

2. Description of the Related Art Recent LSI (Large Scale Integratio)
n) In combination with innovative advances in technology, various types of information processing equipment and information communication equipment have been developed and commercialized. In this type of equipment, the CPU (Central Pr
A variety of processing services are provided by executing predetermined program code by an operating unit and other processors.

[0004] On the other hand, reduction of power consumption of information equipment is regarded as one of the most important issues in the industry. This is because a battery-operated information device is a problem related to extension of the battery duration. Also,
For information devices that can be driven inexhaustibly by commercial power sources, power saving is recommended from the socio-ecological point of view of limited resources.

[0005] In an information device, the power consumption of a processor as its main controller accounts for a large proportion of that of the entire device. In other words, power saving of the processor also leads to power saving of the information equipment itself. In general, a processor tends to increase the operation speed as the operating frequency increases, while increasing the power consumption (further the heat generation amount).

For example, Japanese Patent Application Laid-Open No. 11-194849 discloses that a predetermined processing operation can be completed within a predetermined processing time without unnecessarily increasing power consumption, and the setting can be performed even when the processing capacity of a task changes. A data processing method and apparatus for simplifying operations are disclosed.

[0007] In the data processing device disclosed in the publication,
The processing capacity and processing time when the microcomputer executes various processing operations are registered in the capacity storage unit and the time storage unit, and the processing capacity and processing corresponding to the case where the microcomputer executes various processing operations are registered. The time is selected, the processing capacity is divided by the processing time to calculate the processing speed of the microcomputer, and the frequency of the reference clock is made variable. Since the processing speed of the microcomputer is varied in accordance with the processing capacity and the processing time, a predetermined processing operation can be reliably completed in the predetermined processing time, and the frequency of the reference clock can be set to an optimum value.
Unnecessary increase in power consumption in the data processing device can be prevented.

However, the data processing method and apparatus disclosed in the publication aims to reduce power consumption only by changing the operating clock frequency of the processor.
In other words, although the power consumption per unit time is reduced by reducing the operating clock frequency, the time required to complete each process is increased, and as a result, the effect of reducing the total power is not so high. That is, the power consumption does not exceed the range of the power consumption when the processor is in the idling state, and the effect is insufficient.

In the data processing method and apparatus disclosed in the above publication, the processing timing of each processing is predetermined, and all the processing is performed in time by performing the processing sequentially without interrupting each processing. It is assumed that it can be completed. For this reason, it cannot be applied to a system that needs to interrupt the execution of a certain process and perform a process with a higher degree of urgency (for example, a real-time process).

In Japanese Patent Application Laid-Open No. 2000-122747, a clock generator for supplying a clock to a digital signal operation processor is provided, and a clock frequency supplied from the clock generator to the digital signal operation processor is set to a digital value. A control device and a method for reducing power consumption by controlling based on a calculation processing amount in a signal calculation processing unit are disclosed.

However, the control device and method disclosed in the publication aims to reduce power consumption only by changing the operation clock frequency of the operation unit. In other words, although the power consumption per unit time decreases due to the reduction of the operating clock frequency, the time required to complete each process increases, and as a result, the effect of reducing the power amount is that the operation unit is in an idling state. This does not exceed the range of the power consumption at a certain time, and the effect is insufficient.

In the control apparatus and method disclosed in the publication, the operating frequency is calculated from the ratio of the idling time. However, since the ratio of the idling time changes every moment, it is extremely difficult to predict the change.

Also, Takanori Okuma, Tohru Ishihara,
"Real-Time Task Scheduling" written by Hiroto Yasuura
for a Variable Voltage Processor "(IEEE 12th Inte
rnational Symposium on System Synthesis, November
The scheduling method of SS and SD proposed in 1999) presupposes that the execution start time of a task is known before the system starts operating. For this reason,
There is a problem that it cannot be applied to a process whose execution start time and processing time cannot be predicted in advance, such as a GUI (Graphical User Interface) process.

Further, there is a problem that the DD scheduling method proposed in this paper cannot be applied to processing having no clear deadline such as GUI processing.

Also, a paper "Voltage-Clock Scaling for Low Energy Consump", co-authored by Yann-Hang Lee and CM Krishna.
tion in Real-time Embedded Systems "(IEEE Sixth In
ternational Conference on Real-Time Computing Syst
The method called "Task based static scheduling" proposed in ems and Applications, December 1999) is based on the premise that the task execution time is known before operating the system. For this reason, there is a problem that it cannot be applied to a process whose execution time or processing time cannot be predicted in advance, such as a GUI process.

Further, Japanese Patent Application No. 2000-287882 and Japanese Patent Application No. 2000-287882, which have already been assigned to the present applicant, have been disclosed.
The specification of -287883 proposes power-saving scheduling of task execution in an arithmetic processing system including a processor of a type whose operating frequency and power supply voltage are variable.

[0017] Of these, Japanese Patent Application No. 2000-287882 discloses a power-saving scheduling method capable of reducing the power consumption of a processor while responding to a real-time request of an application. That is, in a system in which the operating frequency and the power supply voltage of the processor can be changed under the control of the operating system, the operating frequency of the processor required to process the activated periodic real-time tasks and non-real-time tasks without delay. Is adaptively changed, and the optimal processor power supply voltage is determined in accordance with the operating frequency that changes every moment, thereby reducing the power consumption of the processor.

Further, Japanese Patent Application No. 2000-287883 discloses a multiprocessor configuration system capable of reducing power consumption by a processor while responding to real-time requests of applications.
In other words, operating frequency and power supply voltage are
In a multiprocessor configuration system having a plurality of processors that can be dynamically changed by system control, the operating frequency required to process each started task without delay is adaptively changed for each processor. At the same time, power consumption of each processor and the entire system can be reduced by determining an optimum power supply voltage in accordance with an operating frequency that changes every moment.

However, Japanese Patent Application No. 2000-28788.
No. 2 and Japanese Patent Application No. 2000-287883,
It is intended for real-time tasks for which the startup interval and the maximum required time are known in advance, and saves power during the execution of tasks whose execution start time and processing time cannot be predicted in advance, such as GUI processing. It does not perform scheduling.

In general, the processor tends to increase the operation speed as the operating frequency increases, while increasing the power consumption (furthermore, the amount of heat generation) (described above). In addition, the power supply voltage (in other words, power consumption) must be raised together with the operating frequency of the processor.
(However, in practice, since the upper limit of the power supply voltage is limited by the miniaturization of the LSI manufacturing process, the frequency is not increased by increasing the voltage.)

If the system can change the operating frequency and the power supply voltage of the processor by dynamic control,
The operating frequency required to process each task started without delay is adaptively changed, and the optimal power supply voltage is determined according to the operating frequency that changes every moment, thereby reducing the power consumption of the processor. It is thought that it is possible to reduce.

However, the prior art in which the power consumption of the processor is reduced by setting the operating frequency and the power supply voltage during the execution of a task whose execution start time and processing time cannot be predicted in advance, such as GUI processing, is performed. I can't find it.

[0023]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved power reduction technique for a processor that performs one or more tasks, including those tasks that have a requirement for response time.

It is a further object of the present invention to provide an excellent power reduction technique for a processor having a mechanism for changing an operating frequency and a power supply voltage.

A further object of the present invention is to provide a GUI (Graphica
l User Interface) It is possible to reduce power consumption by optimally setting the operating frequency and power supply voltage when executing tasks whose execution start time and processing time cannot be predicted in advance, such as processing. It is to provide an excellent power reduction technology for a processor.

[0026]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and a first aspect of the present invention is to provide a processor capable of executing a processing task having a request for a response time. An arithmetic processing system or arithmetic processing control method, comprising: at each time during operation of the processor, an operating frequency determining means or step for determining an operating frequency of the processor sufficient to satisfy a request for the response time; Processor clock generating means or step for generating an operating frequency clock based on a result determined by the operating frequency determining means or step and supplying the generated clock to the processor. It is.

However, the term "system" as used herein refers to a logical collection of a plurality of devices (or functional modules for realizing specific functions), and each device or functional module is a single case. It does not matter whether it is in the body or not.

When the processing task to which the request for the response time is imposed is in a waiting state, the operating frequency determining means determines an operating frequency of the processor sufficient to process another task imposed on the processor. Make a decision. Further, the operating frequency of the processor is increased stepwise in response to a lapse of a predetermined time after the processing task leaves the waiting state.

Therefore, according to the arithmetic processing system or the arithmetic processing control method according to the first aspect of the present invention, the reaction time felt by the user is not increased by utilizing the time when the processing task leaves the waiting state. The power consumed by the processor due to the task execution can be reduced appropriately (that is, without adversely affecting the user's feeling of use).

For example, a response time of about 0.1 second for the GUI application is sufficient. If the user responds earlier than this, the user's feeling of using the system hardly improves (it is not felt). Normally, when processing that can be executed in 0.1 seconds or less is performed, by controlling the operating frequency of the processor so that the processing is executed with a relatively slow response speed of about 0.1 second, the usability of the user is improved. The power consumption of the system can be reduced without adverse effects.

Similarly, at the time of executing a data read request from the disk device, the operating frequency of the processor is gradually recovered in accordance with the elapsed time after receiving the notification of the completion event from the disk device. The power consumption of the system can be reduced without affecting the user's feeling of use.

Also, when data reading is requested via a network connection, the operating frequency of the processor is gradually recovered in accordance with the elapsed time after receiving the notification of the completion event from the remote device. Thus, it is possible to reduce the power consumption of the system while not adversely affecting the user's feeling of use.

An arithmetic processing system or an arithmetic processing method according to the first aspect of the present invention determines a power supply voltage of the processor sufficient to drive the processor at the operating frequency determined by the operating frequency determining means. The apparatus may further include a power supply voltage determining unit or step, and a processor power supply unit or step for generating a power supply voltage based on a result determined by the power supply voltage determining unit or step and supplying the power supply voltage to the processor.

Generally, in order to increase the operating frequency of the processor, it is necessary to raise the voltage of the power supply.
The operating frequency required to process each task started in the processor without delay is adaptively changed, and the optimal power supply voltage is determined according to the operating frequency that changes every moment, thereby consuming the processor. The power can be effectively reduced.

The operating frequency determining means or step may increase the operating frequency of the processor in a stepwise manner when a predetermined time has elapsed since the processing task exited the waiting state.

Alternatively, the operating frequency determining means or step may continuously increase the operating frequency of the processor during a period from when the processing task leaves the waiting state until a predetermined time elapses.

According to a second aspect of the present invention, there is provided computer software written to execute, on a computer system, control of arithmetic processing by a processor capable of executing a processing task to which a request for response time is imposed. Wherein the computer software determines, at each time during operation of the processor, an operating frequency of the processor sufficient to satisfy the request for the response time. Operating frequency determining step, and an operating frequency clock that generates an operating frequency clock based on the result determined by the operating frequency determining step and supplies the generated operating frequency clock to the processor
And a clock generation step.

The storage medium according to the second aspect of the present invention is a medium for providing computer software in a computer-readable format to a general-purpose computer system capable of executing various program codes.
Such a medium is, for example, a CD (Compact Disc) or F
It is a removable and portable storage medium such as D (Floppy Disk) and MO (Magneto-Optical disc). Alternatively, it is technically possible to provide computer software to a specific computer system via a transmission medium such as a network (a network may be either wireless or wired).

Such a storage medium defines a structural or functional cooperative relationship between the computer software and the storage medium for realizing a predetermined computer software function on a computer system. It is. In other words, by installing predetermined computer software into the computer system via the storage medium according to the second aspect of the present invention, a cooperative action is exerted on the computer system, and the second aspect of the present invention is realized. The same operation and effect as the arithmetic processing system and the arithmetic processing control method according to one aspect can be obtained.

Still other objects, features and advantages of the present invention are:
It will become apparent from the following more detailed description based on the embodiments of the present invention and the accompanying drawings.

[0041]

Embodiments of the present invention will be described below in detail with reference to the drawings.

1. System Configuration FIG. 1 shows an arithmetic processing system 1 according to an embodiment of the present invention.
0 schematically illustrates a hardware configuration of the “0”. As shown in FIG. 1, the arithmetic processing system 10 includes a processor 11
, RAM (Random Access Memory) 12 and ROM
(Read Only Memory) 13, a peripheral device 14, and a timer 15.

The processor 11 includes the arithmetic processing system 10
Is a main controller for executing various program codes under the control of an operating system (OS).

A unit in which the operating system manages and controls the execution of a program is generally called a "task". It is assumed that the processor 11 according to the present embodiment includes a multitask mechanism that simultaneously executes a plurality of tasks that operate at different periods. Tasks can be broadly classified into "periodic real-time tasks", which need to complete their execution before the start of the next cycle, and "non-real-time tasks", which have no restriction on the execution completion time. . Non-real-time tasks include tasks that have a requirement for response time or GUI (Graphical
User Interface) processing, including waiting state,
This includes processes for which execution start time and processing time cannot be predicted.

The processor 11 is interconnected with other devices (described later) by a bus 16. Each device on the bus 16 is assigned a unique memory address or I / O address, and the processor 11 can access a predetermined device by designating these addresses. The bus 16 is a common signal transmission path including an address bus, a data bus, and a control bus.

The RAM 12 is a writable memory, and is used for loading a program code to be executed in the processor 11 and temporarily storing work data of an execution program. The program code includes, for example, a basic input / output system (BIOS), a device driver for operating hardware of peripheral devices, an operating system, and an application.

The ROM 13 is a nonvolatile memory for permanently storing predetermined codes and data.
Self-diagnosis program at the time of IOS and startup (Power On Self
Test: POST).

The peripheral device 14 includes a user output device such as a display and a printer, a user output device such as a keyboard and a mouse, an external storage device such as a hard disk and other media drives, and a network interface card ( NIC).

Each peripheral device is assigned an interrupt level, and responds to the occurrence of a predetermined event (for example, GUI processing such as keyboard input or mouse click, or completion of data transfer on a hard disk). The processor 11 can be notified via the interrupt request signal line 19. The processor 11 executes a corresponding interrupt handler in response to such an interrupt request. This type of interrupt processing is processing that includes a wait state or cannot predict the execution start time or processing time.

The timer 15 is a device for generating a timer signal at a predetermined cycle. An interrupt level is also assigned to the timer 15, and a periodic interrupt is generated for the processor 11 via the interrupt request signal line 19. (However, if there are multiple periodic real-time tasks with different periods, the timer signal does not become a periodic interrupt.)

Each component of the system 10 described above receives power from the power supply 17 through the power supply line 18.
Is supplied via The power supply device 17 includes, for example, a battery or a commercial AC power supply, but can supply a constant power supply voltage by an AC / DC adapter or a DC / DC converter.

In the illustrated example, a dedicated DC / DC converter 21 is provided for the processor 11. In the present embodiment, the processor 11 operates
Under the control of the system, the DC / DC converter 2 for the processor
1 is provided with a mechanism for setting the supply voltage.

The processor 11 inputs an operation clock generated by the processor clock generator 22,
It is driven synchronously with the operating frequency. Generally, as the operating frequency increases, the performance, that is, the processing speed of the processor 11 improves, and the power consumption also increases. In this embodiment, the processor 11 has a mechanism for setting the operating frequency of the clock generated by the processor clock generator 22 under the control of the operating system.

It should be noted that both the power supply voltage and the operating frequency for the processor 11 are determined by the DC / DC converter 21 for the processor.
It is not always necessary to dynamically control each of them and the processor clock generator 22, and the effect of the present invention can be realized by either one of the operations. In other words, the operating system is
Even if both the power supply voltage and the operating frequency are not dynamically controlled, but only one of them, the operating characteristics and effects of the present invention described later can be realized. Alternatively, only one of the power supply voltage and the operating frequency may be set by the arithmetic processing, and the other may automatically follow the setting (for example, the processor 11).
May be configured so that the minimum power supply voltage required to operate at that frequency is automatically supplied to the processor 11 by setting the frequency of the operating system by the operating system.)

The processor 11 generally has a CMOS (Co
Implementary Metal Oxide semiconductor: Complementary metal oxide semiconductor. The CMOS logic element has a characteristic that the delay time changes according to the power supply voltage. This means that the circuit can be driven with a lower power supply voltage by lowering the operating frequency of the processor 11. It also means that the processor 11 can be operated at a higher operating frequency by increasing the power supply voltage.

The power consumed by the CMOS logic element is proportional to the number of switching operations per unit time (this is almost proportional to the operating frequency of the processor 11). However, since the processing performance of the processor 11 is almost proportional to the clock frequency, simply lowering the operating frequency will
The power required to perform a given calculation cannot be reduced (because the power consumption per unit time can be reduced, but the time required for the calculation increases by that much, so that the calculation is eventually completed. The amount of power consumed before it is changed).

On the other hand, as the operating frequency decreases,
The minimum power supply voltage at which the processor 11 can operate normally decreases. Further, the power consumption of the processor 11 is substantially proportional to the square of the power supply voltage. Therefore, by reducing the clock frequency of the processor 11 and the power supply voltage, it is possible to reduce the power consumption required for a certain calculation.

In this embodiment, the operating clock frequency and the power supply voltage of the processor 11 are set to be as low as possible within a range that satisfies the performance requirements imposed on the system by the power manager (described later) executed by the processor 11. Controlled. The power manager may be implemented, for example, as a function of the operating system.

The power manager may be configured so that only one of the operating clock frequency and the power supply voltage to the processor 11 is set, and the other automatically follows the setting. For example, if the power manager
By setting only one operating frequency, the minimum power supply voltage required to operate at that frequency may be automatically supplied.

[0060] 2. Application The present invention is designed to reduce the power consumption of the processor 11 that is executing a process to which a request for a response time is imposed, or a process including a wait state, or a process whose execution start time or processing time cannot be predicted. The operation frequency and the power supply voltage are set. In the following, a GUI application that operates in response to a user input from a keyboard or a mouse will be described as an example of a process in which a request for a response time is imposed.

Many GUI applications are implemented so as to proceed by sequentially reacting to various events as described below. That is,

(1) The user has pressed down a key on the keyboard or released the pressed key. (2) The mouse button has been pressed or released. (3) The mouse pointer has entered or exited a certain area in the window.

FIG. 2 schematically shows the configuration of a GUI framework and a GUI application.

The GUI framework controls peripheral devices that perform GUI input / output, such as a keyboard, a mouse, and a display. When an event such as “key input”, “mouse operation”, or “display update” occurs on these peripheral devices,
The UI framework sends the event object to the event queue.

On the other hand, after the GUI application is started, after initializing the application, the GUI application waits until an event object arrives in the event queue. That is, an event waiting procedure is called for the event queue of the GUI framework.

Events to be processed by the application
When the object arrives at the event queue, the type of the event is specified, and a process corresponding to each event is executed.

In the event processing, if necessary, it is possible to request the drawing unit in the GUI framework to update the display. The drawing unit performs a drawing process of the corresponding window on the display in response to the request.

In FIG. 2, the time from when the GUI framework transfers control to the GUI application upon arrival of an event until when the GUI application starts execution of processing for waiting for an event object to arrive in the event queue is: This corresponds to the response time of the GUI application.

In many applications, the GUI
An application response time of about 0.1 second is sufficient. If the user responds earlier than this, the user's feeling of using the system hardly improves (it is not felt). Further, as described above, the same processing can be executed with lower power consumption by lowering the operating frequency of the processor 11.

Therefore, in the present embodiment, when processing that can be normally executed in 0.1 seconds or less is executed, the operation of the processor 11 is performed so that the processing is executed at a relatively slow response speed of about 0.1 second. Frequency and power supply voltage are controlled. It should be appreciated that such control can reduce the power consumption of the system 10 without adversely affecting the user's feeling of use.

For example, if only one task is operating in the system 10 and it is a GUI processing task, the processor 11 operates at a low operating frequency for a certain period of time after an event occurs. However, after that (after a lapse of a predetermined time), the power consumption of the processor 11 is reduced by controlling the operation at a high operating frequency without adversely affecting the user's usability when resuming from the waiting state due to the event occurrence. be able to.

FIG. 3 shows an example of control timing of the operating frequency of the processor 11 when an event occurs during execution of the GUI processing task. In the example shown in the figure, the processor 11 operates at two operation frequencies: a high-level request value required for full operation and a low-level request value minimum required to satisfy a relatively slow response speed. Can do so.

First, when the GUI application shifts to an event waiting state for requesting a GUI input from the user, the operating frequency of the processor 11 is stopped to reduce power consumption to the maximum.

Next, when a user inputs a GUI and an event arrives at the GUI application,
A certain period of time (request level change time)
Does not adversely affect the user's feeling of use even when the operation has a relatively slow response speed. Therefore, an operating frequency of a low level request value is supplied to the processor 11 to reduce power consumption.

When the request level change time elapses, if the response speed remains low, the user's feeling of use begins to be adversely affected. Therefore, the operating frequency of a high-level request value is supplied to the processor 11 to provide the fastest response. Return to speed.

When the operating frequency of the processor is reduced, the processing that required a long response time in the conventional system has a problem that the response time is further increased. On the other hand, in the present embodiment, the response delay is reduced to about 0.1 second or less by setting the request level change time to, for example, about 0.1 second. The performance degradation of 0.1 second has almost no adverse effect on the user's feeling of use, and is not a problem.

In the example shown in FIG. 3, the processor 10 exits from the event wait state only once, and
Operating frequency is changed. However, if the calculation time of each process varies widely, it is conceivable that satisfactory power saving control cannot be realized unless the operating frequency changes by only one step. For such a case, it is also considered effective to change the operating frequency of the processor 11 in multiple stages according to the elapsed time from the arrival of the event to the GUI application.

FIG. 4 shows an example of control timing when the operating frequency of the processor 11 is changed in multiple stages according to the elapsed time from the arrival of the event during execution of the GUI processing task. In the example shown in FIG.
1 is the required value level 1 in the order of lower operating frequency,
It is assumed that the driving can be performed at three operation frequencies, that is, the required value level 2 and the required value level 3.

First, when the GUI application shifts to an event waiting state for requesting a GUI input from the user, the operating frequency of the processor 11 is stopped to reduce power consumption to the maximum.

Next, when a user inputs a GUI and an event arrives at the GUI application,
During the period from the waiting state until the first required level change time, the operating frequency corresponding to the required value level 1 is supplied to the processor 11 so that the processor 11 is operated with the slowest response speed.

Next, when the first required level change time elapses, the operating frequency corresponding to the required value level 2 is supplied to the processor 11 to slightly increase the response speed.

Further, after the elapse of the second required level change time, the operating frequency corresponding to the required value level 3 is supplied to the processor 11 to return to the fastest response speed.

In the example shown in FIGS. 3 and 4, the system 10
Changes the operating frequency of the processor 11 step by step after exiting from the event waiting state, but changes the operating frequency during the period until the operating frequency returns to the maximum before a predetermined time elapses from the arrival of the event. Is not limited to these. For example, it is also effective to increase the number of steps for changing the operating frequency indefinitely during the elapse of the predetermined time from the arrival of the event, and to change the operating frequency continuously.

FIG. 5 shows that while the GUI processing task is being executed, the processor 1 is controlled according to the elapsed time from the arrival of the event.
4 shows an example of control timing when the operating frequency of the first control signal is continuously changed. In the example shown in FIG.
No. 1 can be driven by continuously changing the operating frequency.

First, when the GUI application shifts to an event waiting state for requesting a GUI input from a user, the operating frequency of the processor 11 is stopped to reduce power consumption to the maximum.

Next, when a user inputs a GUI and an event arrives at the GUI application,
During the period from the waiting state to the first required level change time, the operating frequency of the processor 11 is continuously changed to the required level 1.

Next, 2 seconds from the initial request level change time
During the period up to the second required level change time, the operating frequency of the processor 11 is continuously changed from the required level 1 to the required level 2.

After passing through the second required level changing organ, the operating frequency of the processor 11 is continuously changed from the required level 2 to the required level 3 within a predetermined time, so that the fastest response speed is achieved. return.

[0089] 3. Other Embodiments Although the power saving control of the processor 11 has been described by taking the case of executing the GUI application as an example, the gist of the present invention is not limited to the application to the GUI application. The present invention can be applied to all applications that require time and perform processing in response to an event.

As another embodiment of the present invention, an application example in a data arrival waiting state from a disk device such as a hard disk (or another type of external storage device) can be given.

Referring to FIG. 6, an example will be described in which the processor 11 falls into a waiting state until the requested data arrives from the disk device, and thereafter executes an application that repeats a process of displaying a screen based on the transfer data. I do.

In this case, the application program requests the operating system (or the file manager in the OS) to read data from the disk device.

The operating system (or file manager) issues a data read command to the relevant disk device. Software such as a predetermined disk driver (not shown) may be interposed between the operating system and the disk device.

After issuing this data read request, the processor 11 enters an event waiting state and stops the operating frequency.

Thereafter, when the disk device completes reading the requested data, it notifies the operating system of a completion event. The operating system further notifies the requesting application of a completion event.

This completion event corresponds to “event arrival” in the application example to the GUI application.
Therefore, the operating frequency of the processor 11 can be gradually recovered in accordance with the elapsed time after receiving the notification of the completion event, for example, in a format as shown in FIGS. As a result, the power consumption of the system 10 can be reduced while not adversely affecting the user's feeling of use.

The application program can display a read result on a display based on the read data received via the operating system. At this time, the GUI framework (described above) may be interposed.

Further, as another embodiment of the present invention, an example of application to an application for inputting / outputting data via a network connection can be given.

An example in which the processor 11 falls into a waiting state until the requested data arrives via the network connection and thereafter executes an application that repeats the process of displaying a screen based on the transfer data will be described.
This will be described with reference to FIG.

In this case, the application program requests the operating system (or communication protocol software) to read data (from the remote disk) via the network connection.

The operating system (or communication protocol software) issues a data read command to the corresponding remote disk.

After issuing this data read request, the processor 11 enters an event waiting state and stops the operating frequency.

Thereafter, when the remote disk completes reading the requested data, it notifies the operating system of a completion event. The operating system further notifies the requesting application of a completion event.

This completion event corresponds to “event arrival” in the application example to the GUI application.
Therefore, the operating frequency of the processor 11 can be gradually recovered in accordance with the elapsed time after receiving the notification of the completion event, for example, in a format as shown in FIGS. As a result, the power consumption of the system 10 can be reduced while not adversely affecting the user's feeling of use.

The application program can display the read result on a display based on the read data received via the operating system. At this time, the GUI framework (described above) may be interposed. Further, the application transmits the result to the data readout destination via the network.

[0106] 4. Software Configuration Power management by operating frequency control of the processor 11 as shown in FIGS. 3 to 5 can be implemented, for example, as one function of an operating system. Hereinafter, the functional module in the operating system will be referred to as a “power manager”.

FIG. 8 schematically shows the software configuration of the power manager when the operating frequency of the processor 11 is restored at one stage after the arrival of the event, as shown in FIG.

As shown in FIG. 8, the power manager prepares a framework unit and a timer, one for each task. Each task has the following three types of variables. The meanings of these variables are as already described with reference to FIG.

(1) Low level request value (value range is [0, 1.
0]) (2) High level request value (value range is [0, 1.0]) (3) Request level change time

In the example shown in FIG. 8, the framework unit
It operates according to the following procedure.

[0111] Step 1: When the task is to ask "wait in the event queue until the event object to arrive" process of the execution start to the framework part (procedure P
1) The power manager is notified that this task has not made any request regarding the operating frequency of the processor 11 (procedure P2). If the timer is operating, it is stopped.

Step 2: When an event arrives at the event queue (procedure P3), the task is
Is notified that a low-level request has been made for the operating frequency (procedure P4), and the timer is started (procedure P
5). The corresponding application is notified of the arrival of the event (procedure P6). The timer notifies the power manager that this task is making a high-level request when the request level change time has elapsed since the timer was started (procedure P7).

FIG. 9 schematically shows a software configuration for recovering the operating frequency of the processor 11 at one stage after the arrival of the event, as shown in FIG.

As shown in FIG. 9, the power manager prepares the following four types of variables for each task. The meaning of these variables is as follows.

(1) Request value stage number This is a variable that holds the order of the operation frequency of the processor 11 at present. For example, in the example shown in FIG. 4, the value of this variable is 1 immediately after “2. Arrival of event” to immediately before “3. Thereafter, each time the required value is changed, the required value step number is incremented by one. When no request has occurred (that is, when the task is in the event waiting state), the value is 0.

(2) Request Value Array The request value when the variable “request value stage number” takes the value n is stored in the n-th element of the request value array.

(3) Request value change time array In the n-th element of the request value change time array, the variable “request value stage number” takes a value n, and the request “request value array [n]” is sent to the power manager. The length of the period for which "" is set is stored. After this time has elapsed, the required value for the next stage will be set. However, n does not increase beyond the variable “number of steps” described below.

(4) Number of steps This is a variable that holds the number of steps.

In the example shown in FIG. 9, the framework unit
It operates according to the following procedure.

Step 1: When the task requests the framework unit to start the execution of the process of “waiting for the arrival of an event object in the event queue” (procedure P1
1) Notify the power manager that this task has not made any request regarding the operating frequency of the processor 11 (procedure P12). If the timer is operating, it is stopped. Further, 0 is substituted for the required value stage number of the framework unit.

Step 2: When an event arrives at the event queue (procedure P13), 1 is substituted for the request value stage number (or incremented by 1). Then, the required value of the first step (or the next step) is set in the power manager (procedure P14), and the timer is started (procedure P1).
5). The corresponding application is notified of the arrival of the event (procedure P16). When the time indicated by the first element of the request value change time array has elapsed, the timer notifies the power manager that this task is making a request for the next stage (procedure P17). by this,
The request value step number is updated, the request value corresponding to this step number is set, and the timer is reset.

[0122] 5. To be suitably implement the present invention under power manager multitasking environment, power manager integrates the performance requirements of a plurality of tasks, it is necessary to determine the proper operating frequency of the processor 11, and a power supply voltage. In this section, a method for performing the determination processing will be described.

In this embodiment, it is assumed that the processor 11 can handle the following three types of tasks.

(1) Real-time task A real-time task is a task that is started at a predetermined cycle and whose execution must be completed before the start of the next cycle. However, the cycle of each real-time task varies.

(2) High Responsiveness Task This is a task to perform a process to which a request for a response time is imposed, or a process including a wait state or an execution start time or a processing time which cannot be predicted. The high-responsive task is executed in response to various events such as a user input operation such as a keyboard and a mouse.

(3) Other tasks

In the present embodiment, the power manager always calculates an appropriate operating frequency of the processor 11 according to a change in load, taking into account all the real-time tasks in operation and other tasks. This processing itself is performed, for example, in Japanese Patent Application No. 2000-28 already assigned to the present applicant.
No. 7,882,878 discloses a method for adaptively changing the operating frequency of a processor necessary for processing activated periodic real-time tasks and non-real-time tasks without delay, and changing the operating frequency to change every moment. The power consumption of the processor is reduced by deciding the optimum processor power supply voltage in accordance therewith.) Then, the calculation result is stored in a variable “request value of a real-time task or another task”.

A real-time task, by its nature, needs to be executed with priority over other tasks. That is, it is assumed that whenever there is an executable real-time task, it is guaranteed that they are executed.

The required value of the high responsive task in operation is notified to the power manager via the framework unit (for example, procedures P2, P4, P7 in FIG. 8). Each time this notification is made (i.e., every time the request for a responsive task changes), the power manager calculates the following value:
This is set as the operating frequency of the processor 11.

[0130]

(Equation 1)

[Supplement] The present invention has been described in detail with reference to the specific embodiments. However, it is obvious that those skilled in the art can modify or substitute the embodiment without departing from the spirit of the present invention. That is, the present invention has been disclosed by way of example, and should not be construed as limiting. In order to determine the gist of the present invention, the claims described at the beginning should be considered.

[0132]

As described above in detail, according to the present invention,
An excellent power reduction technique can be provided for a processor that performs one or more tasks, including tasks that have a requirement for response time.

Further, according to the present invention, it is possible to provide an excellent power reduction technique for a processor having a mechanism for changing an operating frequency and a power supply voltage.

According to the present invention, a GUI (Graphica
l User Interface) It is possible to reduce power consumption by optimally setting the operating frequency and power supply voltage when executing tasks whose execution start time and processing time cannot be predicted in advance, such as processing. An excellent power reduction technique for a processor can be provided.

Further, according to the present invention, the processor is consumed by executing the GUI application or the network application without increasing the reaction time felt by the user (ie, without adversely affecting the user's feeling of use). Electric power can be suitably reduced. Further, since the power consumption of the processor is reduced, the amount of heat generated can also be suppressed.

[Brief description of the drawings]

FIG. 1 is an arithmetic processing system 10 provided for implementing the present invention.
FIG. 2 is a diagram schematically showing the hardware configuration of FIG.

FIG. 2 is a diagram schematically illustrating a configuration of a GUI framework and a GUI application.

FIG. 3 is a diagram illustrating an example of control timing of an operating frequency of a processor 11 when an event occurs during execution of a GUI processing task.

FIG. 4 is a diagram showing another example of the control timing of the operating frequency of the processor 11 when an event occurs during execution of the GUI processing task.

FIG. 5 is a diagram illustrating another example of the control timing of the operating frequency of the processor 11 when an event occurs during execution of the GUI processing task.

FIG. 6 schematically illustrates an application example of the present invention in a case where an application that repeats a process of performing a screen display based on transfer data after executing a wait state until request data arrives from a disk device. FIG.

FIG. 7 is a diagram schematically showing an application example of the present invention to an application that inputs and outputs data via a network connection.

FIG. 8 is a diagram schematically illustrating a software configuration of a power manager when the operating frequency of the processor 11 is restored in one stage after an event arrives, as illustrated in FIG. 3;

FIG. 9 is a diagram schematically illustrating a software configuration of a power manager when the operating frequency of the processor 11 is restored in multiple stages after the arrival of the event, as illustrated in FIG. 4;

[Explanation of symbols]

 Reference Signs List 10 arithmetic processing system 11 processor 12 RAM 13 ROM 14 peripheral device 15 timer 16 system bus 17 power supply 18 power supply line 19 interrupt request line 21 processor DC / DC converter 22 … Processor clock generator

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B011 EA01 LL02 LL13 5B033 AA06 AA15 BC01 5B079 BA01 BC01 5B098 FF03 GA02 GA04

Claims (15)

[Claims] An arithmetic processing system including a processor capable of executing a processing task to which a request for a response time is imposed, wherein at each time during operation of the processor, the processor is sufficient to satisfy the request for the response time. Operating frequency determining means for determining an operating frequency of the processor; and a processor clock generating means for generating an operating frequency clock based on a result determined by the operating frequency determining means and supplying the generated operating frequency clock to the processor. Arithmetic processing system. 2. A power supply voltage determining means for determining a power supply voltage of the processor sufficient to drive the processor at the operating frequency determined by the operating frequency determining means, and based on a result determined by the power supply voltage determining means. The processing system according to claim 1, further comprising: a processor power supply unit configured to generate a power supply voltage and supply the generated power supply voltage to the processor. 3. The operating frequency determining means according to claim 1, wherein said operating frequency determining means determines an operating frequency of said processor in accordance with an elapsed time after a processing task leaves a waiting state.
An arithmetic processing system according to item 1. 4. The processor according to claim 1, wherein said operating frequency determining means increases the operating frequency of said processor in a stepwise manner when a predetermined time has elapsed since the processing task exited the waiting state. An arithmetic processing system according to item 1. 5. The operating frequency determining means according to claim 1, wherein the operating frequency of the processor is continuously increased during a period from when the processing task leaves the waiting state until a predetermined time has elapsed. An arithmetic processing system according to item 1. 6. The processor may execute, in parallel, one or more tasks including a processing task to which a request for a response time is imposed, and the operating frequency determination unit may determine that the request for a response time is not received. The operation of claim 1, wherein when an imposed processing task is in a wait state, determining an operating frequency of the processor sufficient to process other tasks imposed on the processor. Processing system. 7. An arithmetic processing control method for controlling arithmetic processing by a processor capable of executing a processing task to which a request for a response time is imposed, wherein the request for the response time is determined at each point in time when the processor is operating. An operating frequency determining step of determining an operating frequency of the processor sufficient to satisfy the condition; and a processor clock generating step of generating an operating frequency clock based on a result determined by the operating frequency determining step and supplying the operating clock to the processor. An arithmetic processing control method comprising: 8. A power supply voltage determining step of determining a power supply voltage of the processor sufficient to drive the processor at the operating frequency determined by the operating frequency determining step, and based on a result of the determination by the power supply voltage determining step. The method according to claim 7, further comprising a processor power supply step of generating a power supply voltage and supplying the power supply voltage to the processor. 9. The arithmetic processing control according to claim 7, wherein in the operating frequency determining step, the operating frequency of the processor is determined according to an elapsed time after the processing task leaves the waiting state. Method. 10. The operating frequency determining step includes increasing the operating frequency of the processor in a stepwise manner when a predetermined time has elapsed since the processing task exited the waiting state. 3. The arithmetic processing control method according to 1. 11. The operating frequency determining step, wherein the operating frequency of the processor is continuously increased during a period from when the processing task leaves the waiting state until a predetermined time elapses. 3. The arithmetic processing control method according to 1. 12. The processor according to claim 1, wherein the processor is capable of executing one or more tasks including a processing task to which a request for a response time is imposed in parallel. 8. The operation of claim 7, wherein when an imposed processing task is in a wait state, determining an operating frequency of the processor sufficient to process other tasks imposed on the processor. Processing control method. 13. Computer software physically stored in a computer-readable format, which is written to execute, on a computer system, control of arithmetic processing by a processor capable of executing a processing task to which a request for a response time is imposed. An operating frequency determining step of determining an operating frequency of the processor sufficient to satisfy the request for the response time at each time during the operation of the processor; and A processor clock generating step of generating an operating frequency clock based on a result determined by the frequency determining step and supplying the operating frequency clock to the processor. 14. The operating frequency determining step, wherein the operating frequency of the processor is continuously increased during a period from when the processing task leaves the waiting state to when a predetermined time elapses. A storage medium according to claim 1. 15. The processor may execute one or more tasks including a processing task to which a request for a response time is imposed in parallel. 14. The storage of claim 13, wherein when an imposed processing task is in a waiting state, determining an operating frequency of the processor sufficient to process other tasks imposed on the processor. Medium.