JP2002297449A - System integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system integrated circuit that prevents the readout destination of restricted data stored in a memory device from being discovered even if the activity of a CPU inside a system LSI is traced. SOLUTION: A second memory stores the restricted data, which are used with a CPU 7. Readout from the second memory into a first memory is executed during the initialization of a STB(set top box) in which the system integrated circuit is built. More specifically, an initial condition management device 15, during the initialization of the STB, reads out the restricted data from memory devices 101, 111 to set the data in any of a plurality of areas in the first memory, and then instructs the CPU 7 to start its operation. Even if the activity of the CPU 7 is submitted to a reverse analysis in detail, the readout destination of the restricted data is not discovered.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system integrated circuit in which various circuits such as a central processing unit are integrated, and relates to an improvement in a case where confidential data is handled by being incorporated in a device.

[0002]

2. Description of the Related Art Along with rapid progress of semiconductor process technology, devices having a built-in system integrated circuit (system LSI) are rapidly spreading. A device with a built-in system LSI includes a system LSI and one or more memory devices, and is used in a wide range of fields such as a set-top box (STB) and a portable device. The logic part of the circuit element that implements such a device is mounted inside the system LSI. The logic part includes a central processing unit (CPU), a cache memory used by the CPU, registers, a TS decoder for demultiplexing the transport stream, and an MPEG.
There is an MPEG decoder for decoding a stream.
By integrating these in the LSI, stable operation of the logic part is guaranteed. On the other hand, a ROM for storing programs and data is mounted outside the system LSI as a memory device. Since the data and the program are mounted outside the system LSI, the data and the program can be changed by rewriting the stored contents of the memory device without modifying the system LSI.

[0003] In a device such as an STB, there is a case where a user needs to be charged for receiving a pay broadcast or reproducing a pay content, and the memory device stores identification information (device ID) of the device and information of an operator. Identification information (user ID)
Data that is required to be treated as secret, so-called secret data, must be stored. However, the contents stored in the memory device may be exposed by a technique for analyzing the contents of the product, so-called "reverse analysis". Therefore, in a conventional device, the secret data is encrypted and stored in a memory device, thereby avoiding revealing the secret data due to an illegal reverse analysis.

[0004] Since the secret data is stored in the memory device in an encrypted state, it is possible to suitably protect the device from hacking.

[0005]

By the way, although secret data is completely encrypted when stored in the memory device, the program stored in the memory device is often not encrypted. By disassembling the program while referring to the CPU mnemonic table, you can ask what kind of processing the CPU does. The device ID and user ID as described above are
During the initial operation of the CPU, it is often taken from the memory device to the system LSI.
By analyzing the read command issued from the CPU in the system LSI to the memory device, the secret data stored in the memory device can be stored in any of a plurality of registers or memories built in the system LSI. Can be heard.

[0006] Since the secret data is stored in a register and a memory inside the system LSI in a state where it is decrypted by the decryption unit, a more detailed reverse analysis can be performed by using a read destination obtained by decryption as a key. By doing so, it is possible to know secret data that has not been encrypted. If the confidential data obtained in this way is passed on to malicious third parties, hacking acts on the equipment may be widespread, and the manufacturers of the equipment and those who handle pay broadcasting and pay contents will be hit hard I will wear it.

[0007] If only disassembly of the program can be prevented, such as by encrypting the program, it seems that disclosure of the secret data can be prevented. However, the technological progress of the reverse analysis is remarkable, and a slight trace when the CPU operates is shown in the system L
If observed from outside the SI, it may be possible to use this as a clue to find out where to read the secret data. In the future, if the above-mentioned devices are required to handle electronic money, etc., it will be the responsibility of the manufacturer of the system LSI to take drastic measures against the progress of the reverse analysis in the system LSI. Can be

It is an object of the present invention to provide a system integrated circuit which prevents a source of secret data stored in a memory device from being revealed even if the movement of a CPU inside the system LSI is traced.

[0009]

In order to achieve the above object, a system integrated circuit according to the present invention is a system integrated circuit incorporated in a device together with a memory device storing secret data. An access unit for reading and writing to the device, an instruction unit for instructing the central processing unit to start operation when the device is initialized, and an access to read secret data from the memory device prior to the operation start instruction to the central processing unit And a read control unit for controlling the unit.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a system integrated circuit (system LSI) will be described with reference to the drawings. (First Embodiment) A system LSI according to this embodiment is an STB.
Implemented within. Figure 1 shows an S that implements a system LSI.
FIG. 3 is a diagram illustrating an internal configuration of a TB. STB is a satellite broadcast, a terrestrial wave, receives a broadcast wave transmitted from any of the wire, performs the demultiplexing of the transport stream included in this, further decodes the video signal, This device outputs audio signals and the like, and is used in ordinary households in combination with a television receiver or a personal computer.

As shown in FIG. 1, the STB includes memory devices 101 and 111, a front end unit 102, a peripheral device 103, an external reset signal generator 104, and a clock signal oscillator 105. Memory device 101, 1
11 is a program for realizing the operation of the device, data,
EEPROM and SDRAM for storing device IDs and user IDs, IC cards and memory cards incorporating these,
It is connected to a system LSI via a control line to form secondary storage. Among these various data, the device ID and the user ID are data for which confidentiality is required, and are encrypted and stored in the memory devices 101 and 111. An algorithm for encrypting data that requires confidentiality is what is called “bit shuffling”. This algorithm replaces the bit data constituting the original device ID and user ID with a predetermined regularity, and replaces the encrypted device ID and user ID with the same regularity to obtain the original device ID and the user ID. Device ID and user ID can be obtained.

The front end unit 102 demodulates a broadcast wave received by a satellite broadcast antenna or the like, and sequentially outputs a transport stream defined by the MPEG2 standard to a system LSI. The peripheral device 103 includes a front panel and a remote control transmission / reception unit. External reset signal generator 10
4 outputs an external reset signal when an initialization operation is performed on the device.

The clock signal oscillator 105 outputs a clock signal when an initialization operation for the device is performed.
The logic part that realizes the STB function is based on this system LSI.
Therefore, the board wiring in the STB is extremely simple. While the board wiring in the STB has been simplified, various components will be mounted at high density inside the system LSI. With reference to FIG. 2, what components are implemented in the internal configuration of the system LSI will be described. As shown in FIG.
I is a transport decoder 1, an AV decoder 2, a peripheral device interface 3, an SRAM 4, a register file 5, a cross bus switch 6, a CPU 7, an instruction cache 8, a data cache 9, a fetch unit 10, an instruction decoder 11, and an arithmetic operation circuit 12. , Bus access control unit 13,
It comprises a cipher conversion device 14 and an initial state management device 15.

The transport decoder 1 demultiplexes the transport stream output from the front end unit 102 to obtain a video stream and an audio stream defined by the MPEG2 standard, and outputs the video stream and the audio stream to the AV decoder 2. . The AV decoder 2 decodes the demultiplexed video stream-audio stream to obtain a video signal and an audio signal.

The peripheral device interface unit 3 is an interface with a front panel and a remote control transmitting / receiving unit in the peripheral device 103. The SRAM 4 stores a part of the data stored in the memory devices 101 and 111. The register file 5 contains the memory device 1
Part of the data stored in 01 and 111 is stored. While the memory devices 101 and 111 are called secondary storage, the SRAM 4 and the register file 5 are called primary storage.

The cross bus switch 6 includes a data bus, an I / O
Interconnects the O bus, address bus, and instruction bus. The central processing unit (CPU) 7 is connected to the cross bus switch 6 via a cache memory for instructions (instruction cache 8) and a cache memory for data (data cache 9), and performs integrated control in the system LSI. CPU
A fetch unit 10 for fetching instructions from the memory devices 101 and 111 via the instruction cache 8 and the data cache 9, an instruction decoder 11 for decoding the fetched instructions, and a memory device 10 for decoding the fetched instructions.
And an arithmetic operation circuit (ALU) 12 for performing an operation using data read from the system integrated circuits 1 and 111 to the system integrated circuit. This is as shown in the frame corresponding to the CPU 7 in FIG.

The bus access control unit 13 reads and writes data from and to the memory devices 101 and 111 in accordance with an instruction from the CPU 7. Hereinafter, the details of the processing of the bus access control unit 13 will be described separately for clauses (13.i), (13.ii), (13.iii), and (13.iv). (13.i) At the time of reading from the memory devices 101 and 111, the bus access control unit 13 outputs the content stored in the secondary storage to the data bus.
Instruct secondary storage through the control line. If the stored contents are sequentially output to the data bus, the bus access control unit 1
3 sequentially retrieves these stored contents and stores them in the primary storage.

(13.ii) When writing to the memory devices 101 and 111, the bus access control unit 13 sequentially outputs the storage contents of the primary storage to the data bus. At the same time, it instructs the memory devices 101 and 111 through the control line to take in the stored contents. When the memory devices 101 and 111 take in the transmission contents of the data bus in accordance with the instruction, data writing from the system LSI to the memory devices 101 and 111 is performed.

(13.iii) Reading and writing of the memory devices 101 and 111 by the bus access control unit 13 is performed by the CPU.
7, the initial state management device 1
5 may be performed according to the control. That is, CPU
The bus access control unit 13 controls the memory device 101 under the control of the CPU 7 when the CPU 7 reads an instruction constituting the program, or reads and writes data with the execution of the program with respect to the memory devices 101 and 111. ,
111 is accessed. On the other hand, the access to the memory devices 101 and 111 under the control of the initial state management device 15 is performed when the memory device 1
In this case, the secret data stored in 01 and 111 is read.

(13.iv) The access instruction through the control line is
This is performed by the bus access control unit 13 outputting three types of signals such as a select signal, an address signal, and a command signal. The select signal is a signal indicating which one of the plurality of memory devices 101 and 111 is to be selected, and the address signal indicates which address is to be accessed in the memory device 101 or 111 selected by the select signal. Signal. The command signal indicates whether the content of the access is read or write.

If the stored content fetched into the system LSI by the bus access control unit 13 is secret data, the cryptographic conversion device 14 decrypts the encrypted data to obtain the original data and then stores the primary data. Configure cache memory,
Store in any of the registers. The secret data is stored in the primary storage. If the CPU 7 instructs to write the secret data, the bus access control unit 1 encrypts the secret data after encrypting it.
3 and stored in the memory devices 101 and 111.

When the initialization of the device by the user is started, the initial state management device 15 instructs the bus access control unit 13 to read out the device ID and the user ID from the memory devices 101 and 111 after a predetermined first period has elapsed. Then, after a predetermined second period has elapsed, an internal reset signal is output to cause the CPU 7 to start operation. The above-described first period is a period from when the power is turned on to when the hardware of the entire STB is stabilized. Waiting for this first period to elapse
This is to ensure the normal operation of the U and the memory device.
On the other hand, the second period is a period longer than the first period, and is set to twice the first period in the present embodiment. The initial state management device 15 has a counter to monitor the progress of the first period and the second period.

Here, the initialization of the equipment means that the power supply voltage supplied to the equipment becomes a predetermined voltage value and the external reset signal is output.
It means to rise from LOW (meaning the inactive state) to HIGH (meaning the active state). Some time after the power is turned on to the device, the clock signal generator 105 starts generating a clock signal. FIG. 3 is a timing chart showing a temporal transition of the process of the initial state management device 15. The first row of the figure shows the power supply level outside the device, and the second row shows
The external reset signal, the third stage is a clock signal composed of a clock pulse train, and the fourth and fifth stages are built in the initial state management device 15 when the wave number of the clock pulse reaches 500 or 1000. The notification signal output by the current counter, the sixth row is a read signal issued by the bus access control unit 13, and the seventh row is the initial state management device 15.
5 shows an internal reset signal issued to the memory. In the figure, the first period refers to a period in which the clock pulse wave number has reached 500 times, and the second period has a clock pulse wave number of 10 times.
It means the period when the number of times is 00.

When the initialization operation of the device is performed, the power supply rises from 0V to 5V as shown by an arrow y1. Thereafter, after an indefinite period y2, the clock signal oscillator 105 starts outputting a clock pulse. On the other hand, the external reset signal generator 104 generates an external reset signal as shown by an arrow c1.
Start from LOW to HIGH. When the output of the clock pulse is started and the external reset signal rises from LOW to HIGH, the counter incorporated in the initial state management device 15 starts counting the clock pulse. After the start of counting, the wave number of the clock pulse is 500 as indicated by arrow y3.
When the number reaches the counter, the counter in the initial state management device 15
The notification signal p1 is output to the bus access control unit 13. When the notification signal p1 is output, the bus access control unit 13 causes the memory device 101 to read the device ID and the user ID.
The read signal p3 is output to the memory 111.

Thereafter, as shown by arrow y4, when the second period elapses and the number of clock pulses reaches 1000, the counter in initial state management device 15 outputs notification signal p2. The internal reset signal c2 is turned low to the bus access control unit 13.
Start up from W to HIGH. When the internal reset signal c2 rises, the CPU 7 controls the bus access control unit 13 so as to read and execute a command constituting a program from the memory devices 101 and 111.

As described above, the system LS according to the present embodiment
According to I, memory device 1
After the secret data stored in the system LSI is read into the system LSI, the CPU 7 is instructed to start the operation. Therefore, even if a malicious third party attempts to trace the operation of the CPU 7 from outside the system LSI, the secret data is not transmitted. A malicious third party cannot identify the location of the read destination. Since it does not give any clue to the location of the reading destination inside the system LSI, it is possible to defeat the nose of malicious acts of specifying the reading destination of the secret data. This makes it possible to prevent hacking of the STB.

(Second Embodiment) In the first embodiment, since secret data is transmitted on the bus, if a device such as a logic analyzer is connected to the bus and the transmission content of the bus is observed,
It is possible to know secret data in an encrypted state. Even though it is encrypted, the device ID and the user ID may be revealed by performing more detailed reverse analysis on the revealed secret data. The present embodiment proposes an improvement to prevent the disclosure of secret data even when the transmission content of the bus is observed.

FIG. 4 shows the internal configuration of the device according to the second embodiment. As shown in the figure, in the second embodiment, the bus access control unit 13 and the memory devices 101 and 111 are connected by a dedicated serial line 21. In the first embodiment, the secret data is handled in the same manner as the command and other data and transmitted on the data bus. However, in the second embodiment, the system LSI does not transmit the secret data on the bus, Is transmitted on the serial line 21. If the transmission of the secret data from the memory devices 101 and 111 to the system LSI is performed on the serial line 21, the secret data will not be revealed even if the transmission content of the bus is reversely analyzed by the logic analyzer or the like. Serial line 21
In this embodiment, the confidentiality is secured in that the confidential data is transmitted through the network device. Therefore, in this embodiment, the crypt conversion device 14 is not provided in the system LSI, and the confidential data is stored in the memory devices 101 and 111 without encryption. May be stored.

(Third Embodiment) In the first embodiment, the secondary storage is constituted by the memory devices 101 and 111.
In the present embodiment, it is proposed that one memory device 101 configures secondary storage. FIG. 5 shows the internal configuration of the device according to the third embodiment. In FIG. 5, the system LSI
Replaces the bus access control unit 13 that performs bus control with
A device access control unit 31 for controlling a single memory device 101 is provided. The control of the memory device 101 by the system LSI is performed via the control line as in the first embodiment. In the first embodiment, the bus access control unit 13 performs data transmission on the bus, but the device access control unit 31 in the third embodiment performs data transmission on the serial line 32.

The system LSI has a single memory device 10
Since it is sufficient to perform access control on the device 1, simplification of the configuration by the system LSI can be realized as compared with the case where control is performed via a bus. Further, since it is more difficult to perform the reverse analysis on the serial line as compared with the reverse analysis on the bus, it is possible to efficiently protect the disclosure of the secret data without encrypting the secret data.

(Fourth Embodiment) In the first embodiment, the secret data stored in the memory devices 101 and 111 is fetched into the system LSI when the equipment is initialized. Not CPU7
Needs secret data, the memory device 10
It is proposed that secret data be read into the system LSI from 1, 111. In order to realize the reading of the secret data, the memory device 10 shown in the first embodiment is used.
1, 111, the CPU 7, and the initial state management device 15 are improved. Hereinafter, the improvements according to the fourth embodiment will be described.

Memory device 1 in the fourth embodiment
01 and 111 are different from those shown in the first embodiment in that a read command for reading secret data into any one of a plurality of storage areas in a program stored by the memory devices 101 and 111. Is the point that exists.
The second difference is that, in this program, a read instruction for the secret data is arranged before an instruction using the read secret data. The read command for the secret data is different from other read commands in that the read destination of the secret data is not specified. Therefore, even if a person who disassembles the programs in the memory devices 101 and 111 notices the existence of the read command for the secret data, it cannot specify which storage area the secret data is stored in. .

The difference between the CPU 7 in the fourth embodiment and that shown in the first embodiment is that when a read command for secret data is read from the memory devices 101 and 111 and decoded, the read request is sent to the initial state management. Apparatus 1
5 is issued. The initial state management device 15 according to the fourth embodiment does not attempt to read secret data when the device is initialized, and when a read request is issued from the CPU 7, the memory device 101,
The secret data is read from 111, and of the primary storage,
Set to a predetermined storage area. If the secret data is stored in the primary storage, the process using this secret data is
U7 does.

As described above, the initial state management device 15
When U7 decodes the read command and issues a request to read the secret data, the secret data is read, so the timing of reading the secret data is not limited to the time of initialization of the device. Therefore, even if a malicious third party performs a detailed reverse analysis of the data exchange at the time of initializing the device and attempts to obtain secret data, it is possible to evade their relentless reverse analysis.

In this embodiment, the memory device 1
01, 111 and the system LSI are connected by a serial line,
The transmission of the secret data may be performed via a serial line. (Fifth Embodiment) In the first embodiment, data and programs that implement the functions of the devices are stored in the memory devices 101, 1 and 2.
It is clear that it is stored at 11. Therefore, if the stored contents of the memory devices 101 and 111 are copied as they are to another recording medium, copies of programs and data used in the device can be easily created. In the first embodiment, only the device ID and the user ID are encrypted and stored in the memory devices 101 and 111. However, in the fifth embodiment, all data to be stored in the memory device is stored in this memory device. 101, 11
By encrypting and storing using an encryption key (device key) unique to 1, the prevention of dead copy is realized.

FIG. 6 shows a system LSI according to the fifth embodiment.
FIG. 3 is a diagram showing an internal configuration of the device. FIG. 6 differs from FIG.
In FIG. 6, the cryptographic conversion device 14 does not exist and the cross bus switch 6 inside the system LSI and the bus access control
And a cryptographic conversion device 50 is provided. Also the first
In the embodiment, the initial state management device 15 reads the device ID and the user ID from the memory devices 101 and 111 after a lapse of the first period from the time of initialization.
However, in the fifth embodiment, the initial state management device 15 controls the bus access control unit 13 so as to read out the encrypted device key after the same first period has elapsed.

FIG. 7 shows the internal configuration of the encryption conversion device 50. As shown in FIG. 7, the encryption conversion device 50 includes a device key decryption unit 51, a device key storage unit 52, and an EX-OR operation unit 5.
3. An EX-OR operation unit 54 and an EX-OR operation unit 55 are provided. When the encrypted device key is read from the memory device, the device key decryption unit 51 decrypts the device key to obtain the original device key.

The device key storage unit 52 stores the device key decrypted by the device key decryption unit 51. The EX-OR operation unit 53 includes the memory devices 101 and 11
An EX-OR operation is performed on the data to be written to 1 and the device key, and the result is output to the bus access control unit 13. As a result, data to be written to the memory devices 101 and 111 is encrypted with a device key unique to the memory devices 101 and 111.

The EX-OR operation units 54 and 55 store data or instructions read from the memory devices 101 and 111,
Performs an EX-OR operation with the device key and outputs the result to primary storage. Thereby, the memory devices 101 and 111
Within, data or instructions are stored in memory device 101,
Even if the data is encrypted with the device key unique to the memory device 111, the data is decrypted when data is read from the memory devices 101 and 111.

When data is read from or written to the memory devices 101 and 111, the EX-OR operation units 53 to 55 perform an EX-OR operation on the device key and the data. Memory devices 101 and 111
Can be stored. As described above, according to the present embodiment, after the data to be stored in the memory devices 101 and 111 is encrypted using the device key unique to the memory devices 101 and 111,
1 and 111, even if a malicious third party dead copies the stored contents of the memory devices 101 and 111, programs and data cannot be used by other devices. As a result, the confidentiality and copyright of the programs and data are suitably protected.

The device key used for encryption is CP
Before the operation of U7 is started, the operation is taken into the system LSI. Therefore, even if a malicious third party traces the operation of CPU 7, the probability that the device key is exposed is low. In this embodiment, the memory devices 101 and 111 and the system
The connection with the LSI may be performed by a serial line, and the transmission of the secret data may be performed through the serial line.

(Sixth Embodiment) This embodiment relates to an improvement for storing an updated version of an instruction or data stored in \ uSTB in the external memory device 101. The updated version will be broadcast to STBs located in each household. The update version is stored in the external memory device 101 in the STB,
Uses this updated version to upgrade the version of the instruction or data stored therein. The issue here is copyright protection for the updated version. In other words, the updated version
Since it is stored in the external memory device 101 in the STB, a malicious third party can illegally reverse analyze the update version stored in the external memory device 101 or take it out illegally to another device. There is a risk of transplanting. Of course, broadcasters do not sit around to watch this situation, but instead take advantage of broadcasting the updated version after encrypting it using a unique encryption method. Even if such an allowance is made, if the STB stores the updated version in the external memory device 101 as it is, the copyright protection of the updated version is not sufficient. This is because "(i) For example, when uniformly updating the STB installed in 10,000 households and broadcasting an updated version, if the STBs installed in 10,000 households are all in the same state, the external memory device 101 (Ii) The fact that the update version is stored in the same form in all 10,000 household STBs increases the probability that the encryption method for the update version will be exposed. " Put facts on the grounds.

In this embodiment, the fifth embodiment is applied to reading and writing of an updated version encrypted by a broadcaster. The update version encrypted by the broadcaster is encrypted using the device key and then written to the external memory device 101. When the update version is read, the update version read from the external memory device 101 is used as the device key. Instruction cache 8,
The data is taken into the data cache 9.

FIG. 8 shows a system LS according to the sixth embodiment.
FIG. 3 is a diagram showing an internal configuration of I. In FIG. 8, since the update version is multiplexed on the transport stream and broadcast, the transport decoder 1 in FIG. 8 performs a process of acquiring the update version from this transport stream and outputting the updated version to the encryption conversion device 50. Do.

FIG. 9 is a diagram showing the internal configuration of the encryption conversion device 50. The difference between this figure and the encryption conversion device 50 shown in FIG. 7 is that the encryption conversion device 50 shown in FIG.
The difference is that a descrambler 56 is provided instead of the calculation unit 55. Further, the EX-OR operation unit 53 performs an EX-OR operation on the updated version output from the transport decoder 1 and the device key, and outputs the result to the bus access control unit 13 so that the result is written to the external memory device 101. . The EX-OR operation unit 54 decrypts the update version written in the external memory device 101 using the device key, and outputs the decrypted update version to the instruction cache 8 and the data cache 9. Further, the descrambler 56 newly added in FIG. 9 decrypts the update version decrypted by the EX-OR operation unit 54 using the decryption key supplied from the broadcaster to obtain the original update version.

The following can be said as advantages of adopting such a configuration. Comparing the case where the combination of the descrambler and the scrambler is implemented in the system LSI with the case of the present embodiment where only the descrambler is implemented in the system LSI, the former case shows that It is said that there is a high probability that the conversion scheme will be analyzed. Conversely, in the latter case where only the scrambler is implemented, the probability that the encryption method for the updated version is exposed is halved.

Therefore, in this embodiment, the probability that the encryption method is exposed by the broadcaster is reduced by mounting only the descrambler in the system LSI.

[0048]

As described above, the system integrated circuit according to the present invention is a system integrated circuit incorporated in a device together with a memory device storing secret data.
A central processing unit, an access unit that reads and writes to the memory device, an instruction unit that instructs the central processing unit to start operation when the device is initialized, and an instruction unit that starts operation of the central processing unit. A read control unit that controls the access unit to read the secret data. When the equipment is initialized, the secret data stored in the memory device is read into the system integrated circuit, and then the central processing unit is instructed to start the operation. However, a malicious third party cannot specify the location of the read destination from which the secret data has been read. Since no clue is given to the location of the readout destination inside the system integrated circuit, it is possible to prevent the malicious third party from trying to identify the readout destination of the secret data inside the system integrated circuit. This makes it possible to prevent hacking of the device.

Here, the device includes a clock oscillating unit that outputs a clock signal that is a time sequence of a plurality of clock pulses when the device is initialized, and the system integrated circuit determines the wave number of the clock pulse in the time sequence. It comprises a counter for counting, the instruction unit, the count value of the wave number,
When the first predetermined value is reached, the central processing unit is instructed to start an operation. When the count value of the wave number becomes a second predetermined value smaller than the first predetermined value, the read control unit causes The access unit may be controlled to read the secret data from the device. According to this system integrated circuit, the secret data is read from the memory device before instructing the central processing unit to start operation, so that a malicious third party observed the operation of the central processing unit using a logic analyzer. However, the destination of the secret data in the system LSI is not revealed.

Here, the secret data is encrypted data obtained by encrypting identification information of a device or identification information of a user who operates the device, and the system integrated circuit is further read by an access unit. A decryption unit that decrypts the encrypted data to obtain the original identification information,
The central processing unit may perform a process using the original identification information after the operation start is instructed.

According to this system integrated circuit, the identification information used when handling electronic money or the like is encrypted and stored in the memory device, so that even if a malicious third party deadlines the stored content of the memory device. Even if copied, malicious third parties cannot obtain confidential data. Here, the secret data is a device key unique to a memory device, and the system integrated circuit further includes an encryption unit that encrypts data to be written using the device key when data writing is instructed by the central processing unit. And the access unit may write the encrypted data to a memory device.

According to this system integrated circuit, data to be stored in the memory device is encrypted using a device key unique to the memory device and then stored in the memory device. Even if the content stored in the device is dead copied, the program,
The data cannot be used on other devices. As a result, the confidentiality and copyright of the programs and data are suitably protected.

Since the device key used for encryption is taken into the system integrated circuit prior to the start of the operation of the central processing unit, even if a malicious third party traces the operation of the central processing unit, the device key is not deleted. Is unlikely to be exposed. Here, in the device, the memory device is connected to the system integrated circuit via a bus and a serial line, and the access unit, when the reading of the secret data is instructed by the read control unit, via the serial line,
The secret data may be received from the memory device, and the data or the instruction may be received from the memory device via the bus when the reading or writing of the data or the instruction is instructed by the central processing unit. If the transmission of the secret data from the memory device to the system LSI is performed on a serial line, the secret data will not be revealed even if the transmission content of the bus is reversely analyzed by a logic analyzer or the like.

Here, a system integrated circuit connected to a memory device storing secret data and a program comprising a plurality of instructions, wherein the instructions are sequentially taken out of the programs stored in the memory device and are read by a central processing unit. A processing unit, including a storage unit having a plurality of storage areas,
In the program, a read instruction for reading the secret data is arranged before an instruction for performing a process using the read secret data, and the system integrated circuit includes a read command for the central processing unit. May be provided with a read control unit that reads secret data from the memory device and writes the secret data to a predetermined storage area among the plurality of storage areas when decrypting. Since the secret data is read when the central processing unit issues the read command, the timing of reading the secret data is not limited to the time of initialization of the device. Therefore, even if a malicious third party performs a detailed reverse analysis of the data exchange at the time of initializing the device and attempts to obtain secret data, it is possible to evade their relentless reverse analysis.

[Brief description of the drawings]

FIG. 1 is a diagram showing an internal configuration of an STB on which a system LSI is mounted.

FIG. 2 is a diagram illustrating an internal configuration of a system LSI.

FIG. 3 is a timing chart showing a temporal transition of processing of an initial state management device 15;

FIG. 4 is a diagram illustrating an internal configuration of a system LSI according to a second embodiment.

FIG. 5 is a diagram illustrating an internal configuration of a system LSI according to a third embodiment.

FIG. 6 is a diagram illustrating an internal configuration of a system LSI according to a fifth embodiment.

FIG. 7 is a diagram showing an internal configuration of a cryptographic converter 50 provided in a system LSI in a fifth embodiment.

FIG. 8 is a diagram showing an internal configuration of a system LSI according to a sixth embodiment.

FIG. 9 is a diagram showing an internal configuration of a cryptographic conversion device 50.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transport decoder 2 AV decoder 3 Peripheral device interface 4 SRAM 5 Register file 6 Cross bus switch 7 Central processing unit 8 Instruction cache 9 Data cache 10 Fetch unit 11 Instruction decoder 12 Arithmetic operation circuit 13 Bus access control unit 14 Encryption conversion device 15 Initial state management device 21 Serial line 31 Device access control unit 32 Serial line 50 Cryptographic converter 51 Device key decryption unit 52 Device key storage unit 53 to 55 EX-OR operation unit 56 Descrambler 101, 111 Memory device 102 Front end unit 103 Peripheral device 104 External reset signal generator 105 Clock signal oscillator

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B017 AA07 BA07 BA08 CA15 5C025 BA25 BA27 BA30 DA05 DA10 5C064 BA01 BB01 BC03 BC06 BC20 BD09

Claims (13)

[Claims] 1. A system integrated circuit incorporated in a device together with a memory device storing secret data, comprising: a central processing unit; an access unit for reading and writing to the memory device; and a central processing unit when the device is initialized. A system integrated circuit comprising: an instruction unit for instructing the central processing unit to start operation; and a read control unit for controlling an access unit to read secret data from a memory device prior to an operation start instruction to a central processing unit. 2. The device according to claim 1, wherein the device includes a clock oscillating unit that outputs a clock signal that is a time sequence of a plurality of clock pulses when the device is initialized, and the system integrated circuit determines a wave number of the clock pulse in the time sequence. When the count value of the wave number reaches a first predetermined value, the instruction unit instructs the central processing unit to start operation, and the read control unit determines that the count value of the wave number is 2. The system integrated circuit according to claim 1, wherein the access unit is controlled to read the secret data from the memory device when the second predetermined value becomes smaller than the first predetermined value. 3. The system integrated circuit according to claim 2, wherein the instruction to start operation by the instruction unit switches an internal reset signal from an inactive state to an active state. 4. The device includes an external reset signal output unit that switches an external reset signal from an inactive state to an active state, and the counter is configured to output a clock pulse from the time when the external reset signal is switched to a high level. 4. The system integrated circuit according to claim 3, wherein counting of a wave number is started. 5. The secret data is encrypted data obtained by encrypting identification information about a device or identification information about a user who operates the device, and the system integrated circuit is further read by an access unit. A decryption unit that decrypts the encrypted data to obtain the original identification information, wherein the central processing unit performs a process using the original identification information after an instruction to start the operation is given. The system integrated circuit according to claim 1. 6. The secret data is a device key unique to a memory device, and the system integrated circuit further encrypts data to be written using a device key when data writing is ordered by a central processing unit. The system integrated circuit according to claim 1, further comprising an encryption unit, wherein the access unit writes the encrypted data to a memory device. 7. The access unit reads the encrypted data from the memory device when the central processing unit instructs the data read, and the system integrated circuit further performs the encryption read using the device key. 7. The system integrated circuit according to claim 6, further comprising a decoding unit for decoding data. 8. The apparatus includes a receiving unit that receives a broadcast wave, the data to be written to the memory device is data obtained by receiving the broadcast wave by the receiving unit, and is determined in advance by a broadcaster. The data encrypted by the encryption method, and the encryption unit encrypts the data encrypted by the encryption method using a device key when the central processing unit instructs data writing. 8. The system integrated circuit according to claim 7, wherein: 9. The decryption unit decrypts the encrypted data read into the system integrated circuit using a memory device, and then decrypts the data obtained by the decryption based on the encryption method described above. hand,
9. The system integrated circuit according to claim 8, wherein the original data is obtained by decoding. 10. The device according to claim 10, wherein the memory device comprises:
Connected to the system integrated circuit via a bus, the access unit, when the read control unit is instructed to read the secret data, and when the central processing unit is instructed to read or write data or instructions, The system integrated circuit according to claim 1, wherein secret data, data, and instructions are received from the memory device via the bus. 11. The device according to claim 11, wherein the memory device comprises:
The access unit is connected to the system integrated circuit via a serial line, and the access unit is configured to read the secret data by the read control unit or to read or write the data or the instruction by the central processing unit. The system integrated circuit according to claim 1, wherein secret data, data, and instructions are received from the memory device via a serial line. 12. The device according to claim 12, wherein the memory device comprises:
The access unit is connected to the system integrated circuit via a bus and a serial line. The access unit receives the secret data from the memory device via the serial line when reading of the secret data is instructed by the read control unit. The system integrated circuit according to claim 1, wherein when the processing unit instructs reading or writing of the data or the instruction, the data or the instruction is received from the memory device via the bus. 13. A system integrated circuit connected to a memory device storing secret data and a program consisting of a plurality of instructions, the central processing unit sequentially extracting and decoding instructions from the program stored in the memory device. A processing unit; and a storage unit having a plurality of storage areas. In the program, a read instruction to read the secret data is arranged before an instruction to perform a process using the read secret data. The system integrated circuit includes a read control unit that reads secret data from a memory device when the central processing unit decodes the read command and writes the secret data to a predetermined storage area among a plurality of storage areas. A system integrated circuit characterized by the above.