JP2002281077A - Signal receiving device and signal receiving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a delay time required for jitter absorption by simplifying the absorption of the jitter of a real time transmission signal to be transmitted through a packet network such as an IP in which a large amount of jitter is generated. SOLUTION: This signal receiving device is provided with a means 11 for storing a time stamp CR for an RTP and an MPEG-2 system layer in the same dejitter buffer 13, a means 15 for calculating a time TCd according to the storage value 19 of the dejitter buffer 13, and a means 18 for comparing 17 the time stamp CR with the time TCd at the reading side of the dejitter buffer, and for controlling the reading when they are matched.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal receiving apparatus and a signal receiving method, and more particularly, to a general-purpose image or audio coded signal which is a real-time signal and is assumed to be transmitted at a constant speed. However, when the signal is transmitted to a packet network such as an IP having a large amount of jitter, whose arrival time becomes earlier or later, the signal is received on the receiving side with the aim of suppressing the jitter and minimizing the delay time. The present invention relates to a signal receiving device and a signal receiving method.

[0002]

2. Description of the Related Art As a conventional technique relating to an image coding method, various methods are known.
There are a fixed-length coding method in which a fixed codeword length is assigned to each sampling point (pixel) and a variable-length coding method in which a variable-length codeword is assigned. Although variable-length coding has a complicated structure, the average codeword length can be essentially shortened because a codeword having an optimum length can be assigned according to the probability of occurrence of an event. , Transmission efficiency can be improved. For this reason, variable length coding has been widely adopted.

However, in variable-length coding, since the codeword length for each screen is different, it is necessary to synchronize the screens on the transmission side and the reception side. For this reason, the transmitting side acquires the value of the time information called STC at a period of, for example, 100 ms, and transmits it to the receiving side as time information (time stamp) called PCR. The receiving side recovers the time STC using the transmitted time stamp PCR, and decodes the image and the audio signal. The recovery of the time STC means that the receiving side counts with a counter using a system clock of a predetermined frequency, creates the time STC, compares the time STC with the received time stamp PCR, and the comparison is consistent. In this manner, the control is performed by increasing or decreasing the frequency of the system clock.

Since the above-mentioned system clock is used in the entire decoding apparatus, the image display is also defined by the system clock. For this reason, if the system clock deviates significantly from the normal frequency, the image monitor cannot display an image. Also, when the system clock fluctuates in a relatively short cycle, the clock generated by the color control signal demodulation voltage-controlled oscillator of the image monitor does not fluctuate in response to the fluctuation even if the deviation width itself is small. Interference such as unevenness may occur.

[0005] When an ATM network or a dedicated line network with small jitter is used as the transmission path, the time stamp PCR arrives with small jitter, so that the receiving side can easily recover the system clock and the time STC. However, as is clear from the above-described method of generating the system clock, the receiving side is required to receive a large amount of jitter when the reception time of the time stamp PCR transmitted at a constant period fluctuates greatly without observing the above-mentioned period. The above-mentioned PCR
Cannot be correctly compared with the time STC at the time of arrival of the PCR, and it is difficult to correctly recover the system clock and the time STC. That is, as described above, problems such as the inability to display an image on the image monitor and the occurrence of color unevenness occur.

The causes of jitter in a packet network are as follows. The packet network is designed to reliably transmit non-real-time data, and is configured to transmit data in bursts only when there is data. That is, a network node constituting a packet network includes a device called a router or the like, which stores a received signal in a memory in the router once, and then transmits the signal only when there is room for transmission to the network. Transmit the signal. For this reason, there is a variation in how long each data is stored in a router or the like. Also, when the amount of data actually flowing increases as compared with the transmission capacity, the waiting time in the router increases, so that not only the delay as a whole increases but also the jitter increases.

As a prior art (first prior art) for solving the above-mentioned problem, for example, "ITU Recommendation H.222.0 A"
The technology described in “nnex J.2 First example” is known. In the first prior art described in this recommendation, before receiving the above-described time stamp PCR on the receiving side, the data is stored in one bit.
In this method, data is stored in a FIFO (buffer memory for first in first out) and data is read out from the FIFO at a constant speed so that the accumulation amount of the FIFO is satisfied to a certain amount (for example, half). In this method, if the arrival speed of the received signal varies, that is, if the jitter is large, the accumulation amount of the FIFO also varies, so that the reading speed from the FIFO must be varied according to the variation of the accumulation amount. . Therefore, this method can be applied to a case where the jitter is relatively small such as an ATM network.
When the jitter of the input signal is extremely large, the readout speed from the FIFO varies correspondingly, which is difficult to apply.

In general, the MPEG-2 decoding apparatus performs decoding processing based on the reading speed, and performs display on an image monitor based on this speed. As is well known, an image monitor cannot reproduce a color if the subcarrier frequency for transmitting a color difference signal of an image signal to be displayed is about 200 to 300 ppm, which deviates from a prescribed frequency: 3.5795 MHz. Therefore, if the reading speed has a large jitter,
Jitter may also occur in an image signal output to an image monitor using the same, and the subcarrier frequency may deviate from a specified value, and the color signal may not be reproduced beyond the range of the image monitor.

As another prior art (second prior art) capable of solving the above-mentioned problem, there is also an "IT
The technology described in "U. Recommendation H.221.0 Second Example of Annex J.2" is known. This second conventional technique is based on the following procedure.

(1) In the network adaptation layer (in the IP network, a method called RTP: Real Time Protocol is applied), the C provided to the RTP layer
From a time stamp called R, the PLL (Phased Lock L
oop) or the like, an RTP time called TC is extracted.

(2) The time TCd is calculated by subtracting the time (J / 2: J is the peak-to-peak value of the jitter) necessary for absorbing the jitter from the time TC.

(3) The data received via the packet network is separated into an MPEG-2 system layer and the above-mentioned CR, and stored in a de-jitter buffer and a jitter removal control circuit, respectively.

(4) The jitter elimination control circuit is provided in the above (2).
And compares the time TCd generated in the above with the stored CR and reads out the signal of the MPEG-2 system layer corresponding to the CR.

(5) The MPEG-2 decoding apparatus uses the MPE
A decoding system clock and a time STC are generated from the time stamp PCR in the G-2 system layer, and normal decoding is performed.

(6) Thus, a normal receiver can be configured by absorbing a large jitter caused by the packet network.

FIG. 5 shows the IP according to the second prior art described above.
FIG. 6 is a block diagram showing the configuration of the signal receiving device, and FIG. 6 is a block diagram showing the configuration of the time recovery circuit in FIG. 5. The prior art will be described with reference to these drawings. 5 and 6, reference numeral 6 denotes an IP signal receiving apparatus, 11 denotes a network transport packet decoding circuit, 12 denotes a network data packet decoding circuit, 13 denotes a de-jitter buffer, 14 denotes a write address (WA) counter, 1
5 is a time (TC) recovery circuit, 16 is a difference circuit, 17 is a jitter removal control circuit, 18 is a read address (RA) counter, 31 is a counter, 32 is a comparison circuit, 33 is a smoothing circuit, and 34 is a voltage controlled oscillator. It is.

In the signal receiving apparatus 6 shown in FIG. 5, only the signal to be received is received by the network transport packet decoding circuit 11 from the received packet signal, and the header and the like of the packet in the transport layer are removed. Thus, the network data is transferred to the network data packet decoding circuit 12. The network data packet decoding circuit 12 decomposes the packet and
The time stamp CR for P is extracted and the time stamp CR is extracted.
Is written into the time recovery circuit 15 and the jitter removal control circuit 17, and the MPEG-2 system layer signal is written into the de-jitter buffer 13. The write address of the de-jitter buffer 13 is specified by the WA counter 14.

The time recovery circuit 15 has a time stamp CR.
From time TC. In order to suppress the underflow of the de-jitter buffer 13 due to the jitter, the difference circuit 16
Is the value obtained by multiplying the peak-to-peak value of the jitter by 1/2.
By subtracting / 2 from TC, a time TCd delayed from TC is generated, and the time TCd is notified to the jitter removal control circuit 17.

The jitter removal control circuit 17 stores the time stamp CR, delays the time stamp CR in synchronization with the corresponding MPEG-2 system layer signal stored in the de-jitter buffer 13, and compares the time stamp CR with the time TCd. If they match, the read address counter 18 is incremented to read the corresponding MPEG-2 system layer signal from the de-jitter buffer 13.

In the signal receiving device 6 shown in FIG. 5 operating as described above, since the value of the time TC is synchronized with the time TC of the transmitting side, the signal receiving apparatus 6 has a predetermined delay time After (J / 2), the MPEG-2 system layer signal can be read from the de-jitter buffer 13, and the jitter can be removed in principle. In addition, even if there is slight jitter in the system clock recovered on the receiving side, an image monitor (not shown) that displays the MPEG-2 system layer signal performs display with no problem in image quality as long as the color difference signal is within the allowable range. be able to.

The time recovery circuit 15 in the signal receiving device 6 is configured as shown in FIG. And
The counter 31 is initialized to the value of CR provided from the network data packet decoding circuit 12, and thereafter,
Every time R is given, the value of CR given and the counter 31
Is compared by the comparison circuit 32. After the result of the comparison is smoothed by the smoothing circuit 33, it is input to the voltage controlled oscillator 34, and the clock is recovered. The clock is input to the counter 31 and increments the counter value. This clock is substantially synchronized with the clock for generating the CR on the transmitting side, and the value of the counter 31 operates so as to substantially match the value of the counter for generating the CR on the transmitting side. The reason why they do not completely match is that the time difference between the transmission time on the transmission side and the arrival time on the reception side of the CR is not constant due to jitter or the like. As described above, the time recovery circuit 15
The clock and time on the transmitting side can be reproduced almost correctly on the receiving side.

In the above-mentioned second prior art, a clock called TC is reproduced from a received CR instead of directly reproducing a read clock from the remaining amount of the FIFO. TC is 90kHz regardless of transmission speed and its jitter
It is. Also, the clock on the transmitting side that is generating the CR
Since the frequency is 90 kHz and this value is generated from the camera signal, the frequency accuracy of the camera signal can be guaranteed. It is known that the accuracy of a camera signal is extremely high, about ± 10 ppm. Therefore, if the receiving clock range is set to, for example, about ± 100 ppm, the receiving clock can be synchronized with the transmitting clock with a sufficient margin, and the image monitor can be locked. It is also possible to keep it within the range.

[0023]

The above-described second prior art is capable of better suppressing the jitter than the first prior art, but the RTP time stamp CR and the RTP time stamp CR are different from each other. Since the signals of the MPEG-2 system layer are stored separately, there is a problem that the management becomes complicated and it is difficult to reduce the size of the apparatus and make it economical. Also, in the second conventional technique, CRs are transmitted at equal intervals on the transmission side. Therefore, when applied to a network having a small jitter such as an ATM network, CRs arriving at CRs are almost equally spaced. It is relatively easy to reproduce the TC from this, but when applied to a network with a large jitter such as a packet network, the arrival of CRs will be at irregular intervals.
Reproducing C naturally requires complicated logical operations, which causes a problem that the circuit scale becomes large.

Further, in the above-mentioned second conventional technique, J / 2 is subtracted from TC as a value for absorbing jitter, and the MPEG-2 system layer corresponding to each CR is read out. If it fluctuates, the jitter cannot be completely absorbed and the de-jitter buffer underflows, causing a transmission error, or
MPE by giving more absorption capacity than necessary
An object of the present invention having a problem that a G-2 system layer signal may be greatly delayed is to receive a jitter generated when a real-time signal such as an image coded signal is transmitted through a packet network. It is an object of the present invention to provide a signal receiving apparatus and a signal receiving method capable of receiving signals while suppressing the delay on the side and minimizing the delay time.

[0025]

According to the present invention, an object of the present invention is to provide a signal receiving apparatus for receiving a real time signal via a packet network, wherein a time stamp signal for transmitting time information on a transmitting side and a real time signal are transmitted. Means for storing in the same buffer memory, means for recovering the clock and time information on the transmission side in accordance with the accumulated amount of the buffer memory, and comparing the time stamp with the recovered time information on the reading side of the buffer memory. Means for reading out a real-time signal from the buffer memory when they match.

That is, specifically, the present invention relates to RTP
Means for storing the time stamp CR for use in the same dejitter buffer as the MPEG-2 system layer, means for calculating the time TCd according to the accumulated amount of the dejitter buffer,
A means for reading out the de-jitter buffer when the CR and the time TCd are compared and matched on the read side of the de-jitter buffer.

[0027]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a signal receiving apparatus according to the present invention.

FIG. 1 is a block diagram showing the overall system configuration for transmitting a real-time signal such as an image or audio signal through a packet network. First, referring to FIG. A system configuration for transmitting a real-time signal such as a signal through a packet network will be described. In FIG. 1, reference numeral 1 denotes a camera, 2 denotes a microphone, 3 denotes an image and sound encoding device, 4 denotes a packet signal transmitting device, 5 denotes a packet network, 6 denotes a signal receiving device, 7 denotes an image and sound decoding device, and 8 denotes an image monitor. , 9 are speakers.

In the system shown in FIG. 1, an image signal picked up by the camera 1 and a sound signal picked up by the microphone 2 are encoded by an image / speech encoding device 3 and suitable for an IP network by a packet signal transmitting device. After being converted into the format, it is output to the packet network 5. Packet signal receiving device 6
Receives the packet signal transmitted from the IP transmission network 5, converts the packet signal into an appropriate format, and then transfers the signal to the video / audio decoding device 7. The image / sound decoding device 7 restores the image signal or the sound signal in a procedure reverse to the coding in the image / sound coding device 3, and outputs it to the image monitor 8 or the speaker 9.

FIG. 2 is a block diagram showing a configuration of a signal receiving apparatus according to an embodiment of the present invention. FIG. 3 is a diagram for explaining a change in the amount of data stored in a de-jitter buffer. FIG. 4 is a time recovery circuit in FIG. FIG. 3 is a block diagram showing the configuration of FIG. 2 and 4, 19 is an accumulation amount counter, 21 is a difference circuit, 22 is a positive / negative judgment circuit, 23 is a switch, 24
Is a multiplying circuit, 25 is an averaging circuit, 26 is a voltage controlled oscillator, 27 is a counter, and the reference numerals of the terminals are the same as those in FIG.

In the signal receiving apparatus 6 according to the embodiment of the present invention shown in FIG. 2, the received IP signal is transmitted by the network transport packet decoding circuit 11 in the same manner as in the case of the prior art described with reference to FIG. The port layer packet header is removed to generate a network data packet. This network data packet is written directly to the de-jitter buffer 13. The write address is specified by the WA counter 14.

The time recovery circuit 15 includes a WA counter 14
The accumulation amount of the de-jitter buffer 13 obtained by the accumulation amount counter 19 counting the difference between the data and the RA counter 18 is input. The time recovery circuit 15 controls and reproduces the speed of the system clock so that the value obtained by time-averaging the accumulated amount of the de-jitter buffer 13 becomes a constant value, and generates the receiving-side time TCd from the system clock. I do. That is, when the average value of the accumulated amount of the de-jitter buffer 13 increases, the time recovery circuit 15 speeds up the TCd by increasing the system clock in order to increase the reading speed, and conversely, the average value of the accumulated amount decreases. If you do, slow down the system clock and
Delay d.

The point that the time recovery circuit 15 of the embodiment of the present invention generates the system clock from the accumulated amount is as follows.
Same as in the first prior art described above, but
In the embodiment of the present invention, the frequency of the system clock is synchronized with the system clock on the transmission side. That is,
Since it is known that the system clock frequency on the transmission side is stable to about ± 10 ppm, the control range of the system clock frequency on the reception side is set to ± 100 ppm as in the case of the second prior art described with reference to FIG. It can be limited to the degree. Therefore, the jitter of the image signal generated from such a system clock can be suppressed to ± 200 ppm to 300 ppm or less at which the color difference signal can be reproduced, and a normal display can be performed.

The initialization of the time recovery circuit 15 is performed as follows. That is, when the time recovery circuit 15 is initialized, the de-jitter buffer 13 performs the idle reading until the time stamp CR is detected, and when the CR is detected, the reading is stopped there. Next, when the accumulated amount of the de-jitter buffer 13 reaches a predetermined value, reading of the de-jitter buffer 13 is started, and the value of CR is written to the time recovery circuit 15 to initialize the time recovery circuit 15. Become

Network data packet decoding circuit 1
2 extracts the CR from the network data packet read from the de-jitter buffer 13 by the RA counter 18 and notifies the jitter removal control circuit 17 of the CR, deletes the headers of the network data packet,
The EG-2 system layer signal is transferred to the video / audio decoding device 7 shown in FIG.

The jitter removal control circuit 17 includes TCd and CR
The RA counter 18 is incremented when they match, and the de-jitter buffer 13 is read.

The signal receiving device according to the embodiment of the present invention comprises:
By providing the above-described configuration and performing the above-described processing operation, an operation equivalent to that of the second related art can be realized with a simpler circuit.

The above-described embodiment of the present invention has a feature that the accumulated amount is used for generating TCd. Therefore, the signal delay time can be reduced while absorbing jitter by the method described below. .

That is, as the evaluation function at the time TCd recovery, the absolute value of the difference between the accumulated amount and the threshold is added when the accumulated amount is equal to or larger than the threshold, and the absolute value of the difference is subtracted when the accumulated amount is smaller than the threshold. You may make it smooth. In this case, as shown in FIG. 3A, the average delay time is constant whether the jitter is large or small. On the other hand, as shown in FIG. 3B, a relatively small threshold is set in order to minimize the accumulation amount. When the accumulation amount is equal to or larger than the threshold value, the difference between the accumulation amount and the threshold value is set. Add the absolute value,
When the difference is smaller than the threshold, the absolute value of the difference between the threshold and the accumulated amount may be multiplied by a large weight N and then subtracted and averaged.
Since the ratio of the area of the region where the delay time is greater than the threshold value to the area of the region where the delay time is less than the threshold value is the reciprocal of the above-described weight, the weight N (N may be, for example, a value of about 10 to 100) is The larger the area, the smaller the area of the region below the threshold. Therefore, the variation in the accumulation amount when weighting is performed is illustrated in FIG. 3B. When the jitter width is small, the accumulation amount is reduced, and the delay time can be reduced. When the jitter is large, the minimum value of the storage amount hardly changes, but the average value increases. As a result, the delay time is automatically increased, and the underflow in the de-jitter buffer 13 can be prevented.

The above-described threshold value may be set to a minimum value at which the de-jitter buffer 13 does not cause underflow within a range where jitter is assumed.

Next, an example of the time recovery circuit 15 having a circuit for averaging by changing the weight according to the sign of the difference between the threshold value and the accumulation amount will be described with reference to FIG.

The time recovery circuit 15 includes a WA counter 14
Buffer 1 that is the difference between the
The accumulated amount of No. 3 is calculated by the accumulated amount counter 19, and the result is input. As shown in FIG. 4, the time recovery circuit 15 includes a difference circuit 21, a positive / negative determination circuit 22, a switch 23 for selecting a weight, a multiplication circuit 24, an averaging circuit 25, a voltage controlled oscillator 26, and a counter 27. ing.

In the time recovery circuit 15 shown in FIG. 4, the difference circuit 21 calculates the difference between the input storage amount of the de-jitter buffer 13 and the threshold. This calculated difference is
Positive / negative is determined by the positive / negative determination circuit 22, and “1” or a large value “N” is selected as a weight by the switch 23 depending on the result. The selected weight is multiplied by the output of the difference circuit 21 by the multiplication circuit 24, smoothed by the averaging circuit 25, and input to the control terminal of the voltage controlled oscillator 26. The voltage controlled oscillator 26 increases or decreases the frequency of the system clock according to the voltage of the control terminal.
This system clock is applied to a counter 27, which generates a time TCd. Therefore, this time T
Cd is controlled so as to be faster or slower in accordance with the accumulation amount of the de-jitter buffer 13.

At this time, if the value of the above-mentioned weight is set to "1", simple averaging as shown in FIG.

In the embodiment of the present invention described above, the time stamp CR for transmitting the time information on the transmitting side and the real-time signal obtained by encoding the image and the like are stored in the same buffer memory, and stored in the buffer memory. It has been described that the clock and time information on the transmission side are recovered in accordance with the amount, and the above-described time stamp CR is compared with the recovered time information on the reading side of the buffer memory, and the real-time signal is read when they match. The present invention can be modified as described below.

That is, according to the present invention, as a measure against packet loss, numbers may be sequentially assigned to packets. For example, MPEG over IP includes Real Time Prot
There is a protocol called ocol (hereinafter referred to as RTP), and a sequence number is given to each packet. According to the method based on this protocol, if a packet does not arrive, or if the packet arrives, and the packet is discarded due to a parity error or the like, the received sequence number becomes discontinuous, so that packet loss or discard can be detected.

In the above-described embodiment of the present invention, in the case of using the above-described protocol, if there is a packet loss or a packet is discarded, the accumulation amount of the de-jitter buffer 13 is reduced, and the control for the time recovery circuit 15 is This is performed so as to unnecessarily lower the system clock frequency. In order to prevent this, according to the present invention, when packet loss or packet discarding is detected as described above, the de-jitter buffer 13 of the address corresponding to the corresponding packet number is used.
By writing a pseudo signal corresponding to a lost or discarded packet into the buffer and deleting the pseudo signal when reading from the de-jitter buffer 13, it is possible to prevent the accumulation amount from being affected.

Although the embodiment of the present invention controlled as described above has been described as receiving a signal for an MPEG-2 system signal, the present invention relates to a method for receiving a signal in a system for transmitting an arbitrary real-time signal having a time stamp. Can be applied to

According to the above-described embodiment of the present invention, MP
Since the real-time signal such as the EG-2 system data and the time stamp CR are stored in the same buffer memory, it is easy to correlate the signals, and the control of signal reception is simplified. can do.
Further, according to the embodiment of the present invention, since the time on the receiving side is recovered using the storage amount of the buffer memory, the signal storage amount in the buffer memory is minimized within a range in which jitter can be absorbed. Therefore, the delay time due to the buffer can be suppressed to a necessary minimum.

[0050]

As described above, according to the present invention, it is possible to suppress the jitter that occurs when a real-time signal is transmitted through a packet network on the receiving side and to receive the signal while minimizing the delay time. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall system configuration for transmitting a real-time signal such as an image or an audio signal through a packet network.

FIG. 2 is a block diagram illustrating a configuration of a signal receiving device according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a change in a data storage amount in a de-jitter buffer.

FIG. 4 is a block diagram showing a configuration of a time recovery circuit in FIG. 2;

FIG. 5 is a block diagram illustrating an example of a configuration of a signal receiving device according to a conventional technique.

FIG. 6 is a block diagram illustrating a configuration of a time recovery circuit in FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Camera 2 Microphone 3 Image audio encoding device 4 Packet signal transmitting device 5 Packet network 6 Signal receiving device 7 Image audio decoding device 8 Image monitor 9 Speaker 11 Network transport packet decoding circuit 12 Network data packet decoding circuit 13 De Jitter buffer 14 Write address (WA) counter 15 Time (TC) recovery circuit 16, 21 Difference circuit 17 Jitter removal control circuit 18 Read address (RA) counter 19 Accumulated amount counter 22 Positive / negative judgment circuit 23 Switch 24 Multiplier circuit 25 Averaging Circuit 26 Voltage controlled oscillator 27 Counter 31 Counter 32 Comparison circuit 33 Smoothing circuit 34 Voltage controlled oscillator

Continued on the front page (72) Inventor Noriyoshi Torii 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Within the Social Network Systems Division, Hitachi, Ltd. (72) Inventor Susumu Takase 216 Totsukacho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Address Co., Ltd. Social Network Systems Division, Hitachi, Ltd. (72) Inventor Yuji Omori 4-1, Egasaki, Tsurumi-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Tokyo Electric Power Company, Inc. F-term (reference) 5C059 KK00 MA00 RB02 RC04 RC32 SS30 TA71 TB04 TC15 TC45 TD11 UA32 UA38 5K030 GA11 HA10 HB02 HB15 HB28 KA03 KA21 MB15 5K047 AA06 AA18 BB15 DD02 GG09 MM12 MM24

Claims (4)

[Claims] 1. A signal receiving apparatus for receiving a real time signal via a packet network, means for storing a time stamp signal for transmitting time information on a transmitting side and a real time signal in the same buffer memory, and a buffer memory. Means for recovering the clock and time information on the transmitting side according to the accumulated amount of
Means for reading a real-time signal from the buffer memory when the time stamp and the recovered time information are compared and matched on the reading side of the buffer memory. 2. The means for recovering the clock and time information on the transmission side comprises: means for comparing a storage amount of the buffer memory with a predetermined threshold value to obtain a difference; and wherein the storage amount of the buffer memory is predetermined. Means for multiplying the difference by a weight of 1 when the difference is greater than or equal to the threshold, and means for multiplying the difference by a larger weight when the accumulation amount of the memory is smaller than the predetermined threshold; 2. The signal receiving apparatus according to claim 1, further comprising: a unit that recovers the clock using a converted value. 3. A signal receiving method for receiving a real-time signal via a packet network, wherein a time stamp signal for transmitting time information on the transmitting side and the real-time signal are stored in the same buffer memory, and stored in the buffer memory. Recovering the clock and time information on the transmission side according to the amount, and reading the real-time signal from the buffer memory when the time stamp and the recovered time information match on the reading side of the buffer memory and match. A signal receiving method characterized by the above-mentioned. 4. The recovery of the clock on the transmission side is performed by comparing a storage amount of the buffer memory with a predetermined threshold to obtain a difference. When the storage amount of the buffer memory is equal to or larger than the predetermined threshold, the difference is calculated. Is multiplied by a weight of 1, and when the accumulated amount of the memory is less than the predetermined threshold, the difference is multiplied by a larger weight, and the clock obtained by smoothing the difference multiplied by the weight in the time direction is recovered. 4. The signal receiving method according to claim 3, wherein the method is performed.