JP2002281039A - Packet transmitter-receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of the transmission overhead by reducing the delay of the start of transmission due to a transmission start threshold on an FIFO buffer in transmission. SOLUTION: In transmitting data, the data length of a packet to be transmitted is compared with each transmission data threshold, and the minimum transmission data threshold in a transmission data threshold to which the data length is applied is selected, and a transmission start threshold making a pair with the selected transmission data threshold is set at a transmission control part so that a transmitting operation can be executed. For example, when the data length is 800 bytes, the minimum transmission data threshold in the applied transmission data thresholds is 1024 bytes, and the transmission start threshold corresponding to this is 256 bytes. The data DMA(direct memory access)- transferred from a packet area are stored in a transmission FIFO buffer, and when the number of bytes of the data received by the transmission FIFO buffer exceeds the transmission start threshold set at the transmission control part after the start of the DMA, the transmission control part starts the transmission of the data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet transmitting / receiving apparatus for packet communication such as Ethernet, and more particularly to a packet transmitting / receiving apparatus for dynamically controlling a packet transmission start timing.

[0002]

2. Description of the Related Art Ethernet (registered trademark), IEEE1394,
In a communication method such as USB, communication is performed by transmitting and receiving data in packet units. Ethernet is IEEE
It is defined in the 802.3 standard and is a CSMA / CD network standard. IEEE1394 is a communication system defined by the IEEE1394 standard as its name implies. USB is a communication system planned by the USB Consortium.

In these communication systems, variable-length packets are used. Usually, a buffer such as FIFO is provided on a control device implemented by an application specific integrated circuit (ASIC), etc.
The type, length, etc. of the received packet are determined, and the data packet to be processed by the own station is transferred to the packet area on the main memory by DMA and processed, and conversely, the transmission is performed on the main memory. Transmission is performed while transferring data from the packet area by DMA.

[0004]

The problem in packet transmission is the speed difference between the external speed and the DMA speed. In consideration of the case where the DMA is delayed due to the execution of another DMA, a sufficient amount of data for practical use is
It is usual practice to start transmission at the time of entering the buffer (a fixed transmission start threshold is set as this practically sufficient amount).

Thus, a transmission underrun state in which the DMA cannot keep up with the transmission speed is avoided. However, in the case of Ethernet, there is a large variation in packet size from 64 bytes to 1518 bytes. If a sufficient capacity is secured as a threshold value in consideration of the rare case in the case of a large packet length, whether the amount of data in the FIFO buffer exceeds the threshold value in all packets including the case of short packets, In the case of a bucket having a size equal to or smaller than the threshold value, transmission starts when the end of the packet is detected. This means that the start of transmission is always delayed until an input for the threshold value is received, and this delay in transmission start is a problem.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, to reduce the delay of transmission start due to a transmission start threshold value on a FIFO buffer at the time of transmission, and to eliminate transmission overhead.

[0007]

SUMMARY OF THE INVENTION According to the present invention, in a packet communication such as Ethernet, a part of a packet is taken in a temporary buffer such as a FIFO memory to interpret a protocol, and the packet is transmitted from another device. A packet transmitting / receiving apparatus that transfers a packet to a packet area on an internal main memory when the packet is to be processed by its own station, and transmits the packet when the packet is from a packet area on a main memory in the apparatus. This is achieved by providing a changing means for dynamically changing the transmission start timing according to the transmission packet length.

[0008] Further, the object is that the changing means is arranged to transmit, to the transmission FIFO, data of a transmission start threshold byte number corresponding to a minimum packet data threshold among packet data thresholds to which a packet length applies. Achieved by starting transmission when entered.

The above object is achieved by providing, as a table, pairs of a packet data threshold value and a corresponding transmission start threshold byte number.

[0010] The above object is achieved by providing means for registering the table.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below, taking a packet transmitting / receiving apparatus conforming to the case of Ethernet based on the IEEE802.3 standard as an example.

FIG. 1 shows an example of the configuration of a packet transmission / reception system, including a program ROM 1, a main memory 2, and a CPU.
3, a network adapter 4, and a system bus 5. In this configuration example, the one corresponding to the packet transmission / reception device of the embodiment of the present invention is a network adapter 4 implemented by an ASIC (application-specific integrated circuit) or the like.

The packet transmission / reception system includes a program RO
When M1 is activated, network adapter 4
Send and receive using the function of. Transmission and reception of packets are performed by DMA to the main memory 2. Main memory 2
A packet buffer for managing the above packet area to be DMA is also placed in the main memory 2, and the network adapter card reads the contents by DMA and writes back the management information.

FIG. 2 shows the configuration of a packet transmission / reception device (network adapter).
3, FIFO RAMs 14, 17, transmission FIFO buffer 15, reception
FIFO buffer 16, network management unit 18, transmission control unit 19, Ethernet controller 20, reception control unit 2
1, clock 22, encoder 23, decoder 24, AU
The host interface 13 includes an EEPROM 11 and a boot PROM 1.
2 are connected.

[0015] The preamble removal, CRC check,
The reception control unit 21 and the Ethernet controller 20 perform reception control specified by IEEE 802.3 on the decoded data including processing such as pad removal. The Ethernet controller 20 receives a data packet determined to be a packet to be received by the packet transmitting / receiving device, and the received data packet is copied to the reception FIFO buffer 16. The copied contents are DMA-transferred by the function of the host interface 13 and DMA-transferred to the main memory 4 via the system bus 5.

The transmission is performed by DMA by the function of the host interface 13, and the packet data in the main memory 4 is DMA-transferred via the system bus 5 and sent to the transmission FIFO buffer 15. The data in the transmission FIFO buffer 15 is subjected to transmission control defined by IEEE 802.3, processed by the encoder 23 for preamble addition, CRC generation, pad data generation, and the like, and then transmitted from the twisted pair transceiver 26 to the network. Sent to.

FIG. 3 shows the configuration of the packet buffer. FIG. 4 shows the structure of a descriptor which is a component of the packet buffer.

The packet buffer is, as shown in FIG.
This is the area on the main memory for managing the packet area that is the target of DMA. In the embodiment of the present invention, one
It has two input packet buffers and one result holding packet buffer for reception. The packet buffer for reception manages packet areas having different lengths. The packet buffer is composed of a plurality of descriptors. The descriptor has a link for holding the address of the next descriptor, and forms a normal ring buffer. Further, the descriptor has a status for storing status information of the packet area, and a packet area address indicating the head address of the packet area.

One descriptor of the packet buffer for transmission represents one packet, and one packet may be composed of a plurality of packet areas. That is, one packet can be distributed to a plurality of areas.

In the descriptor shown in FIG. 4, the address of the next descriptor is set in the link field. The OWN bit is included in the control bit of the status field, the number of packet areas in which one packet managed by the descriptor is stored is set in the number of packet areas, and the data length of the packet is set in the data length. Is set. In the field of the packet area address, there are a number of pairs of the packet area length and the packet area address corresponding to the data length of the packet, and the packet area length is the length (size) of the packet area.
Is set, and the head address of the packet area is set in the packet area address.

At the time of transmission, the host interface 13 loads the descriptor of the packet buffer set by software by DMA, checks the OWN bit of the control bit in the descriptor, and performs transmission only when the OWN bit is set. When not standing, the descriptor is re-read by DMA at certain time intervals,
Either a polling mode that repeats until the OWN bit is set or a batch mode that stops operation on the fly.

When the OWN bit is set, it is assumed that the packet area addresses for the number of packet areas are specified, and the transmission data is transferred from the packet area indicated by the packet area address to the transmission FIFO buffer 15 by DMA. The data stored in the transmission FIFO buffer 15 is transmitted. Data for one descriptor (ie, 1
Transmission of data for one packet),
The same processing is performed for the descriptor specified by the address indicated by the link of the descriptor. However, if the address indicated by the link is 0, the transmission is stopped (that is, a transmission end interrupt is generated for software).

FIG. 5 shows a processing flow at the time of transmission.

First, a transmission data threshold value / transmission start threshold value correspondence table register group is set (step 511).

FIG. 6 shows an example of the transmission data threshold value / transmission start threshold value correspondence table register group. A plurality of pairs of transmission data (packet data) threshold values and corresponding transmission start threshold values are provided. This is a register group that can be registered. In the embodiment of the present invention, five pairs can be registered. In the example of FIG. 6, 64 bytes, 128 bytes, 512 bytes, 1024 bytes, and 2048 bytes are set as the transmission data threshold values in the transmission data threshold registers 1 to 5, respectively. 32, 64, 128, and 25, respectively, in the transmission start threshold registers 1 to 5 paired with
6 bytes and 512 bytes are set.

At the time of data transmission, the data length (packet length) of the packet to be transmitted is compared with each transmission data threshold value,
Select the minimum transmission data threshold among the transmission data thresholds to which the data length applies. Then, a transmission start threshold value paired with the selected transmission data threshold value is
Select as the transmission start threshold for the packet to be transmitted. The transmission operation is performed by setting the selected transmission start threshold in the transmission control unit.

For example, the data length of a packet to be transmitted is 8
If the transmission data threshold value is 00 bytes, the minimum transmission data threshold value among the applicable transmission data threshold values is 1024 bytes, and the transmission start threshold value paired with the transmission data threshold value is 256 bytes. The threshold is 256
It becomes bytes.

Next, the address of the first descriptor is set in the host interface (step 512).

Next, a transmission start instruction is issued to the host interface (step 513).

The host interface reads the address of the set descriptor, and loads the descriptor by DMA using this address (step 51).
4).

It is determined whether the OWN bit is set in the control bit of the status field of the loaded descriptor, that is, whether the OWN bit is "1" (step 515).

If the OWN bit is "1", step 5
Proceed to 16.

When the OWN bit is 0, the process goes to '1' by polling. When the OWN bit is '1', the process proceeds to step 516.

Next, the data length of the status field of the loaded descriptor is compared with the transmission data threshold set in the set transmission data threshold / transmission start threshold correspondence table register group. Select the minimum transmission data threshold among the transmission data thresholds to which the data length of the status field applies, and set the transmission start threshold paired with the selected transmission data threshold for transmission of the packet to be transmitted. Select as starting threshold. The selected transmission start threshold is set in the transmission control unit (step 516).

Next, the data in the packet area specified by the packet area address of the loaded descriptor is transferred to the transmission FIFO buffer by DMA (517).

When step 517 is completed, the next descriptor address is set in the host interface (step 518). Then, the processing from step 514 is repeated.

Next, packet transmission control is performed by a transmission control unit.

The data transferred from the packet area by DMA is stored in the transmission FIFO buffer. Transmit after DMA starts
When the number of bytes of data received in the FIFO buffer exceeds the transmission start threshold value set in the transmission control unit, the transmission control unit starts transmitting data (step 519).

Data transmission is performed while data is taken out from the transmission FIFO buffer (step 520).

When the DMA for the designated data length is completed, data indicating the end of the packet is written to the transmission FIFO buffer. Upon receiving this packet end data, the transmission control unit performs packet end processing and returns to the original state.

When the DMA is completed, the host interface sets the next descriptor specified by the descriptor and repeats the same processing.

In the description of the embodiment of the present invention, the temporary stop of the DMA and the transmission error processing when a collision or an error occurs during transmission are not particularly related to the essence of the invention itself. The description of the transmission error processing is omitted.

In the description of the embodiment of the present invention, ethe
Although the case of rnet is described, it is obvious that the same processing can be used to increase the transmission efficiency of other packet transmissions such as IEEE1394 and USB.

[0044]

According to the first aspect of the present invention, when the packet length is short, transmission can be started quickly, and the performance is improved without a short transmission interval.

According to the second and third aspects of the present invention, an appropriate transmission start timing according to the packet length can be obtained, and the performance can be improved without a transmission interval regardless of the packet length.

According to the fourth aspect of the present invention, the optimum performance can be set by changing the threshold value according to the DMA speed and the bus performance.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a packet transmission / reception system.

FIG. 2 Packet transmitting / receiving apparatus (network adapter)
FIG.

FIG. 3 is a diagram illustrating a configuration of a packet buffer.

FIG. 4 is a diagram showing a structure of a descriptor which is a component of the packet buffer.

FIG. 5 is a diagram showing a processing flow at the time of transmission.

FIG. 6 is a diagram showing an example of a transmission data threshold value / transmission start threshold value correspondence table register group.

[Explanation of symbols]

 Reference Signs List 1 program ROM 2 main memory 3 CPU 4 network adapter 5 system bus 11 EEPROM 12 boot PROM 13 host interface 14, 17 FIFO RAM 15 transmission FIFO buffer 16 reception FIFO buffer 18 network management unit 19 transmission control unit 20 Ethernet controller 21 reception control unit 22 Clock 23 Encoder 24 Decoder 25 AUI 26 Twisted Pair Transceiver

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference)

Claims (4)

[Claims] 1. In packet communication such as Ethernet (registered trademark), a part of a packet is fetched by a temporary buffer such as a FIFO memory to interpret a protocol. A packet transmission / reception device that transfers the packet to a packet area on an internal main memory and transmits the packet when the packet is from a packet area on the main memory in the apparatus, and starts transmission according to a transmission packet length. A packet transmitting / receiving apparatus comprising a changing means for dynamically changing a timing. 2. The packet transmission / reception device according to claim 1, wherein the changing unit includes a transmission start threshold number of bytes corresponding to a minimum packet data threshold among packet data thresholds to which a packet length applies. A packet transmission / reception device, which starts transmission when the data of (1) is input to the transmission FIFO. 3. The packet transmission / reception device according to claim 1, wherein a transmission start threshold value corresponding to the packet data threshold value is set.
A packet transmitting / receiving apparatus comprising a pair of te numbers as a table. 4. The packet transmitting / receiving apparatus according to claim 3, further comprising: means for registering the table.