JP2002280904A - Analog multiplex transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analog multiplex transmitter where number of pins of a BB-LSI and an RF-LSI and number of wires between them can be reduced. SOLUTION: The analog multiplex transmitter multiplexes a plurality of analog signals in the time base direction, includes a means that multiplexes a plurality of analog signal information items in a time base direction to generate an analog multiplex signal, a means that multiplexes a synchronization signal and an address signal in the time base direction to generate an analog control signal, a means that transmits the analog multiplex signal and the analog control signal, a means that receives the analog multiplex signal and the analog control signal, and a means that reproduces a plurality of analog signal from the received analog multiplex signal and analog control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog multiplex transmission apparatus, and is particularly suitable for transmitting an analog signal whose signal voltage periodically changes in steps. For example, CDMA (Code
A control signal to be given to a variable gain amplifier that controls transmission power in a mobile station of a division multiple access (wireless) communication system.

[0002]

2. Description of the Related Art A conventional example will be described with reference to FIG. FIG.
5 is BB-LSI1, RF-IC2, D / A converter group 1
2. The transmission path 22 is configured. Where BB-LSI
(Base Band Large Scale Integration) means an LSI mainly composed of a digital circuit that performs baseband signal processing in a mobile station of a wireless communication system (for example, a CDMA wireless communication system), and an RF-IC (Radio Frequency Int).
Egration Circuit) means an IC mainly composed of an analog circuit that performs frequency up-conversion, frequency down-conversion, power amplification, low-noise amplification, variable gain amplification, and filtering in a high-frequency band. Although the D / A converter group 12 is mounted on the BB-LSI in FIG. 25, the BB-LSI is full logic,
A D / A converter group is mounted on another LSI called E-LSI or AD-LSI, and the AFE-LSI or AD-LSI
-The LSI may be arranged between the BB-LSI and the RF-IC. In that case, the BB-LSI 1 in FIG.
-LSI or AD-LSI. Further, the RF-IC 2 is replaced with an RF unit when the above functions are implemented by discrete components.

[0003] Signal lines connecting the BB-LSI 1 and the RF-IC 2 include RF signals such as transmission power control, reception AGC (Auto Gain Control), offset correction, and AFC (Auto Frequency Control) in addition to transmission signals and reception signals. There is a control signal called a control signal. Each control signal is generated as a digital control signal having a multi-bit resolution of about 8 bits to 12 bits and a low-speed control cycle of several hundred μS to several tens ms in the BB-LSI. 8 bits
The digital control signal of about 1 to 12 bits is converted from a digital signal to an analog signal by a D / A converter having a desired resolution, and then transmitted through the transmission line 20 in an analog manner. It should be noted that a D / A converter having a resolution of about 8 bits to 12 bits is provided on the transmission line 20 through an LPF (Low Pass F / F).
In some cases, a digital signal is converted into an analog signal using a D / A converter based on a PWM method or a PDM method with an ilter). Japanese Patent Application Laid-Open No. 11-284514 discloses an example of a D / A converter using the PWM method and the PDM method.

As another conventional example, there is Japanese Patent Application Laid-Open No. 2000-244586 as a patent relating to multiplex transmission of analog signals, which is optical transmission mainly for image signals. JP 20
Japanese Patent Application Publication No. 00-244586 is a data transmission system based on amplitude modulation and amplitude multiplexing in which image information is analog-multiplexed in the amplitude direction and transmitted and received.

[0005]

SUMMARY OF THE INVENTION BB-LSI and RF-
RF control signals such as transmission power control, reception AGC, DC offset correction, and AFC exist between ICs, and BB-LSI
In addition, there is a problem that the number of pins of the RF-IC is increased. Particularly in recent years, transmission power control and reception AGC tend to require more than two stages of variable gain amplifiers and more than two control signals for the purpose of high resolution and wide dynamic range. Is increasing. When the number of control signals increases and the number of wirings between the BB-LSI and the RF-IC increases, the wiring pattern on the substrate becomes complicated, and the wiring pattern is easily affected by noise.

JP-A-11-284514 discloses a PW
There is a feature that the M / PDM method simplifies the D / A converter and facilitates analog output from the BB-LSI, but does not reduce the number of signal lines. Japanese Patent Laid-Open No. 2000-244586 multiplexes analog signals in the amplitude direction. Therefore, when each signal has a multi-bit resolution such as an RF control signal, the number of signal lines is reduced according to the performance of the D / A converter. The effect of reduction cannot be expected.

To reduce the number of signal lines, a serial bus transfer method using digital signals can be considered. However, for an RF-IC that handles a very weak analog signal, the influence of digital noise poses a problem in a serial bus transfer method that requires a high-speed clock signal.

[0008]

SUMMARY OF THE INVENTION The present invention is an analog multiplex transmission apparatus for multiplexing a plurality of analog signals in a time axis direction and transmitting / receiving the same. Means for generating an analog control signal by multiplexing a synchronization signal and an address signal in the amplitude direction, means for transmitting the analog multiplex signal and the analog control signal, and means for transmitting the analog multiplex signal and the analog control signal. Means for receiving a signal; and means for reproducing a plurality of analog signals from the received analog multiplexed signal and the analog control signal.

[0009]

FIG. 1 shows a first embodiment of the present invention. FIG. 1 shows BB-LSI1, RF-IC2, transmitter 1.
0, a transmission path 20, and a receiver 30. Here, the BB-LSI means an LSI mainly composed of a digital circuit that performs baseband signal processing in a mobile station of a wireless communication system (for example, a CDMA wireless communication system).
F-IC is frequency up-conversion, frequency down-conversion, power amplification, low-noise amplification,
It means an IC mainly composed of an analog circuit that performs variable gain amplification, filtering, and the like. BB- in FIG.
The LSI 1 has a form in which a D / A converter is mounted.
However, the BB-LSI is set to full logic and AFE (An
alog Front End)-A D / A converter is mounted on another LSI called LSI or AD-LSI, and the AFE-LSI
Alternatively, the AD-LSI may be arranged between the BB-LSI and the RF-IC. In that case, the BB-LSI of FIG.
1 shall be replaced with AFE-LSI or AD-LSI. The RF-IC shown in FIG. 1 is replaced by an RF unit when the above function is implemented by discrete components.

[0010] Between the BB-LSI 1 and the RF-IC 2, in addition to transmission signals and reception signals, transmission power control, reception AGC, DC
There are control signals such as offset correction and AFC, and control information is exchanged at power-on and at communication. For example, transmission power control uses RF to adjust transmission power to an optimum value during communication.
-A control signal for adjusting the gain of the variable gain amplifier in the IC in units of 1 dB every one slot (for example, 666 μs) is required. The reception AGC requires a control signal that is substantially equal to the transmission power control except for the control cycle. D
The C offset correction requires a control signal for measuring a DC offset generated in the RF unit in the BB-LSI when the power is turned on, and correcting the DC offset. The AFC measures the carrier frequency deviation between the base station and the mobile station in the BB-LSI, and requires a control signal for removing the frequency deviation at the time of power-on and at the time of communication.

In FIG. 1, the plurality of control signals are referred to as DATA1 to DATA7. Each control signal is 8 to 12 bits inside the BB-LSI.
Multi-bit resolution of several bits, several hundred μS to several tens ms
Is generated as a digital control signal having a slow control cycle. For example, in FIG. 1, DATA1 is 8 bits and DAT is
A2 is 10 bits, DATA3 is 9 bits, DATA4
8 bits, DATA5 12 bits, DATA6 1
One bit and DATA7 are 10 bits. In addition,
In order to easily explain the features of the present invention, it is assumed that the control timing of each control signal is different and a plurality of control signals do not change at the same time.

BB-L for controlling the RF-IC2
Seven types of control signals DATA1 generated inside SI1,
DATA2, DATA3, DATA4, DATA5, D
ATA6 and DATA7 are input to the transmitter 10 with a 1-bit strobe signal STRB added to digital control data DATA having a resolution of 8 to 12 bits. FIG. 2 shows DATA1, DATA2, DATA3 to DA.
7 shows waveforms of digital control data and a strobe signal of TA7. As shown in the timing chart of FIG. 2, the strobe signal is "1" at a predetermined pulse width at a data change point.
, The transmitter 10 recognizes that the digital control data has changed.

Next, the transmitter 10 will be described in detail with reference to FIG. The transmitter 10 includes an 8-bit D / A converter 101, 10
bitD / A converter 102, 9-bit D / A converter 10
3, 8-bit D / A converter 104, 12-bit D / A converter 105, 11-bit D / A converter 106, 10-bit
D / A converter 107, analog multiplexer 108,
LPF (Low Pass Filter) 109, control circuit 10a,
It comprises a 3-bit D / A converter 10b and an LPF 10c. Although the D / A converters 101 to 107 have different resolutions, the maximum value Vmax and the minimum value Vm of the output voltage are different.
in shall be equal to each other. In the transmitter 10, BB−
Digital control data DATA1 generated inside the LSI
7 and strobe signals STRB1 to STRB7, respectively, and convert digital control data into analog control signals at the timing of strobe signals using D / A converters 101 to 107. The analog multiplexer 108 has a function of selecting and outputting one of the seven analog control signals by the 3-bit select signal SEL of the control circuit 10a.

FIG. 4 shows the configuration of the control circuit 10a. The control circuit 10a includes a binary encoder 10a1, a synchronization timing generator 10a2, and a selector circuit 10a3. The binary encoder 10a1 has a 7-bit input,
It is a 3-bit output binary encoder.

Table 1 shows a truth table of input versus output in the binary encoder 10a1.

[0016]

[Table 1] When any one of the inputs A1 to A7 becomes "1", the binary encoder 10a1 outputs a 3-bit output SEL [2: 0] according to the bit position that has become "1" as shown in Table 1. I do.

FIG. 5 shows the configuration of the synchronization timing generator 10a2. Synchronous timing generator 10a2 is 7 bit O
It comprises an R circuit 10a21 and a timer 10a22. The seven strobe signals STRB1 to STRB7 are 7 bit O
When the signal is input to the R circuit 10a21 and one of the STRBs 1 to 7 becomes "1", the 7-bit OR circuit 10a21
Is "1". The timer 10a22 has a monostable multivibrator function. When "1" is input to the input, the output is held at "1" for a predetermined time T1 [S].
The circuit returns to "0" after one hour has passed.

Table 2 shows a truth table of input versus output in the synchronous timing generator 10a2.

[0019]

[Table 2] The synchronous timing generator 10a2 is a circuit in which when any one of the inputs B1 to B7 becomes "1", the output T1 becomes "1" for a predetermined time T1 [s]. Returning to the description of the control circuit 10a in FIG.
Becomes "1", the T1 output from the synchronization timing generator 10a2 becomes "1". When the output of T1 of the synchronization timing generator 10a2 becomes "1", the selector 10a3 selects the synchronization code ("000" in FIG. 4). Since the T1 output of the synchronous timing generator 10a2 becomes "1" for a predetermined T1 [s] time, the output CTRL of the control circuit 10a becomes "000" for the T1 [s] time, and thereafter the output of the binary encoder 10a1. S
EL will be output.

In FIG. 3, the output CTR of the control circuit 10a
L is input to the 3-bit D / A converter 10b,
Is converted from a digital signal to an analog signal.

FIG. 6 shows seven strobe signals STRB1 to STRB1.
The relationship between the STRB 7 and the output waveform of the 3-bit D / A converter 10b is shown. As can be seen from FIG. 6, when the strobe signal becomes "1", the output of the 3-bit D / A converter 10b becomes "0" level when the range between Vmax and Vmin is set to 8 values for a predetermined T1 [s] time. After that, a voltage corresponding to the binary code corresponding to the position of the strobe signal is output. For example, when STRB3 becomes "1", 3b
The output of the itD / A converter 10b goes to the "0" level for a predetermined time T1 [s], and then continues to output the "3" level voltage until the next strobe signal goes to "1". The same applies to other strobe signals.

FIG. 7 shows the relationship between the output waveform of the D / A converter 10b and the output waveform of the analog multiplexer 108. From FIG. 7, it can be seen that the start time at which the D / A converter 10b outputs the “0” level serving as the synchronization code is equal to the time at which the output of the analog multiplexer 108 changes. The output of the analog multiplexer 108 is output from the D / A converter 10 by using the output signal SEL of the control circuit 10a.
One of the signals 1 to 107 is a selected signal, and switches at the same time as the start time of the synchronization code. As can be seen from the lower part of FIG. 7, the output of the analog multiplexer 108 is a signal obtained by multiplexing signals having different resolutions in the time axis direction. For example, in FIG. 7, when the D / A converter 10b outputs the "3" level of the address next to the "0" level which is the synchronization code, the output of the analog multiplexer 108 outputs the 9-bit digital control data of DATA3. Since the level becomes the D / A converted level, the “238” level is output when the range between Vmax and Vmin is set to 512 values. Next, when the D / A converter 10b outputs the address “5” level next to the synchronization code “0” level, the output of the analog multiplexer 108 converts the 12-bit digital control data of DATA5 to D / A.
Since the converted level is obtained, the range between Vmax and Vmin is set to 40
The “1609” level when 96 values are output.

Returning to the description of FIG. 3, the output of the analog multiplexer 108 has a waveform from which harmonic components have been removed by the LPF 109, and is output from the transmitter 10 to the outside as an analog multiplex signal mux. Also, the D / A converter 10
The output of b also has a waveform from which the harmonic components have been removed by the LPF 10c, and the analog control signal c from the transmitter 10 to the outside.
Output as trl.

Next, another configuration of the transmitter 10 of FIG. 3 will be described. Although the transmitter 10 of FIG. 3 needs to prepare D / A converters for the number of signals, the number of D / A converters can be significantly reduced by using a digital multiplexer.

FIG. 8 shows a configuration of a transmitter in which the number of D / A converters is reduced. The transmitter 10 of FIG.
Means that the D / A converters 101 to 107 in FIG.
To 10j, the analog multiplexer 108 is replaced by the digital multiplexer 10k, and the D / A converter 10L
Has been added. The D / A converter 10L is a D / A converter having a resolution equal to or greater than the maximum number of bits of the digital control data DATA1 to DATA7. In FIG. 8, 12 bitD /
A converter. In FIG. 8, digital control data DA
TA1 to TA7 are held in the registers 10d to 10j at the timing of the strobe signals STRB1 to STRB7. In addition,
Registers 10d to 10j store digital control data DAT.
It is assumed that the number of bits matches A1 to A7. The digital multiplexer 10k controls the control circuit 10a from among the digital control data held in the registers 10d to 10j.
Is selected by the 3-bit select signal SEL of
It has a function to output after adjusting the number of it.

FIG. 9 shows the configuration of the digital multiplexer 10k. Digital multiplexer 10k is 12 bits
7 inputs, 12 bits 1 output. Registers 10d-1
0j, the digital control data DATA1.
DATA7 has a value of 8 bits to 12 bits. However, since the internal input of the digital multiplexer 10k is 12 bits, the digital control data of less than 12 bits is inserted into the lower bit by inserting “0” into the lower bit.
Perform t adjustment. Only one of the seven bit-adjusted 12-bit input signals is selected by the select signal SEL and becomes an output signal.

Returning to the description of FIG. 8, the output of the digital multiplexer 10k is input to the 12-bit D / A converter 10L and converted from a digital signal multiplexed in the time axis direction to an analog signal. The output of the D / A converter 10L of FIG. 8 has the same waveform as the output of the analog multiplexer 108 of FIG. The output of the D / A converter 10L is the LPF 10
9 is a waveform from which harmonic components have been removed.
0 is output to the outside as an analog multiplex signal mux. The output of the D / A converter 10b also has a waveform from which the harmonic components have been removed by the LPF 10c, and is output from the transmitter 10 to the outside as an analog control signal ctrl.

Next, the receiver 30 in the RF-IC will be described with reference to FIG. The receiver 30 is a waveform shaper 30
1, analog demultiplexer 302, waveform shaper 30
It comprises a 3, 3 bit A / D converter 304, a sample timing generator 305, and sample and hold circuits 306 to 30c. The analog multiplex signal mux transmitted from the transmitter is input to the receiver 30 along with the analog control signal ctrl via the transmission path. The analog multiplex control signal mux and the control signal ctrl are input to the waveform shaping circuits 302 and 303, respectively. Waveform shaping circuit 30
Reference numerals 1 and 303 have a function of restoring an analog signal from which harmonic components have been removed by the LPF of the transmitter to the original frequency characteristics. The output waveform of the waveform shaping circuit 301 is equal to the lower waveform of FIG. 7, and the output waveform of the waveform shaping circuit 303 is equal to the upper waveform of FIG. The output of the waveform shaping circuit 301 is input to the input terminal IN of the analog demultiplexer 302, and output terminals OUT1 to OUT7 are output by a 3-bit select signal SEL.
, A waveform equal to the input signal is output, and the O signal having a number equal to the 3-bit decimal value of the select signal SEL is output.
UT is selected. For example, if SEL [2: 0] is binary “0”
If it is "11", that is, "3" as a decimal value, it is output from OUT3.3-bit select signal SEL
Converts the waveform-shaped analog control signal ctrl to A
3D from the 8-level analog signal by the / D converter 304
It is converted into a digital signal of t. The output of the A / D converter 304 is also input to the sample timing generator 305.

FIG. 11 shows a sample timing generator 305.
Is shown. The sample timing generator 305 includes a binary decoder 3051, a 7-bit AND circuit 3052,
It is composed of a delay unit 3053. Binary decoder 3
Reference numeral 051 denotes a circuit in which any one bit of an 8-bit output becomes “1” in response to a 3-bit input.

Table 3 shows a truth table of input versus output of the binary decoder 3051.

[0031]

[Table 3] As can be seen from Table 3, for example, when the input IN is a synchronization code of "000", "1" is output to C0, and when the input IN is "011", C3 becomes "1".

Referring to FIG. 11, the binary decoder 3051
Output C0 to the delay device 3053, C1 to C7 are 7 bits
The signal is input to the AND circuit 3052. Binary decoder 305 delayed by T3 [s] time by delay unit 3053
1 and the outputs C1 to C1 of the binary decoder 3051.
The AND output of C7 becomes the output of the sample timing generator 305.

FIG. 12 shows a timing chart of the sample timing generator. As can be seen from FIG.
Becomes "0", a sample timing signal having a width of T1 [s] is generated at the corresponding Y output with a delay time of T3 [s]. For example, if a decoding result of “3” is obtained following a synchronization code of “0”, Y3 has a delay time of T3 [s] from the time when the input X becomes “0”.
, A timing signal having a width of T1 [s] is generated.

Returning to the description of FIG. 10, the outputs of OUT1 to OUT7 of the analog demultiplexer 302 are input to the sample-and-hold data input IN. Here, the sample and hold circuits 306 to 30c operate in the sample mode when the sample / hold switching S / H is "1".
When it is “0”, it is regarded as a hold mold. The sample and hold circuits 306 to 30c are connected to the sample timing generator 30.
When the sample timing signal output from 5 is "1", the output signal from the analog demultiplexer is sampled, and while the sample timing signal is "0", the sampled value is held and a constant voltage is continuously output.

FIG. 13 shows the relationship between the output waveforms of the A / D converter 304, the sample timing generator 305, and the receiver 30. The sample timing signals Y1 to Y7 obtained from the output X of the A / D converter 304 change the outputs of the sample hold circuits 306 to 30c at the timing shown in FIG. For example, if the A / D converter output X is followed by “3” after the synchronization code “0”, a sample timing signal of T1 [s] width is output from the Y3 output of the corresponding sample timing generator 305 with a delay time of T3. Generated. Output Y3 of sample timing generator 305
Is input to the S / H of the sample and hold circuit 308, samples the OUT3 output of the analog demultiplexer 302 when the output of the sample timing signal Y3 is "1", updates the output data3 of the sample and hold circuit 308, and The updated value is held at the same time when the Y3 output becomes “0”. As long as the sample timing signal Y3 is "0", the sample hold circuit 3
The output data3 of 08 continuously outputs a constant voltage. Similarly, if the output X of the A / D converter is followed by “5” after the synchronization code “0”, the output of the corresponding sample timing generator 305 from the output of Y5 to T1 with a delay time of T3 [s]
A [s] wide sample timing signal is generated. The output Y5 of the sample timing generator 305 is input to the S / H of the sample hold circuit 30a, and the output OUT5 of the analog demultiplexer 302 is sampled when the output of the sample timing signal Y5 is "1", and the output of the sample hold circuit 30a is output. Data5 is updated, and the updated value is held at the same time when the output of the sample timing signal Y5 becomes "0". The sample timing signal Y5 is "0"
Output data of the sample-and-hold circuit 30a as long as
5 keeps outputting a constant voltage.

As described above, the control signals data1 to data7 used in the RF-IC are analog multiplexed signals m.
It can be seen that the signal is reproduced faithfully by the receiver 30 using the ux and the analog control signal ctrl.

In this embodiment, the control signals are data1 to d
Although the description has been made with reference to seven types of signal lines of ata7, the number of signal lines is seven.
Not limited to w, any value can be taken by changing the resolution of the D / A converter 10b.

In the present embodiment, the control timing of each control signal is different for the sake of simplicity, and a plurality of control signals are not changed at the same time. It becomes possible by connecting two stages to form a double buffer configuration and setting rules for transmission and reception. For example, DATA1 and DA
If you want to change TA2 at the same time,
A1 and DATA2 are transmitted in this order.
A1 is sampled and held at the preceding stage of the sample and hold circuit, and when DATA2 is received, DATA1 and DATA2 are simultaneously changed by providing a rule for sampling and holding the output of the sample and hold circuit at the preceding stage of DATA1 at the subsequent sample and hold circuit. It becomes possible.

Although the present embodiment has been described by taking a mobile station of a wireless communication system as an example, the present invention can be easily applied to a base station of a wireless communication system or an image signal transmission device.

FIG. 14 shows a second embodiment of the present invention. Figure 1
Reference numeral 4 is a device in which the transmitter 10, the transmission path 20, and the receiver 30 in FIG. 1 are replaced with a transmitter 11, a transmission path 21, and a receiver 31. The output of the transmitter 10 of FIG. 1 is an analog multiplex signal mux and an analog control signal ctrl, whereas the transmitter 11 of FIG. 14 has only an analog multiplex signal mux. While the transmission path 20 in FIG. 1 is transmitted by two signal lines, the transmission path 21 in FIG. 14 is transmission by one signal line. The input signal of the receiver 30 of FIG. 1 is an analog multiplex signal mux and an analog control signal ctr.
In contrast, the receiver 31 of FIG. 14 has only the analog multiplex signal mux. The other parts are the same as those in FIG.

The transmitter 11 will be described in detail with reference to FIG. The transmitter 11 is an 8-bit D / A converter 111, 10b
itD / A converter 112, 9-bit D / A converter 113,
8-bit D / A converter 114, 12-bit D / A converter 1
15, 11-bit D / A converter 116, 10-bit D / A
Converter 117, analog multiplexer 118, LPF
119, control circuit 11a, 3-bit D / A converter 11b
It consists of. The D / A converters 111 to 117
And 11b have different resolutions, but assume that the maximum value Vmax and the minimum value Vmin of the output voltage are the same. In the transmitter 11, digital control data DATA1 to DATA7 generated inside the BB-LSI and strobe signals STRB1 to STRB1 are output.
7 are input, and the digital signals are converted into analog signals at the timing of the strobe signals using the D / A converters 111 to 117. DATA1, DATA2, DAT
The waveforms of the digital control data A3 to DATA7 and the strobe signal are the same as those in FIG. Analog multiplexer 11
Reference numeral 8 denotes 3bi of the control circuit 11a from among a total of eight analog signals of the D / A converters 111 to 117 and the D / A converter 11b.
It has a function of selecting and outputting one by the select signal SEL of t.

The configuration of the control circuit 11a will be described in detail with reference to FIG. The control circuit 11a is a binary encoder 1
1a1, a synchronous timing generator 11a2, and selector circuits 11a3 and 11a4. Control circuit 11a
Has a configuration in which one selector circuit is added to the control circuit 10a of FIG. The binary encoder 11a1 is shown in FIG.
10a1 and is equal to the truth value in Table 1.

FIG. 17 shows the configuration of the synchronization timing generator 11a2. Synchronous timing generator 11a2 has 7 bits
It is composed of an OR circuit 11a21 and timers 11a22 and 11a23. Seven strobe signals STRB1-7
Is input to the OR circuit 11a21, and when any of the STRBs 1 to 7 becomes "1", the 7-bit OR circuit 11a
21 becomes "1". Timers 11a22 and 11a
Reference numeral 23 has a monostable multivibrator function. When "1" is input to the input, if the timer 11a22, the output is held at "1" for a predetermined time T1 [S]. This is a circuit for returning to “0”.
In the case of a23, the output is held at "1" for a predetermined time T2 [S], and returns to "0" after the elapse of the time T2.

Returning to the description of the control circuit 11a of FIG. 16, when any of the strobe signals STRB1 to STRB7 becomes "1", the synchronous timing generator 11a2 outputs "1" from the output of T1 for a predetermined time T1 [s]. "1" for a predetermined time T2 [s] from the output of T2. When the T1 output of the synchronous timing generator 11a2 becomes "1", the selector 1
1a3 selects a synchronization code ("000" in FIG. 16), and outputs the output SEL [2: 0] of the binary encoder 11a1 when the T1 output becomes "0". When the T2 output of the synchronization timing generator 11a2 becomes "1", the selector 11a4 selects "000", and when the T2 output becomes "0", the output SE of the binary encoder 11a1 becomes "0".
L [2: 0] is output.

In FIG. 15, the output CT of the control circuit 11a is
RL is input to the 3-bit D / A converter 11b,
The digital signal of t is converted into an analog signal and input to the analog multiplexer 118. The relationship between the strobe signals STRB1 to STRB7 and the output waveform of the 3-bit D / A converter 11b is the same as in FIG.

FIG. 18 shows the relationship between the SEL output waveform of the control circuit 11a and the output waveform of the analog multiplexer 118. The SEL signal becomes "0" for the time T2 [s], and thereafter becomes the value of any one of the digital control data DATA1 to DATA7. When the SEL signal is "0", the output of the analog multiplexer 118 is at the "0" level when the first T1 [s] time has eight values in the range between Vmax and Vmin, and the remaining (T2-T1) [ [s] Time becomes a level indicating an octal address. SEL after T2 [s] time
Until the signal becomes "0", it becomes an analog signal obtained by D / A conversion of the value of the digital control data indicated by the address.
For example, in FIG. 18, the output of the analog multiplexer 118 becomes “0” level for the time T1 [s], and the remaining (T2
-T1) [s] time indicates an address of "3" level. Therefore, the time from the time T2 [s] until the next time the SEL signal becomes “0” is 9-bit D / A of DATA3.
The output of the converter is shown in FIG. Subsequently, the output of the analog multiplexer 118 becomes the “0” level for the time T1 [s], and the remaining (T2−T1) [s] time indicates the address of the “5” level. Therefore, after T2 [s] time, S
The time until the EL signal becomes “0” is 12 of DATA5.
It becomes an output of the bit D / A converter, and it can be seen that it is at the “2340” level.

As described above, the analog multiplexer 11
It can be seen from the output 8 that signals having different resolutions are multiplexed in the time axis direction. Since the “0” level when the range between Vmax and Vmin is set to eight values is assigned to the synchronization code, the digital control data DATA1 to DATA7 is Vma.
Use of the lower 1/8 range of x and Vmin is prohibited. For example,
The range of 0 to 63 cannot be used for DATA3, and the range of 0 to 255 cannot be used for DATA5.

Returning to the description of FIG. 15, the output of the analog multiplexer 118 becomes a waveform from which harmonic components have been removed by the LPF 119, and is output from the transmitter 11 to the outside as an analog multiplex signal mux.

Next, another configuration of the transmitter 11 shown in FIG. 15 will be described. The transmitter 10 shown in FIG.
Although the A converter is prepared, the number of D / A converters can be greatly reduced by using a digital multiplexer.

FIG. 19 shows a configuration of a transmitter in which the number of D / A converters is reduced. In the transmitter 11 of FIG. 19, the D / A converters 111 to 117 of FIG. 15 are replaced by registers 11b to 11j, the analog multiplexer 118 is replaced by a digital multiplexer 11k, and a D / A converter 11L is added. The D / A converter 11L
Is a D / A converter having a resolution not less than the maximum number of bits of the digital control data DATA1 to DATA7. In FIG. 19, 12
It is a bit D / A converter. In FIG. 19, digital control data DATA1 to DATA7 are strobe signals STRB1 to STRB1.
At timing 7, the data is held in the registers 11d to 11j. The registers 11d to 11j have the number of bits corresponding to the digital control data DATA1 to DATA7. The digital multiplexer 11k has a function of selecting one from a total of eight types of digital control data and a control circuit 11a output CTRL by a 3-bit select signal SEL of the control circuit 11a, adjusting the number of bits, and outputting the result.

FIG. 20 shows the configuration of the digital multiplexer 11k. Digital multiplexer 11k is 12bi
t8 input, 12 bit1 output. Register 11d ~
11j digital control data DATA1
ＤＡDATA7 and CTRL have values of 3 bits to 12 bits. Since the internal input of the digital multiplexer 11k is 12 bits, the digital control data of the number of bits less than 12 bits is inserted by inserting “0” into the lower bit to b
Perform it adjustment. Only one of the eight 12-bit input signals whose bit has been adjusted is selected by the select signal SEL and becomes an output signal.

Returning to the description of FIG. 19, the output of the digital multiplexer 11k is input to the 12-bit D / A converter 11L, and the digital control data multiplexed on the time axis is converted into an analog control signal. The output of the D / A converter of FIG. 19 has the same waveform as the output of the analog multiplexer 118 of FIG. The output of the D / A converter 11L is LP
A waveform from which higher harmonic components have been removed by F119 is output from the transmitter 10 to the outside as an analog multiplexed signal.

Next, the receiver 31 in the RF-IC will be described with reference to FIG. The receiver 31 is a waveform shaper 31
1, analog demultiplexer 312, 3-bit A / D
It comprises a converter 314, a sample timing generator 315, and sample and hold circuits 316 to 31c. The analog multiplex signal mux transmitted from the transmitter is input to the receiver 31 via the transmission path. Analog multiplex signal mu
x is input to the waveform shaping circuit 311 and has a function of restoring the analog signal from which the harmonic components have been removed by the LPF of the transmitter to the original frequency characteristics. The output of the waveform shaping circuit 311 is equal to the waveform shown in the lower part of FIG. Waveform shaping circuit 311
Is the input terminal I of the analog demultiplexer 312.
N, a waveform equal to the input signal is output from any of the output terminals OUT1 to OUT7 by the 3-bit select signal SEL, and OUT having a number equal to the 3-bit decimal value of the select signal SEL is selected. For example, S
If EL [2: 0] is "011" in binary value, that is, "3" in decimal value, it is output from OUT3. 3
The bit select signal SEL is obtained by converting the waveform-shaped analog multiplex signal mux to the waveform shown in the lower part of FIG. 18 and converting the 8-level analog signal into a 3-bit digital signal by the A / D converter 314. is there. A / D
The output of the converter 314 is the sample timing generator 315
Is also entered.

FIG. 22 shows a sample timing generator 315.
Is shown. The sample timing generator 315 includes a binary decoder 3151, a 7-bit AND circuit 3152,
Delay devices 3153, 3154, 3-bit register 315
It is composed of 5, 7-bit register 3156. The binary decoder 3151 receives 8 bits for a 3-bit input.
This is a circuit in which any one bit of the output of t becomes “1”. The truth table for input versus output of binary decoder 3151 is equal to Table 3. As can be seen from Table 3, for example, input IN
Is "000", "1" is output to C0, and if the input IN is "011", C3 becomes "1".

In FIG. 22, binary decoder 3151
Is output to delay units 3153 and 3154, and outputs C1 to C7 of binary decoder 3151 are input to a 7-bit register. Outputs C1 to C of binary decoder 3151
7 is latched at the timing of the output C0 of the binary decoder 3151 delayed by the time T3 [s] by the delay unit 3154. The outputs C0 and 7bi of the binary decoder 3151 delayed by the time T4 [s] by the delay unit 3153
The AND outputs of the outputs Q1 to Q7 of the t register 3156 are output as the sample timing generator 315.

FIG. 23 shows a timing chart of the sample timing generator. First, the value of ADR changes with a delay time of T3 [s] from the time when the input X becomes “0”. For example, if the address value following the synchronization code of “0” is “3”, the ADR output is “3”. Next, a sample timing signal having a width of T1 [s] is generated at the corresponding output of Y with a delay time of T4 [s] from the time when the input X becomes "0". For example, if a decoding result of “3” is obtained following a synchronization code of “0”,
A timing signal having a width of T1 [s] is generated at the output of Y3 with a delay time of T4 [s] from the time when the input X becomes "0".

Returning to the description of FIG. 21, the outputs of OUT1 to OUT7 of the analog demultiplexer 312 are input to the sample-and-hold data input IN. Here, the sample hold circuits 316 to 31c are in the sample mode when the sample / hold switching S / H is "1",
When it is “0”, it is regarded as a hold mold. ADR, which is the output signal of the sample timing generator 315, is input to the select signal input SEL of the analog demultiplexer 312, and the output from OUT1 to OUT7 is selected. When the sample timing signal output from the sample timing generator 315 is "1", the output signal from the analog demultiplexer is sampled. During the period when the sample timing signal is "0", the sampled value is held and a constant voltage is output. Keep doing.

FIG. 24 shows the relationship among the output waveforms of the A / D converter 314, the sample timing generator 315, and the receiver 31. The outputs of the sample hold circuits 316 to 31c change at the timing shown in FIG. 24 according to the sample timing signals Y1 to Y7 obtained from the output X of the A / D converter 314. For example, if the A / D converter output X is followed by "3" after the synchronization code "0", the corresponding sample timing generator 31 has a delay time of T4 [s].
5, a sample timing signal having a width of T1 [s] is generated from the Y3 output. The output Y3 of the sample timing generator 315 is input to the S / H of the sample hold circuit 318, and the output OUT3 of the analog demultiplexer 312 is sampled when the output of the sample timing signal Y3 is "1". Output data
3 is updated to "0" and the updated value is held at the same time. As long as the sample timing signal is "0", the output data3 of the sample hold circuit 318 keeps outputting a constant voltage. Similarly, if the output X of the A / D converter is followed by "5" after the synchronization code "0", a sample timing signal having a width of T1 [s] is output from the Y5 output of the corresponding sample timing generator 315 with a delay time of T4. Is generated. Output Y5 of sample timing generator 305
Is input to the S / H of the sample and hold circuit 31a, samples the OUT5 output of the analog demultiplexer 312 when the sample timing signal Y5 output is "1", updates the output data5 of the sample and hold circuit 31a, and updates the sample timing signal. The updated value is held at the same time when the Y5 output becomes “0”. As long as the sample timing signal Y5 is "0", the sample hold circuit 3
The output data5 of 1a keeps outputting a constant voltage.

According to the above description, the control signals data1 to data7 used in the RF-IC are analog multiplexed signals m.
It can be seen that the signal is reproduced faithfully by the receiver 30 using ux.

In the present embodiment, the control timing of each control signal is different for the sake of simplicity of description, and a plurality of control signals are not changed at the same time. It becomes possible by connecting two stages to form a double buffer configuration and setting rules for transmission and reception. For example, DATA1 and DA
If you want to change TA2 at the same time,
A1 and DATA2 are transmitted in this order.
A1 is sampled and held in the preceding stage of the sample and hold circuit, and when DATA2 is received, a rule is set to sample and hold the output of the sample and hold circuit in the preceding stage of DATA1 in the subsequent sample and hold circuit, thereby simultaneously changing DATA1 and DATA2. It becomes possible.

Although the present embodiment has been described by taking a base station of a wireless communication system as an example, the present invention can be easily applied to a base station of a wireless communication system, an image signal transmission device, or the like.

[0062]

According to the present invention, it is possible to transmit information of a plurality of analog signal lines with a small number of one or two signal lines. Further, there is no problem of the influence of digital noise as in the serial bus transfer method.

[Brief description of the drawings]

FIG. 1 is a BB employing an analog multiplex transmission apparatus of the present invention.
-The figure which showed the connection of LSI and RF-IC.

FIG. 2 is a timing chart showing a relationship between digital control data input to a transmitter and a strobe signal.

FIG. 3 is a diagram showing a configuration of a transmitter equipped with an analog multiplexer.

FIG. 4 is a diagram showing a configuration of a control circuit.

FIG. 5 is a diagram showing a configuration of a synchronization timing generator in detail.

FIG. 6 is a timing chart showing a relationship between a strobe signal and a D / A converter output signal.

FIG. 7 is a timing chart showing a relationship between a D / A converter output signal and an analog multiplexer output signal.

FIG. 8 is a diagram showing a configuration of a transmitter equipped with a digital multiplexer.

FIG. 9 is a diagram showing a digital multiplexer in detail.

FIG. 10 is a diagram showing a configuration of a receiver.

FIG. 11 is a diagram showing a configuration of a sample timing generator in detail.

FIG. 12 is a timing chart showing a relationship between an A / D converter output signal X and sample timing signals Y1 to Y7.

FIG. 13 shows an A / D converter output signal X, sample timing signals Y1 to Y7, and receiver outputs data1 to data7.
6 is a timing chart showing the relationship of FIG.

FIG. 14 is a diagram B showing the analog multiplex transmission apparatus of the present invention.
FIG. 4 is a diagram showing connection between a B-LSI and an RF-IC.

FIG. 15 is a diagram showing a configuration of a transmitter equipped with an analog multiplexer.

FIG. 16 is a diagram showing a configuration of a control circuit.

FIG. 17 is a diagram showing the configuration of a synchronization timing generator in detail.

FIG. 18 is a timing chart showing a relationship between a D / A converter output signal and an analog multiplexer output signal.

FIG. 19 is a diagram showing a configuration of a transmitter equipped with a digital multiplexer.

FIG. 20 is a diagram showing a digital multiplexer in detail.

FIG. 21 is a diagram showing a configuration of a receiver.

FIG. 22 is a diagram showing a configuration of a sample timing generator in detail.

FIG. 23 is a timing chart showing a relationship between an A / D converter output signal X and sample timing signals Y1 to Y7.

FIG. 24 shows an A / D converter output signal X, sample timing signals Y1 to Y7, and receiver outputs data1 to data7.
6 is a timing chart showing the relationship of FIG.

FIG. 25 is a diagram showing a configuration of a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... BB-LSI, 2 ... RF-IC, 10 ... Transmitter, 20 ... Transmission line, 30 ... Receiver, 101-107 ...
・ D / A converter, 108 ・ ・ ・ analog multiplexer, 1
09 LPF, 10a control circuit, 10b D / A converter, 10c LPF, 10a1 binary encoder, 10a2 synchronous timing generator, 10a3 selector Circuit, 10a21... 7-bit OR circuit, 10a
22: timer, 10d to 10j: register, 10k ...
・ Digital multiplexer, 10L ・ ・ ・ D / A converter, 3
01 ... waveform shaping circuit, 302 ... analog demultiplexer, 303 ... waveform shaping circuit, 304 ... A / D converter, 305 ... sample timing generator, 306-3
0c: sample and hold circuit, 3051: decoder circuit, 3052: AND circuit, 3053: delay unit, 11
... Transmitter, 21 ... Transmission path, 31 ... Receiver, 111-
117 ... D / A converter, 118 ... analog multiplexer, 119 ... LPF, 11a ... control circuit, 11b ...
D / A converter, 11a1 ... binary encoder, 11
a2: Synchronous timing generator, 11a3: Selector circuit, 11a4: Selector circuit, 11a21 ... 7 bits
OR circuit, 11a22 ... timer, 11a23 ... timer, 11d to 11j ... register, 11k ... digital multiplexer, 11L ... D / A converter, 311 ... waveform shaping circuit, 312 ..Analog demultiplexers, 31
4 ... A / D converter, 315 ... Sample timing generator, 316-31c ... Sample hold circuit, 315
1 Decoder circuit, 3152 AND circuit, 3153
... Delay device, 3154 ... Delay device, 3155 ... 3 bits
Register, 3156 ... 7 bit register, 12 ... D /
A converter, 22 ... transmission line.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J022 AA01 AB01 BA06 BA10 CA07 CA10 CD03 CE08 CF08 CG01 5K022 BB01 BB22 EE01 FF00 5K028 AA17 BB04 DD02 FF09 KK01 KK03 MM16 NN31 SS01 SS03 SS04 SS11 SS14 SS28

Claims (5)

[Claims] 1. An analog multiplex transmission device having a transmitter and a receiver, wherein the transmitter multiplexes a D / A converter and a plurality of analog signals output from the D / A converter. An analog multiplexer that outputs an analog multiplexed signal, and a control circuit that controls the analog multiplexer and outputs a control signal obtained by multiplexing a synchronization signal and an address signal, wherein the receiver receives the control signal. A / D converter, an analog demultiplexer to which the analog multiplexed signal is input, a sample timing generator that generates a sample timing signal according to an output of the A / D converter, and an output of the analog demultiplexer Connected to an output of the sample timing generator, and in response to the sample timing signal, the analog demultiplexer. An analog multiplex transmission apparatus comprising: a sample-hold circuit that samples or holds an output of a multiplexer. 2. The analog multiplex transmission apparatus according to claim 2, wherein said transmitter has a high-frequency cutoff filter for removing harmonic components of said analog multiplex signal and said analog control signal, and said receiver. An analog multiplex transmission device comprising a waveform shaping circuit for restoring a harmonic component of an analog multiplex signal from which the high-frequency component has been removed and an analog control signal. 3. The analog multiplex transmission apparatus according to claim 1, wherein said sample and hold circuit of said receiver has a two-stage configuration, and reproduces information of a plurality of analog signals. . 4. The analog multiplex transmission apparatus according to claim 1, wherein the analog multiplexer of the transmitter multiplexes the analog multiplex signal and the control signal and transmits the multiplexed signal. Multiplex transmission equipment. 5. An analog multiplex transmission device, comprising: a transmitter and a receiver, wherein the transmitter comprises: a digital multiplexer for outputting a digital multiplex signal obtained by multiplexing a plurality of digital signals; A D / A converter connected to an output of the digital multiplexer, and a control circuit that controls the digital multiplexer and outputs a control signal in which a synchronization signal and an address signal are multiplexed; An A / D converter to which the control signal is input; an analog demultiplexer to which an output signal of the D / A converter is input; and a sample for generating a sample timing signal according to an output of the A / D converter. A timing generator, connected to an output of the analog demultiplexer and an output of the sample timing generator, Depending on the sample timing signal, the analog multiplex transmission apparatus characterized by having a sample-and-hold circuit which samples or holds the output of the analog demultiplexer.