JP2002271730A - Recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a recorder that can excellently reproduce a recorded signal. SOLUTION: The recorder is configured with a signal processing means that periodically processes an input image signal for a period of n-frames (n is an integer of 2 or over), an attached information generating means that generates attached information changed periodically for the n-frame period of the image signal, a recording means that uses a rotary head to generate many tracks on a tape recording medium and records an image signal outputted from the signal processing means and the attached information generated by the attached information generating means on m(m is an integer of 1 or over) tracks per one frame, and a control means that controls the recording means so as to terminate the recording on a final track in the n×m tracks in which the image signal of the n frames are cyclicly recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a recording apparatus, and more particularly to a process at the end of recording image signals.

[0002]

2. Description of the Related Art Conventionally, a digital VTR for recording and reproducing an image signal as a digital signal on a magnetic tape has been known. In recent years, the HD Digital VCR Council has proposed the DV format as the format of a consumer digital VTR.

[0003] In the DV format, an NTSC image signal is recorded on ten tracks per frame.
The specification (hereinafter, SD format) and the SD high compression specification (hereinafter, SDL format) for recording on five tracks per frame are defined.

In the SD format, various additional information called system data is recorded in addition to an image signal. The system data includes pack information composed of 5-byte data, ID information included in the ID portion of each sync block, and the like.

[0005] The pack information includes a recording date and time, a time code indicating a frame, and information such as "video source", "audio source",
"Video source control" indicating the type of image (moving image / still image) is available.

[0006] The ID information includes a track pair number in which the beginning of ten tracks on which one frame of image signal is recorded is set to 0, and the number increases from 0 to 4 every three tracks, or one frame in the SD format. 1 indicating the frequency (f1 or f2) of the pilot signal recorded on the first track of the ten tracks on which the image signal is recorded
There is bit pilot frame information.

The recording position of the system data is also specified by a format. For example, a video source control pack is recorded in an area of VAUX on a track. 19 sync blocks and 156 sync blocks are alternately recorded.

Further, additional information is also recorded in the SDL format, and the content of the time code changes every five tracks in which one frame of image signal is recorded.
In the SDL format, the track pair number circulates at a value of 0 to 4 every 10 tracks, that is, every two frames in the SDL format. Also, the values of 1 and 0 are repeated every 10 tracks for the pilot frame.

[0009]

As described above, when recording is performed in the SDL format, if the recording is completed when one frame of data is recorded, the system data circulating in units of two frames in the SDL format may be interrupted. May end the recording.

Therefore, when that part is reproduced, it is not possible to accurately obtain system data circulating in units of two frames, and the reproduced image and sound may be disturbed.

An object of the present invention is to solve the above-mentioned problems.

Another object of the present invention is to enable recorded signals to be satisfactorily reproduced.

[0013]

In order to achieve the above object, the present invention provides an input image signal having n frames (n is 2 frames).
Signal processing means for processing periodically in the above integer) period;
Additional information generating means for generating additional information that periodically changes during n frame periods of the image signal, and a number of tracks formed on a recording medium on tape using a rotary head, and output from the signal processing means. Recording means for recording the image signal and the additional information generated by the additional information generating means on m tracks (m is an integer of 1 or more) per frame; and control means for controlling the recording means so as to end the recording at the last track among the n × m tracks on which the image signals of n frames are cyclically recorded.

[0014]

Embodiments of the present invention will be described below.

FIG. 1 shows a camera-integrated V to which the present invention is applied.
FIG. 3 is a block diagram illustrating a configuration of a TR. The VTR of FIG. 1 can record and reproduce image signals in the SD format and the SDL format described above.

First, a normal recording / reproducing operation will be described.

When recording in the SD format, the recording mode is set to the SD mode using the operation keys 127. Then, when recording start is instructed by the operation key 127, the recording is started.

A moving image signal obtained by the camera unit 101 is input to an input processing circuit 103. Input processing circuit 10
Reference numeral 3 indicates that when the recording mode is set to the SD mode, the luminance signal of the input moving image signal is set to 13.5 MH.
z, the color difference signal is sampled at 6.75 MHz and converted into a digital signal, and one frame is 720 in the horizontal direction.
An image signal of pixels × 480 pixels in the vertical direction is obtained and output to the image memory 105.

The image memory 105 is capable of storing image signals of a plurality of frames, in this embodiment, two frames, which have not been compression-encoded, and has a size of 8 pixels × 8 pixels in an order suitable for the processing of the digital signal processing circuit 107. It is read for each block of pixels. The digital signal processing circuit 107 performs DCT, quantization, and variable length coding on the image signal read from the image memory,
Write to 1.

The track memory 111 can store image signals encoded according to the SD format for a plurality of frames, in this embodiment, three frames.
The data of the T block is written. The recording circuit 113 reads out the image data stored in the track memory 111 at the timing specified by the microcomputer 125. Here, the recording circuit 113 reads out the image data of each macro block in the order according to the scanning order of the screen. Also, the recording circuit 11
3 generates the above-described system data according to the instruction of the microcomputer 125. Then, synchronization and ID data are added to these image data and system data to form a sync block, an error correction encoding process is performed for each recording data of one track, and a digital modulation process is performed to perform pilot modulation. The signal is multiplexed and output to the rotary head 119 via the switch 115.

The switch 115 selects data output from the recording circuit 113 and outputs the data to the rotary head 119 during recording.

On the other hand, the microcomputer 125 outputs a control signal to the servo circuit 131 in response to the instruction to start recording, and the capstan 133 so that the tape 121 runs stably at a predetermined speed V according to the SD format. Control.

The rotary head 119 forms a large number of helical tracks on the tape 121 whose traveling is controlled as described above, and records one frame of image data on ten tracks. FIG. 2 shows the recording tracks on the tape in the SD format.

As shown in FIG. 2, in the SD mode, one frame of image data is recorded on ten tracks.
Reference numeral 201 denotes a value of a track pair number recorded on each track, and reference numeral 203 denotes a frequency of a pilot signal recorded on each track. Reference numeral 205 denotes pilot frame information recorded in each track. In the SD mode, pilot frame information is recorded in two frames, that is, in a cycle of 20 tracks. Also, 2
Reference numeral 07 denotes the state of the video source control pack recorded on each track, and the recording position differs for each track as described above.

Reference numeral 135 denotes a track pair register (T
P register), which stores the information of the track pair number recorded by the recording circuit 113. Microcomputer 125
By checking the contents of the TP register 135, the phase of the currently recorded track can be detected.

The H / V generator 123 is a circuit for generating an internal synchronization signal necessary for the processing of the digital signal processing circuit 107, and generates a horizontal synchronization signal H and a vertical synchronization signal V.

Next, the operation at the time of reproducing the SD format data will be described.

When a reproduction instruction is given by the operation key 129, the microcomputer 125 outputs a control signal to the servo circuit 131, and rotates the capstan 133 so as to convey the tape 121 at a speed V corresponding to the SD format. Control.

Then, the tape 1 is rotated by the rotating head 119.
The data is reproduced from 21 and output to the reproduction circuit 115 via the switch 115. Here, the switch 115 is controlled by the microcomputer 125, and at the time of reproduction,
9 is output to the reproducing circuit 117.

The reproduction circuit 117 demodulates the reproduced data and corrects errors in the reproduced data. Further, it detects the synchronization and ID data in the reproduction data, writes the image data into the track memory 111, and outputs the system data and other data to the microcomputer 125. Here, the data output to the microcomputer 125 also includes information indicating the recording format, and the microcomputer 125 can detect the recording format of the image data based on this information.

The reproduced image data stored in the track memory 111 is transmitted to the digital signal processing circuit 1 at a predetermined timing.
07. The digital signal processing circuit 107 subjects the image data read from the track memory 111 to a decoding process reverse to that at the time of recording, and outputs the result to the image memory 103. The image signal stored in the image memory 103 is read by the output circuit 129 and output to an external monitor or the like.

Next, the recording / reproducing operation in the SDL format will be described.

The SDL mode is set by the operation key 127, and when the recording start is instructed, the recording in the SDL format starts.

The image signal output from the camera unit 101 is processed by the input processing circuit 103 according to the SDL format. That is, the input processing circuit 103 converts the luminance signal of the input image signal into 13.5 MHz and the color difference signal into 6.
After sampling at 75 MHz, it is further filtered to 10.125 MHz, 3.375 MHz, respectively.
, And one frame is 540 in the horizontal direction.
An image signal of 480 pixels in the vertical direction is obtained. this is,
This corresponds to 2/3 of the information amount of the SD format.

The image signal output from the input processing circuit 103 is stored in the image memory 105, and is read out in DCT block units in an order suitable for processing by the digital signal processing circuit 107.

The digital signal processing circuit 107 applies a DC signal to each DCT block as in the case of the SD format.
T, quantization, and variable length coding are performed. At this time, the encoding process is performed such that the code amount per frame is ／ of the SD format.

As described above, in the SDL format, the amount of information is reduced by the input
/ 3, which is ／ in the encoding process of the digital signal processing circuit 107, so that the total amount of information in the SD format is (2/3 × ３) = １ ／.

The digital signal processing circuit 107 encodes the image signal as described above and writes it into the track memory 111. The recording circuit 113 reads out the image data stored in the track memory 111 at a timing according to a control signal from the microcomputer 125, adds synchronization and ID data, and performs error correction encoding processing in units of image data recorded on one track. Apply. As in the case of the SD mode, additional data such as system data is generated, and further subjected to digital modulation processing to multiplex a pilot signal and output to the rotary head 119 via the switch 115.

The microcomputer 125 includes a servo circuit 13
1 to the capstan 133 so that the tape 121 is stably conveyed at 1/2 speed in the SD mode, that is, V / 2 which is a conveying speed corresponding to the SDL format. Control the rotation speed.

The rotary head 119 forms a large number of helical tracks on the tape 121 using head elements arranged differently from those in the SD mode, and records one frame of image data on five tracks. The head element in the SDL format is described in Japanese Patent Application Laid-Open No. H11-328639.
The one described in Japanese Patent Application Laid-Open Publication No. H10-260 can be used. FIG. 3 shows a recording format on a tape in the SDL format.

Next, at the time of reproduction, the microcomputer 125
Outputs a control signal to the servo circuit 131 upon receiving a reproduction instruction from the operation key 127, and the tape 121
The capstan 133 is controlled so that the paper is transported at a transport speed V / 2 corresponding to the format.

The rotary head 119 reproduces data from the tape 121 and outputs the data to the reproducing circuit 117 via the switch 115. The playback circuit 117 detects synchronization and ID data from the playback data, and writes the playback image data to the track memory 111 according to the ID data, as in the SD mode. Further, the reproducing circuit 117 detects system data from the reproduced data and outputs the system data to the microcomputer 125.

The digital signal processing circuit 107 reads out the reproduction data stored in the track memory 111, and
A decoding process according to the L format is performed, and output to the image memory 103. The image signal stored in the image memory 103 is read by the output circuit 129 and output to a device such as an external monitor.

The monitor 109 displays an image according to the output image signal from the camera unit 101 in the recording mode, and displays an image according to the image signal read from the image memory 103 in the reproduction mode.

Next, the operation at the end of recording in the SDL format will be described.

FIG. 4 is a timing chart for explaining the operation of VTR 100 at the end of recording.

In FIG. 4A, reference numeral 401 denotes a recording end signal generated inside the microcomputer 125 when a recording stop instruction is given by the operation key 127 during recording in the SDL format. After reaching the level, the recording end operation is started.

In FIG. 4B, reference numeral 402 denotes the H / V generator 123.
The signal 403 in FIG. 4C is a count value of an internal counter of the microcomputer 125 which counts this V signal and circulates with a numerical value of 0 to 3, and performs digital signal processing based on the count value. The processing phase of the circuit 107 is determined, and system data such as a track pair that circulates in a two-frame cycle is generated.

4D is a switching pulse (SWP) for selecting a plurality of magnetic head elements, and 405 in FIG. 4E is a track pair number value stored in the TP register at the time of recording. Although synchronized with the V signal 402, the amount of delay is determined at the start of recording,
It differs every recording start. 406 in FIG. 4F is VT
The change of the recording / recording pause mode of R is shown.

At the end of recording, the microcomputer 125 checks the value of the TP register 135 after the recording end signal 401 goes high at the timing of 407. Then, a control signal is output to the digital signal processing circuit 107, the track memory 111, the recording circuit 113, and the switch 115 at the timing 408 of the next track of the track in which the value of the TP register becomes 4 continuously for two track periods. , Stop recording. Then, the microcomputer 125 outputs a control signal to the servo circuit 131, and the capstan 1
The conveyance of the tape 121 by 33 is stopped.

As described above, according to the present embodiment, the recording is stopped at the next timing when the recorded track pair number becomes 4 consecutively. Therefore, when the recording in the SDL format is completed, two frames are always recorded. Recording can be ended at the break position.

When recording in the SD format is completed, control is performed so that recording is stopped at one frame of data, that is, at the position of a break of 10 tracks, so that recording in the SD format and recording in the SDL format are completed. The control operation by the microcomputer 125 can be shared between the end and the end.

Next, a second embodiment of the present invention will be described.

In the above-described embodiment, the timing of the break of two frames is detected based on the value of the TP register. In the present embodiment, the timing of the break of two frames is detected based on the read address of the track memory 111. Is what you do.

FIG. 5 is a diagram schematically showing the configuration of the track memory 111. As described above, the track memory 1
11 can store data of three frames encoded according to the SD format. In FIG.
The state of the frame is shown.

In FIG. 5, reference numeral 501 denotes the number of the memory bank of the track memory, and each bank can store data encoded in one frame in the SD format. In this embodiment, the write state and the read state can be switched for each bank.

Reference numeral 502 denotes an address corresponding to a track.
For example, the data stored at address 0 is recorded in the first track of 10 tracks in which one frame is recorded in the SD format. Therefore, during recording in the SDL format, data of two frames is stored in each bank.

Reference numeral 503 denotes a switch for switching the write bank to the track memory 111. The data output from the digital signal processing circuit 107 is supplied during recording, and the data output from the reproduction circuit 117 is supplied during reproduction. Reference numeral 504 denotes a switch for selecting a bank to be read from the track memory 111. The switch 504 outputs data to the recording circuit 113 during recording, and outputs data to the digital signal processing circuit 107 during reproduction. The switches 503 and 504 are controlled to be switched by the microcomputer 125.

For example, at the time of recording, the data stored at the designated address is read out by increasing the address 502 for each SWP and output to the recording circuit 113. In this embodiment, the read address at this time is monitored by the microcomputer 125, and it can be detected whether or not data is currently recorded on the main track in the frame.

FIG. 6 is a block diagram showing the configuration of a digital VTR according to the present embodiment.
Address register 137 instead of TP register 135
It has the same configuration except that. And FIG.
Is the same as the VTR of FIG. 1 except for the processing at the end of recording, and the description of the basic operation at the time of recording and reproduction is omitted. Hereinafter, a process at the end of recording in the SDL format will be described.

FIG. 7 is a timing chart showing the operation at the end of recording in the SDL format according to the present embodiment. 7 (a) to 7 (d) and FIG. 7 (f).
04 and 706 are signals 701 to 701 shown in FIG.
Similar to 704 and 706.

In FIG. 7E, reference numeral 705 denotes a track memory 111 stored in the address register 137 at the time of recording.
Although the read address is synchronized with the V signal 702, the amount of delay is determined at the start of recording, and differs every time recording is started.

At the end of the recording, the microcomputer 125 checks the value of the address register 137 after the recording end signal 701 becomes high level. Then, at timing 707 of the track following the track whose address register value has become "9", a control signal is output to the digital signal processing circuit 107, the track memory 111, the recording circuit 113, and the switch 115, and recording is stopped. I do. Then, the microcomputer 125 outputs a control signal to the servo circuit 131, and stops the transport of the tape 121 by the capstan 133.

As described above, according to the present embodiment, the recording is stopped at the timing after the read address of the track memory is 9, that is, at the timing next to the last track of the 10 tracks in which data of 2 frames are recorded. , The recording can be always terminated at the position of the break of two frames.

In the above embodiment, the present invention is applied to a DV
The case where the present invention is applied to a digital VTR conforming to a format has been described. In addition, for example, n (n
Similarly, when image data is recorded on m (m is an integer of 1 or more) tracks per frame together with additional information such as system data that changes cyclically in a frame period. The present invention can be applied.

In the second embodiment, the address of the track memory is used to detect the processing phase of the image signal in the two-frame period. It is also possible to use an address or the like.

[0067]

As described above, according to the present invention, even when the additional information is cyclically recorded in the n-frame period together with the image signal, the reproduced data is not disturbed at the recording end portion.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital VTR to which the present invention is applied.

FIG. 2 is a diagram showing a recording format on a tape by the apparatus of FIG. 1;

FIG. 3 is a diagram showing a recording format on a tape by the apparatus of FIG. 1;

FIG. 4 is a timing chart showing an operation at the end of recording by the apparatus of FIG. 1;

FIG. 5 is a diagram showing a configuration of a track memory of the device of FIG. 6;

FIG. 6 is a block diagram showing another configuration of a digital VTR to which the present invention is applied.

FIG. 7 is a timing chart showing an operation at the end of recording by the apparatus of FIG. 6;

Claims (6)

[Claims] 1. A signal processing means for periodically processing an input image signal in an n-frame period (n is an integer of 2 or more), and an additional unit for generating additional information which changes periodically in the n-frame period of the image signal. Information generating means, forming a number of tracks on a recording medium on a tape using a rotary head, and converting the image signal output from the signal processing means and the additional information generated by the additional information generating means into one frame Recording means for recording on m tracks (m is an integer of 1 or more) for each of the n × m tracks in which the n-frame image signal is cyclically recorded in response to a recording end instruction. And a control means for controlling the recording means so as to end the recording at the last track. 2. The control device according to claim 1, further comprising: detecting means for detecting a track phase of the tracks recorded by the recording means in the n × m tracks based on the additional information recorded by the recording means. 2. A recording apparatus according to claim 1, wherein said means controls said recording means based on a detection result of said detection means. 3. The signal processing means includes a memory for storing the image signals for the n frames, and the control means controls the recording means to end recording at the last track based on a read address of the memory. The recording apparatus according to claim 1, wherein the recording apparatus is controlled. 4. The method according to claim 1, wherein the additional information is 2 in the n-frame period.
2. The recording apparatus according to claim 1, wherein the information is track pair number information that increases by a predetermined value for each track. 5. A processing phase detecting means for detecting a processing phase of the signal processing means within the n frame period, wherein the control means ends recording at the last track based on a detection result of the processing phase detecting means. 2. The recording apparatus according to claim 1, wherein the recording unit is controlled to perform the recording. 6. The signal processing means is an HD digital VCR.
The input image signal is encoded according to the SD high compression specification specified by the council, and the recording means records the encoded image signal on the tape-shaped recording medium according to the SD high compression specification. Claim 1
The recording device according to any one of the preceding claims.